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may 2008 rev 6 1/77 1 STA323W 2.1-channel high-effici ency digital audio system features ! wide supply voltage range (10 v - 36 v) ! three power output configurations ? 2x10w + 1 x20w ?2x20w ?1x40w ! thermal protection ! under-voltage protection ! short-circuit protection ! powerso-36 slug down package ! 2.1 channels of 24-bit ddx ? ! 100-db snr and dynamic range ! 32 khz to 192 khz input sample rates ! digital gain/attenuation +48 db to -80 db in 0.5-db steps ! four 28-bit user programmable biquads (eq) per channel ! i 2 c control ! 2-channel i 2 s input data interface ! individual channel and master gain/attenuation ! individual channel and master soft and hard mute ! individual channel volume and eq bypass ! ddx ? pop free operation ! bass/treble tone control ! dual independent programmable limiters/compressors ! automodes? settings for: ? 32 preset eq curves ? 15 preset crossover settings ? auto volume controlled loudness ? 3 preset volume curves ? 2 preset anti-clipping modes ? preset night-time listening mode ? preset tv agc ! input and output channel mapping ! am noise-reduction and pwm frequency shifting modes ! soft volume update and muting ! auto zero detect and invalid input detect muting selectable ddx ? ternary or binary pwm output plus variable pwm speeds ! selectable de-emphasis ! post-eq user programmable mix with default 2.1 bass-management settings ! variable max power correction for lower full-power thd ! four output routing configurations ! selectable clock input ratio ! 96 khz internal processing sample rate, 24 to 28-bit precision ! video application supports 576 * fs input mode table 1. device summary order code package STA323W powerso-36 (slug down) STA323W13tr powerso-36 in tape & reel powerso-36 (slug down) www.st.com
contents STA323W 2/77 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 eq processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 general interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 dc electrical specifications (3.3 v buffers) . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 output power against supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 stereo mode, operation with v cc = 26 v, 8 ? load . . . . . . . . . . . . . . . . 23 5.2.2 stereo mode, operation with v cc = 18.5 v . . . . . . . . . . . . . . . . . . . . . . 24 5.2.3 half-bridge binary mode, operation with vcc = 18.5 v . . . . . . . . . . . . . 28 6i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 configuration register a (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1.1 master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STA323W contents 3/77 7.1.2 interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1.3 thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.4 thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.5 fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 configuration register b (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.1 serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.2 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.3 delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 configuration register c (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.1 ddx? power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.2 ddx ? variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 configuration register d (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4.1 high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4.2 de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4.3 dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4.4 post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4.5 biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4.6 dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 45 7.4.7 zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5 configuration register e (address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.1 max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.2 max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.3 am mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.4 pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.5 zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.6 soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6 configuration register f (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.7 volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.1 master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.2 channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.3 volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8 automodes? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.8.1 automodes? eq, volume, gc (address 0x0b) . . . . . . . . . . . . . . . . . . . 52 7.8.2 automodes? am/pre-scale/bass management scale (address 0x0c) . 53 7.8.3 preset eq settings (address 0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
contents STA323W 4/77 7.9 channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.9.1 channel 1 configuration (address 0x0e) . . . . . . . . . . . . . . . . . . . . . . . . 55 7.9.2 channel 2 configuration (address 0x0f) . . . . . . . . . . . . . . . . . . . . . . . . 55 7.9.3 channel 3 configuration (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . 56 7.10 tone control (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.11 dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.11.1 limiter 1 attack/release threshold (address 0x12) . . . . . . . . . . . . . . . . . 57 7.11.2 limiter 1 attack/release threshold (address 0x13) . . . . . . . . . . . . . . . . . 57 7.11.3 limiter 2 attack/release rate (address 0x14) . . . . . . . . . . . . . . . . . . . . . 57 7.11.4 limiter 2 attack/release threshold (address 0x15) . . . . . . . . . . . . . . . . . 58 7.11.5 dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.11.6 anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.11.7 dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 user-programmable settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.1 eq - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.2 pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3 post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.4 mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.5 calculating 24-bit signed fractional numbers from a db value . . . . . . . . . 65 8.6 user defined coefficient ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.6.1 coefficient address register 1 (address 0x16) . . . . . . . . . . . . . . . . . . . . 65 8.6.2 coefficient b1data register bits 23:16 (address 0x17) . . . . . . . . . . . . . . 65 8.6.3 coefficient b1data register bits 15:8 (address 0x18) . . . . . . . . . . . . . . . 65 8.6.4 coefficient b1data register bits 7:0 (address 0x19) . . . . . . . . . . . . . . . . 65 8.6.5 coefficient b2 data register bits 23:16 (address 0x1a) . . . . . . . . . . . . . 65 8.6.6 coefficient b2 data register bits 15:8 (address 0x1b) . . . . . . . . . . . . . . 66 8.6.7 coefficient b2 data register bits 7:0 (address 0x1c) . . . . . . . . . . . . . . . 66 8.6.8 coefficient a1 data register bits 23:16 (address 0x1d) . . . . . . . . . . . . . 66 8.6.9 coefficient a1 data register bits 15:8 (address 0x1e) . . . . . . . . . . . . . . 66 8.6.10 coefficient a1 data register bits 7:0 (address 0x1f) . . . . . . . . . . . . . . . 66 8.6.11 coefficient a2 data register bits 23:16 (address 0x20) . . . . . . . . . . . . . 66 8.6.12 coefficient a2 data register bits 15:8 (address 0x21) . . . . . . . . . . . . . . 66 8.6.13 coefficient a2 data register bits 7:0 (address 0x22) . . . . . . . . . . . . . . . 67 8.6.14 coefficient b0 data register bits 23:16 (address 0x23) . . . . . . . . . . . . . 67 8.6.15 coefficient b0 data register bits 15:8 (address 0x24) . . . . . . . . . . . . . . 67
STA323W contents 5/77 8.6.16 coefficient b0 data register bits 7:0 (address 0x25) . . . . . . . . . . . . . . . 67 8.6.17 coefficient write control register (address 0x26) . . . . . . . . . . . . . . . . . . 67 8.7 reading and writing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.1 reading a coefficient from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.2 reading a set of coefficients from ram . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.3 writing a single coefficient to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.4 writing a set of coefficients to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.8 variable max power correction (address 0x27-0x28) . . . . . . . . . . . . . . . . 70 8.9 fault detect recovery (address 0x2b - 0x2c) . . . . . . . . . . . . . . . . . . . . . . 71 8.10 status indicator register (address 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.1 thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.2 fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.3 pll unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 75 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
list of tables STA323W 6/77 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. component selection ?table a? - full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. component selection "table b" - binary half-bridge operation . . . . . . . . . . . . . . . . . . . . . . 12 table 4. component selection "table c" - mono operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. general interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 10. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. power electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15. ir and mcs settings for input sample rate and clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 18. thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. supported serial audio input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 23. serial input data timing characteristics (fs = 32 to 192 khz). . . . . . . . . . . . . . . . . . . . . . . . 42 table 24. delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 25. channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26. ddx? power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. ddx? output modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 28. ddx? compensating pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 29. high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 30. de-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 31. dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 32. post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 33. biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 34. dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 35. zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 36. max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 37. max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 38. am mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 39. pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 40. pwm output speed selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 41. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 42. soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 43. output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 44. output configuration selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 45. invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 46. binary clock loss detection enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 47. auto-eapd on cloc k loss enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 48. software power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STA323W list of tables 7/77 table 49. external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 50. master volume offset as a function of mv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 51. channel volume as a function of cxv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 52. automodes? eq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 53. automodes? volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 54. automodes? gain compression/limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 55. amps - automodes? auto pre scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 56. automodes? am switching enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 57. automodes? am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 58. automodes? crossover setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 59. crossover frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 60. preset eq selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 61. channel limiter mapping selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 62. channel pwm output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 63. tone control boost/cut selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 64. limiter attack rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 65. limiter release rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 66. limiter attack - threshold selection (ac-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 67. limiter release threshold selection (ac-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 68. limiter attack - threshold selection (drc-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 69. limiter release threshold selection (drc-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 70. ram block for biquads, mixing, and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 71. thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 72. fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 73. pll unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 74. powerso-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 75. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
list of figures STA323W 8/77 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. channel signal flow diagram through the eq block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. output power stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. schematic for 2 (half-bridge) channels + 1 (full-bridge) channel . . . . . . . . . . . . . . . . . . . . 12 figure 6. power schematic for 2 (full-bridge) channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. power schematic for 1 mono parallel channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. package pins (viewed from top of device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. recommended power up and power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. stereo mode - output power vs. supply voltage, thd+n = 10% . . . . . . . . . . . . . . . . . . . . 21 figure 13. output power vs. supply for stereo bridge, thd+n=1% . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. half-bridge binary mode output power vs. supply, thd+n=10% . . . . . . . . . . . . . . . . . . . 22 figure 15. half-bridge binary mode output power vs. supply voltage, thd+n=1% . . . . . . . . . . . . . . 22 figure 16. typical efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. typical frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. fft -60 db, 1 khz output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. fft inter-modulation distortion 19 khz and 20 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20. frequency response, 1 w, btl, 8 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. channel separation, 1 w, btl stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22. thd vs. output power, btl, 1 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23. thd vs. frequency, 1 w output, stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24. thd vs. frequency, btl, 16 w output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25. fft 0 dbfs 1 khz, 8 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 26. fft 0 dbfs 1 khz, 6 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27. fft 0 dbfs 1 khz, 4 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 28. fft -60 dbfs 1 khz, 8 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 29. fft -60 dbfs 1 khz, 6 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 30. fft -60 dbfs 1 khz, 4 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 31. psrr btl, 500 mv ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 32. frequency response, 1 w, binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 33. channel separation, 1 w, half bridge binary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 34. thd+n vs. output power, single ended, 1 khz, half-bridge binary . . . . . . . . . . . . . . . . . . . 29 figure 35. thd vs. frequency, single ended, 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 36. thd vs. frequency, single ended, 8 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 37. fft 0 db, 1 khz, single ended, 2 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 38. fft 0 db, 1 khz, single ended, 3 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 39. fft 0 db, 1 khz, single ended, 4 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 40. fft -60 db, single ended, 1 khz, 2 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 41. fft -60 db, single ended, 1 khz, 4 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 42. fft -60 db, single ended, 1 khz, 3 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 43. psrr single ended, 500 mv ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 44. i 2 c write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 45. i 2 c read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 46. general serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 47. serial input and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 48. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STA323W list of figures 9/77 figure 49. biquad filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 50. mix/bass management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 51. powerso-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
description STA323W 10/77 1 description the STA323W is a single-chip audio system co mprising digital audio processing, digital amplifier control and a ddx ? power-output stage. the STA323W uses all-digital amplification to provide high-power, high-quality and high-efficiency. the STA323W power section consists of four independent half-bridges. these can be configured, by digital control, to operate in the following modes. " tw o channels, provided by two half-bridges, and a single full-bridge giving up to 2 x 10 w + 1 x 20 w of power output. " two channels, provided by two full-bridges, giving up to 2 x 20 w of power. " a single, parallel, full-bridge channel capable of high-current operation and giving 1 x 40w output. the STA323W also provides a full set of digital processing features. this includes up to four programmable 28-bit biquads (eq) per channel, and bass and treble tone control. automodes? enable a time-to-market advantage by substantially reducing the amount of software development needed for specific functi ons. these includes auto volume loudness, preset volume curves and preset eq settings. new advanced am radio-interference reduction modes are also provided. the serial audio data input interface accepts all existing formats, including the i 2 s. three channels of ddx ? processing are provided. this high-quality conversion from pcm audio to ddx patented 3-state pwm switching provides over 100 db of snr and dynamic range. figure 1. block diagram figure 2. channel signal flow diagram through the digital core quad half-bridge power stage ddx processing crossover, volume, limiter processing audio eq, mix, input, channel mapping and resampling serial data out1a power down out1b out2a out2b eapd fault twarn power down system timing clk i 2 c system control scl sda lrcki bicki sdi_12 channel mapping re-sampling ed processing i 2 s input mix ddx crossover filter volume limiter 4x interpol ddx output
STA323W description 11/77 1.1 eq processing two channels of input data (re-sampled if necessary) at 96 khz are provided to the eq processing block. in these blocks, up to four user-defined biquads can be applied to each of the two channels. pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be implemented by means of configuration parameter settings. the entire eq block can be bypassed for all channels simultaneously by setting the dspb bit to 1. the cxeqbp bits can also be used to bypass the eq functionality on a per channel basis. figure 3 shows the internal signal flow through the eq block. figure 3. channel signal flow diagram through the eq block 1.2 output options figure 4. output power stage configurations pre-scale high pass bq#1 re-sampled input tr e b l e bass filter to mix filter bq#2 bq#3 bq#4 de- emphasis filter if cxtcb = 0 btc: bass boost/cut ttc: treble boost/cut if demp = 1 4 biquads user defined if ameq = 00 preset eq if ameq = 01 auto loudness if ameq = 10 if hpb= 0 if dspb = 0 and cxeqb = 0 half bridge half bridge half bridge half bridge channel 1 channel 2 out2a out2b out1a out1b half bridge half bridge half bridge half bridge channel 2 channel 3 out2a out2b out1a out1b channel 1 half bridge half bridge half bridge half bridge channel 3 out2a out2b out1a out1b 2-channel (full bridge) configuration, register bits ocfg[1:0] = 00 2.1-channel configuration, register bits ocfg[1:0] = 01 1-channel mono-parallel configuration, register bits ocfg[1:0] = 11 the setup register is configuration register f (address 0x05) on page 48
applications STA323W 12/77 2 applications figure 5. schematic for 2 (half-bridge) channels + 1 (full-bridge) channel table 2. component selection ?table a? - full-bridge operation load inductor capacitor 4 ? 10 h1.0 f 6 ? 15 h 470 nf 8 ? 22 h 470 nf table 3. component selection "table b" - binary half-bridge operation load inductor capacitor 4 ? 22 h 680 nf 6 ? 33 h 470 nf 8 ? 47 h 390 nf table 4. component selection "table c" - mono operation load inductor capacitor 2 ? 4.7 h2.0 f 3 ? 6.8 h1.0 f 4 ? 10 h1.0 f sub_gnd sub_gnd n.c. out2b vcc2b n.c. gnd2b gnd2a vcc2a out2a out1b vcc1b gnd1b gnd1a n.c. vcc1a out1a gnd_clean gnd_reg vcc_sign vss vdd gnd bicki lrcki sdi vdda gnda xti pll_filter reserved sda scl reset config vl vdd_reg STA323W
STA323W applications 13/77 figure 6. power schematic for 2 (full-bridge) channels figure 7. power schematic for 1 mono parallel channel sub_gnd sub_gnd n.c. out2b vcc2b n.c. gnd2b gnd2a vcc2a out2a out1b vcc1b gnd1b gnd1a n.c. vcc1a out1a gnd_clean gnd_reg vcc_sign vss vdd gnd bicki lrcki sdi vdda gnda xti pll_filter reserved sda scl reset config vl vdd_reg STA323W sub_gnd sub_gnd n.c. out2b vcc2b n.c. gnd2b gnd2a vcc2a out2a out1b vcc1b gnd1b gnd1a n.c. vcc1a out1a gnd_clean gnd_reg vcc_sign vss vdd gnd bicki lrcki sdi vdda gnda xti pll_filter reserved sda scl reset config vl vdd_reg STA323W
pin out STA323W 14/77 3 pin out 3.1 pin numbering figure 8. package pins (viewed from top of device) table 5. pin list pin type name description 1 i/o sub_gnd ground 2 n.c. n.c. not connected 3 o out2b output half bridge 2b 4 i/o vcc2b positive supply 5 n.c. n.c. not connected 6 i/o gnd2b negative supply 7 i/o gnd2a negative supply 8 i/o vcc2a positive supply 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b 11 i/o vcc1b positive supply 12 i/o gnd1b negative supply 13 i/o. gnd1a negative supply 14 n.c. n.c. not connected 15 i/o vcc1a positive supply 16 o out1a output half bridge 1a vcc_sign vss vdd gnd bicki lrcki sdi vdda gnda xti pll_filter reserved sda scl reset config vl vdd_reg sub_gnd n.c. out2b vcc2b n.c. gnd2b gnd2a vcc2a out2a out1b vcc1b gnd1b gnd1a n.c. vcc1a out1a gnd_clean gnd_reg 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
STA323W pin out 15/77 3.2 pin description out1a, 1b, 2a and 2b (pins 16, 10, 9 and 3) the half-bridge pwm outputs 1a, 1b, 2a and 2b provide the inputs signals to the speakers. reset (pin 22) driving reset low sets all outputs low and re turns all register settings to their default (reset) values. the reset is asynchronous to the internal clock. sda, scl (pins 24, 23) the sda (i 2 c data) and scl (i 2 c clock) pins operate according to the i 2 c specification (see chapter 6 on page 33 .) fast-mode (400 kb/s) i 2 c communication is supported. vdda, gnda (pins 29,28) the phase locked loop power is applied here. this +3.3v supply must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the pll circuit. 17 i/o gnd_clean reference ground 18 i/o gnd_reg substrate ground 19 i/o vdd_reg logic supply 20 i/o vl logic supply to power section 21 i config logic levels 22 i reset reset 23 i scl i 2 c serial clock 24 i/o sda i 2 c serial data 25 - reserved reserved test pin must be connected to ground 26 i pll_filter connection to pll filter 27 i xti pll input clock 28 i/o gnda analog ground 29 i/o vdda analog supply 3.3 30 i sdi_12 i 2 s serial data channels 1 and 2 31 i/o lrcki i 2 s left/right clock, 32 i bicki i 2 s serial clock 33 i/o gnd digital ground 34 i/o vdd digital supply 3.3 v 35 i/o vss 5 v regulator referred to vcc 36 i/o vcc_sign 5 v regulator referred to ground table 5. pin list (continued) pin type name description
pin out STA323W 16/77 clk (pin 27) this is the master clock input used by the digital core. the master clock must be an integer multiple of the lr clock frequency. typically, the master clock frequency is 12.288 mhz (256 * fs) for a 48khz sample rate; it is the default setting at power-up. care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, su ch as inability to communicate. pll_filter (pin 26) this is the connection for the external filter components for the pll loop compensation. refer to the schematic diagram figure 7: power schematic for 1 mono parallel channel on page 13 for the recommended circuit. bicki (pin 32) the serial or bit clock input is for framing each data bit. the bit clock frequency is typically 64 * fs using i 2 s serial format. sdi (pin 30) this is the serial data input where pcm audio information enters the device. six format choices are available including i 2 s, left or right justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. lrcki (pin 31) the left/right clock input is for data word framing. the clock frequency is at the input sample rate, fs.
STA323W electrical specifications 17/77 4 electrical specifications 4.1 general interface specifications operating conditions v dd33 = 3.3 v 0.3 v, t amb = 25 c unless otherwise specified. table 6. absolute maximum ratings symbol parameter value unit v dd_3.3 3.3 v i/o power supply -0.5 to 4 v v i voltage on input pins -0.5 to (vdd+0.5) v v o voltage on output pins -0.5 to (vdd+0.5) v t stg storage temperature -40 to +150 c t amb ambient operating temperature -40 to +85 c v cc dc supply voltage 40 v v max maximum voltage on pin 20 5.5 v table 7. thermal data symbol parameter min typ max unit r thj-case thermal resistance junction to case (thermal pad) 2.5 c/w t j-sd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t h-sd thermal shut-down hysteresis 25 c table 8. recommended dc operating conditions symbol parameter value unit v dd_3.3 i/o power supply 3.0 to 3.6 v t j operating junction temperature -40 to +125 c table 9. general interface electrical characteristics symbol parameter test condition min. typ. max. unit i il leakage current: low level input, no pull-up v i = 0 v (1) 1. the leakage currents are generally very small < 1 na. the values given here are maximum after an electrostatic stress on the pin. 1 a i ih leakage current: high level input, no pull-down v i = v dd33 (1) 2 a i oz leakage current: 3-state output without pull-up/down v i = v dd33 (1) 2 a v esd electrostatic protection (human body model) leakage < 1 a2000 v
electrical specifications STA323W 18/77 4.2 dc electrical specifications (3.3 v buffers) operating conditions v dd33 = 3.3 v 0.3 v, t amb = 25 c unless otherwise specified 4.3 power electrical specifications operating conditions v dd33 = 3.3 v 0.3 v, v l = 3.3 v, v cc =30v, t amb = 25 c unless otherwise specified. table 10. dc electrical characteristics symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v hyst schmitt trigger hysteresis 0.4 v v ol low level output ioi = 2ma 0.15 v v oh high level output ioh = -2ma vdd - 0.15 v table 11. power electrical characteristics symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet r dson id = 1 a 200 270 m ? i dss power pchannel/nchannel leakage i dss vcc = 35 v 50 a g n power pchannel r dson matching id = 1 a 95 % g p power nchannel r dson matching id = 1 a 95 % dt_s low current dead time (static) see test circuits , figure 9 and figure 10 10 20 ns t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load, figure 9 and figure 10 25 ns t f fall time resistive load, figure 9 and figure 10 25 ns v cc supply voltage 8 36 v v l low logical state voltage v l = 3.3 v 0.8 v v h high logical state voltage v l = 3.3 v 1.7 v i vcc- pwrdn supply current from vcc in pwrdn pwrdn = 0 3 ma i vcc-hiz supply current from vcc in 3- state v cc = 30 v, 3-state 22 ma
STA323W electrical specifications 19/77 4.4 timing specifications figure 9. test circuit 1 i vcc supply current from v cc in operation (both channel switching) input pulse width = 50% duty, switching frequency = 384 khz, no lc filters; 80 ma i out-sh overcurrent protection threshold (short circuit current limit) 46 a v uv under voltage protection threshold 7v t pw-min output minimum pulse width no load 70 150 ns p o output power thd = 10%, r l = 8 ? , v cc = 18 v 20 w p o output power thd = 1%, r l = 8 ? , v cc = 18 v 16 w table 11. power electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit table 12. timing characteristics symbol parameter test condition min. typ. max. unit t reset hold time for reset (pin 22) active low rest 100 ns f vco vco free run frequency no clock applied to xti 18 28 mhz dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy m58 m57 outxy gnd vdc = vcc/2 v67 r 8 ? + -
electrical specifications STA323W 20/77 figure 10. test circuit 2 4.5 power supply and control sequencing figure 11 shows the recommended power-up and power-down sequencing. the "time zero" reference point is taken where v cc crosses the under voltage lockout threshold. figure 11. recommended power up and power down sequence high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=4 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=1.5a iout=1.5a q4 q1 q3 m64 inb m63 d06au1651 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in figure l68 10 l67 10 outa
STA323W electrical characteristics curves 21/77 5 electrical characteristics curves 5.1 output power against supply voltage figure 12. stereo mode - output power vs. supply voltage, thd+n = 10% figure 12 shows the full-scale output power (0 dbfs digital input with unity amplifier gain) as a function of power supply voltage for 4, 6, and 8 ? loads in either ddx ? mode or binary full bridge mode. output power is constrain ed for higher impedance loads by the maximum voltage limit of the STA323W and by the over-current protection limit for lower impedance loads. the minimum threshold for the over-current protection circuit of the STA323W is 4 a (at 25 c) but the typical threshold is 6 a for the device. the solid curves shows the typical output power capability of the device. the dotted curves shows the output power capability constrained to the minimum current specification of the STA323W. the output power curves assume proper thermal management of the power device's internal dissipation. figure 13. output power vs. supply for stereo bridge, thd+n=1% 80 70 60 50 40 4ohm 6ohm 8ohm 30 20 10 10 12 14 16 18 20 22 24 26 power supply voltage (vdc) output power (w) supply voltage (v) output power (w) - btl 1% thd 0 10 20 30 40 50 60 10 15 20 25 30 16ohm 8 ohm 6 ohm 4 ohm
electrical characteristics curves STA323W 22/77 figure 13 shows the mono mode output power as a function of power supply voltages for loads of 4, 6, 8 and 16 ? . the same current limits as those given for figure 12 apply, except output current is 8 a minimum, with 12 a typical in the mono-bridge configuration. the solid curves show typical performance and dashed cu rves depict the minimum current limit. the output power curves assume proper thermal management of the power device internal dissipation. figure 14. half-bridge binary mode output power vs. supply, thd+n=10% figure 14 shows the output power as a function of power supply voltages for loads of 4, 6, and 8 ? when the STA323W is operated in a half-bridge binary mode. the curves depict typical performance. minimum current limit is not reached for these combinations of voltage and load impedance. the output power curves assume proper thermal management of the power device internal dissipation. figure 15. half-bridge binary mode output power vs. supply voltage, thd+n=1% 10 25 20 15 4ohm 6ohm 8ohm 5 0 10 12 14 16 18 20 22 2 26 power supply voltage (vdc) output power (w) curves measured at f = 1 khz and using a blocking capacitor of 330 f supply voltage (v) output power (w) 0 5 10 15 20 25 10 15 20 25 30 8 ohm 4 ohm 3 ohm 2 ohm curves measured at f = 1 khz and using a blocking capacitor of 330 f
STA323W electrical characteristics curves 23/77 5.2 audio performance 5.2.1 stereo mode, operation with v cc = 26 v, 8 ? load figure 16. typical efficiency figure 17. typical frequency response figure 18. fft -60 db, 1 khz output 100 90 80 70 60 50 40 30 20 10 0 01020 30 40 50 60 70 80 total output power (watts )
electrical characteristics curves STA323W 24/77 figure 19. fft inter-modulation distortion 19 khz and 20 khz 5.2.2 stereo mode, operation with v cc = 18.5 v figure 20. frequency response, 1 w, btl, 8 ? figure 21. channel separation, 1 w, btl stereo mode 8ohm -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr a 4 ohm 6ohm 8ohm 4ohm -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr a
STA323W electrical characteristics curves 25/77 figure 22. thd vs. output power, btl, 1 khz figure 23. thd vs. frequency, 1 w output, stereo mode figure 24. thd vs. frequency, btl, 16 w output 8ohm 6ohm 4ohm 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 100m 50 200m 500m 1 2 5 10 20 w 6ohm 8ohm 4ohm 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 8ohm 6ohm 4ohm
electrical characteristics curves STA323W 26/77 figure 25. fft 0 dbfs 1 khz, 8 ? figure 26. fft 0 dbfs 1 khz, 6 ? figure 27. fft 0 dbfs 1 khz, 4 ? -140 +40 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -140 +40 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -140 +40 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr
STA323W electrical characteristics curves 27/77 figure 28. fft -60 dbfs 1 khz, 8 ? figure 29. fft -60 dbfs 1 khz, 6 ? figure 30. fft -60 dbfs 1 khz, 4 ? -160 +40 -140 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -160 +40 -140 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -160 +40 -140 -120 -100 -80 -60 -40 -20 +0 +20 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr
electrical characteristics curves STA323W 28/77 figure 31. psrr btl, 500 mv ripple 5.2.3 half-bridge binary mode , operation with vcc = 18.5 v figure 32. frequency response, 1 w, binary half-bridge mode figure 33. channel separation, 1 w, half bridge binary 6ohm 8 ohm 4 ohm -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 200 30 40 50 60 70 80 90 100 hz t t dbr frequency (hz) -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 20 20k 50 100 200 500 1k 2k 5k 10k 3ohm 2ohm 4ohm dbr a -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 8ohm 4 ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr a
STA323W electrical characteristics curves 29/77 figure 34. thd+n vs. output power, single ended, 1 khz, half-bridge binary figure 35. thd vs. frequency, single ended, 1 w figure 36. thd vs. frequency, single ended, 8 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 100m 50 200m 500m 1 2 5 10 20 w 4ohm 3 ohm 2 ohm 2ohm 3ohm 4ohm 0.01 0.5 0.02 0.03 0.04 0.05 0.06 0.08 0.1 0.2 0.3 0.4 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 2ohm 3ohm 4ohm 0.01 5 0.02 0.05 0.1 0.2 0.5 1 2 % 20 20k 50 100 200 500 1k 2k 5k 10k hz
electrical characteristics curves STA323W 30/77 figure 37. fft 0 db, 1 khz, single ended, 2 ? figure 38. fft 0 db, 1 khz, single ended, 3 ? figure 39. fft 0 db, 1 khz, single ended, 4 ? -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 +10 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 +10 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 +10 20 20k 50 100 200 500 1k 2k 5k 10k dbr hz -110
STA323W electrical characteristics curves 31/77 figure 40. fft -60 db, single ended, 1 khz, 2 ? figure 41. fft -60 db, single ended, 1 khz, 4 ? figure 42. fft -60 db, single ended, 1 khz, 3 ? -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 +10 20 20k 50 100 200 500 1k 2k 5k 10k dbr hz -110 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 -130 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k hz dbr -130 -140
electrical characteristics curves STA323W 32/77 figure 43. psrr single ended, 500 mv ripple +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 200 30 40 50 60 70 80 90 100 hz dbr a -100 3 ohm 4 ohm 2 ohm
STA323W i 2 c bus specification 33/77 6 i 2 c bus specification the STA323W supports the i 2 c fast mode (400 kbit/s) protocol. this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA323W is always a slave device in all of its communications. 6.1 communication protocol data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. stop condition stop is identified by a low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA323W and the bus master. data input during the data input the STA323W samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 6.2 device addressing to start communication between the master and the STA323W, the master must initiate with a start condition. following this, the master sends 8 bits (msb first) on the sda line corresponding to the device select address and read or write mode. the 7 msbs are the device address identifiers, corresponding to the i 2 c bus definition. in the STA323W the i 2 c interface uses a device address of decimal 34 (binary 00100010). the 8th bit (lsb) identifies read or write operation, rw. this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA323W identifies the device address on the bus. if a match is found, it acknowledges the identification on the sda bus during the 9th bit time. the byte following the device identification byte is the internal space address.
i 2 c bus specification STA323W 34/77 6.3 write operation figure 44. i 2 c write procedure following the start condition the master sends a device select code with the rw bit set to 0. the STA323W acknowledges this and then the master writes the internal address byte. after receiving the internal byte addres s the STA323W again responds with an acknowledgement. byte write in the byte write mode the master sends one data byte. this is acknowledged by the STA323W. the master then terminates the transfer by generating a stop condition. multi-byte write the multi-byte write modes can start from any internal address. sequential data bytes are written to sequential addresses within the STA323W. the master generates a stop condition to terminate the transfer. 6.4 read operation figure 45. i 2 c read procedure current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA323W acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high
STA323W i 2 c bus specification 35/77 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the STA323W. the master acknowledges each data byte read and then generates a stop condition to terminate the transfer. random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA323W acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the STA323W again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA323W acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. random address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are then read from sequential addresses within the STA323W. the master acknowledges each data byte read and then generates a stop condition to terminate the transfer.
register descriptions STA323W 36/77 7 register descriptions you must not reprogram the register bits marked ?reserved?. it is important that these bits keep their default reset values. table 13. register summary address name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc reserved csz4 csz3 csz2 csz1 csz0 om1 om0 0x03 confd mme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame reserved mpc mpcv 0x05 conff eapd pwdn ecle ld te bcle ide ocfg1 ocfg0 0x06 mmute reserved reserved reserved reserved reserved reserved reserved mmute 0x07mvolmv7mv6mv5mv4mv3mv2mv1mv0 0x08 c1volc1v7c1v6c1v5c1v4c1v3c1v2c1v1c1v0 0x09 c2volc2v7c2v6c2v5c2v4c2v3c2v2c2v1c2v0 0x0a c3volc3v7c3v6c3v5c3v4c3v3c3v2c3v1c3v0 0x0b auto1 amps reserved amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x0c auto2 xo3 xo2 xo1 xo1 amam2 amam1 amam0 amame 0x0d auto3 reserved reserved reserved peq4 peq3 peq2 peq1 peq0 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x1f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3c1b7c1b6c1b5c1b4c1b3c1b2c1b1c1b0 0x1a b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x1b b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x1c b2cf3c2b7c2b6c2b5c2b4c2b3c2b2c2b1c2b0 0x1d a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16
STA323W register descriptions 37/77 7.1 configuration register a (address 0x00) 7.1.1 master clock select the STA323W supports sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, and 96 khz. therefore the internal clock is: " 32.768 mhz for 32 khz " 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz " 49.152 mhz for 48 khz, 96 khz, and 192 khz 0x1e a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x1f a1cf3c3b7c3b6c3b5c3b4c3b3c3b2c3b1c3b0 0x20 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x21 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x22 a2cf3c4b7c4b6c4b5c4b4c4b3c4b2c4b1c4b0 0x23 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x24 b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x25 b0cf3c5b7c5b6c5b5c5b4c5b3c5b2c5b1c5b0 0x26 cfud reserved reserved reserved reserved reserved reserved wa w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x2a reserved reserved reserved reserved reserved reserved reserved reserved reserved 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul reserved reserved reserved reserved reserved fault twarn table 13. register summary (continued) address name d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 14. master clock select bit r/w rst name description 0rw1mcs0 master clock select: selects the ratio between the input i 2 s sample frequency and the input clock. 1rw1mcs1 2rw0mcs2
register descriptions STA323W 38/77 the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (fs). the correlation between the input clock and the input sample rate is determined by the status of the mcsx bits and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. 7.1.2 interpolation ratio select the STA323W has variable interpolation (re-sampling) settings such that internal processing and ddx output rates remain consis tent. the first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. the ir bits determine the re-sampling ratio of this interpolation. table 15. ir and mcs settings for input sample rate and clock rate input sample rate fs (khz) ir mcs[2:0] 000 001 010 011 100 101 32, 44.1, 48 00 768 * fs 512 * fs 384 * fs 256 * fs 128 * fs 576 * fs 88.2, 96 01 384 * fs 256 * fs 192 * fs 128 * fs 64 * fs x 176.4, 192 1x 384 * fs 256 * fs 192 * fs 128 * fs 64 * fs x table 16. interpolation ratio select bit r/w rst name description 4:3 rw 00 ir[1:0] selects internal interpolation ratio based on input i 2 s sample frequency table 17. ir bit settings as a function of input sample rate input sample rate fs (khz) ir[1, 0] 1 st stage interpolation ratio 32 00 2 times over-sampling 44.1 00 2 times over-sampling 48 00 2 times over-sampling 88.2 01 pass-through 96 01 pass-through 176.4 10 down-sampling by 2 192 10 down-sampling by 2
STA323W register descriptions 39/77 7.1.3 thermal warning recovery bypass if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery determines if the adjustment is removed when thermal warning is negative. if twrb = 0 and twab = 0, then, when a thermal warning disappears, the gain adjustment determined by the thermal warning post-scale (default = -3 db) is removed and the gain is applied to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears, the thermal warning post-scale gain adjustment remains until twrb is changed to zero or the device is reset. 7.1.4 thermal warning adjustment bypass the STA323W on-chip power output block provides feedback to the digital controller by the power control block inputs. the twarn input is used to indicate a thermal warning condition. when twarn is active (set to 0 for a period greater than 400 ms) the power control block forces an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. once the therma l warning volume adjustment is applied, whether the gain is reapplied when twarn is inactive, depends on the twrb bit. 7.1.5 fault detect recovery bypass the ddx power block provides feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either over-current or thermal). when fault is active (set to 0), the power control block attempts a recovery from the fault by activating the 3-state output (setting it to 0 which directs the power output block to begin recovery). it holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (fdrc registers 0x29-0x2a), then toggles it back to 1. this sequence is repeated as long as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. table 18. thermal warning recovery bypass bit r/w rst name description 5rw1twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled table 19. thermal warning adjustment bypass bit r/w rst name description 6rw1twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled table 20. fault detect recovery bypass bit r/w rst name description 7 rw 0 fdrb 0: fault detector recovery enabled 1: fault detector recovery disabled
register descriptions STA323W 40/77 7.2 configuration register b (address 0x01) 7.2.1 serial audio i nput interface format 7.2.2 serial data interface the STA323W serial audio input interfaces with standard digital audio components and accepts several different serial data formats. the STA323W always acts as a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using 3 input pins: left/right clock lrcki, serial clock bicki, and serial data sdi. the sai register (configuration register b (address 0x01) bits d3-d0) and the saifb register (configuration register b (address 0x01) bit d4) are used to specify the serial data format. the default serial data format is i 2 s, msb first. the formats available are shown in figure 46 and in ta bl e 2 1 and ta bl e 2 2 . figure 46. general serial input and output formats table 22. lists the serial audio input formats supported by STA323W when bicki = 32 * fs, 48 * fs or 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 khz. d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 10000000 table 21. serial audio input interface format bit r/w rst name description 3:0 rw 0000 sai[3:0] determines the interface format of the input serial digital audio interface. 4 rw 0 saifb data format: 0: msb first 1: lsb first i 2 s left justified lrclk left right sclk sdata lsb msb lsb msb msb lrclk left right sclk sdata lsb msb lsb msb msb right justified lrclk left right sclk sdata lsb msb lsb msb msb
STA323W register descriptions 41/77 for example, sai = 1110 and saifb = 1 specifies right justified 16-bit data, lsb first. table 22. supported serial audio input formats bicki sai[3:0] saifb interface format 32 * fs 1100 x i 2 s 15-bit data 1110 x left/right-justified 16-bit data 48 * fs 0100 x i 2 s 23-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0100 0 msb first i 2 s 16-bit data 1100 1 lsb first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data 64 * fs 0000 x i 2 s 24-bit data 0100 x i 2 s 20-bit data 1000 x i 2 s 18-bit data 0000 0 msb first i 2 s 16-bit data 1100 1 lsb first i 2 s 16-bit data 0001 x left-justified 24-bit data 0101 x left-justified 20-bit data 1001 x left-justified 18-bit data 1101 x left-justified 16-bit data 0010 x right-justified 24-bit data 0110 x right-justified 20-bit data 1010 x right-justified 18-bit data 1110 x right-justified 16-bit data
register descriptions STA323W 42/77 figure 47. serial input and data timing 7.2.3 delay serial clock enable g each channel received from the i 2 s can be mapped to any internal processing channel via the channel input mapping registers. this allows processing flexibility. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 23. serial input data timing characteristics (fs = 32 to 192 khz) parameter timing bicki frequency (slave mode) 12.5 mhz max. bicki pulse width high (t1) (slave mode) 40 ns min. bicki active to lrcki edge delay (t2) 20 ns min. bicki active to lrcki edge delay (t3) 20 ns min. sdi valid to bicki active setup (t4) 20 ns min. bicki active to sdi hold time (t5) 20 ns min. t5 t0 t1 t3 t2 t4 sdi bicki lrcki table 24. delay serial clock enable bit r/w rst name description 5rw0dscke 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some i 2 s master devices table 25. channel input mapping bit r/w rst name description 6rw0c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7rw1c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input
STA323W register descriptions 43/77 7.3 configuration register c (address 0x02) 7.3.1 ddx ? power-output mode the ddx ? power output mode selects how the ddx ? output timing is configured. different power devices can use different output modes. the recommended use is om = 10. when om = 11 the csz bits determine the size of the ddx ? compensating pulse. 7.3.2 ddx ? variable compensating pulse size the ddx ? variable compensating pulse size is intended to adapt to different power stage ics. contact st for support when using this function. d7 d6 d5 d4 d3 d2 d1 d0 reserved csz4 csz3 csz2 csz1 csz0 om1 om0 01000010 table 26. ddx ? power-output mode bit r/w rst name description 1:0 rw 10 om[1:0] selects configuration of ddx ? output. table 27. ddx ? output modes om[1,0] output stage - mode 00 not used 01 not used 10 recommended 11 variable compensation table 28. ddx ? compensating pulse csz[4:0] compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ?? 10000 16 clock period compensating pulse size ?? 11111 31 clock period compensating pulse size
register descriptions STA323W 44/77 7.4 configuration register d (address 0x03) 7.4.1 high-pass filter bypass the STA323W features an internal digital high-pass filter for dc blocking. the purpose of this filter is to prevent dc signals from passing through a ddx? amplifier. dc signals can cause speaker damage. 7.4.2 de-emphasis by setting this bit to 1, de-emphasis is implemented on all channels. dspb (dsp bypass, bit d2, cfa) bit must be set to 0 for de-emphasis to function. 7.4.3 dsp bypass setting the dspb bit bypasses all the eq an d mixing functions of the STA323W core. d7 d6 d5 d4 d3 d2 d1 d0 mme zde drc bql psl dspb demp hpb 01000000 table 29. high-pass filter bypass bit r/w rst name description 0rw0hpb 0: ac coupling high pass filter enabled 1: ac coupling high pass filter enabled table 30. de-emphasis bit r/w rst name description 1rw0demp 0: no de-emphasis 1: de-emphasis table 31. dsp bypass bit r/w rst name description 2 rw 0 dspb 0: normal operation 1: bypass of eq and mixing functionality
STA323W register descriptions 45/77 7.4.4 post-scale link post-scale functionality is an attenuation placed after the volume control and directly before the conversion to pwm. post-scale can also be used to limit the maximum modulation index and therefore the peak current. setting 1, in the psl register, causes the value stored in channel 1 post-scale to be used for all three internal channels. 7.4.5 biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 7.4.6 dynamic range compre ssion/anti-clipping bit both limiters can be used in one of two ways: anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 7.4.7 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. when zde = 1, the zero-detect circuit looks at the input data to each processi ng channel after the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. table 32. post-scale link bit r/w rst name description 3 rw 0 psl 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value table 33. biquad coefficient link bit r/w rst name description 4rw0bql 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values table 34. dynamic range compression/anti-clipping bit bit r/w rst name description 5rw0drc 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode table 35. zero-detect mute enable bit r/w rst name description 6 rw 1 zde setting of 1 enables the automatic zero-detect mute
register descriptions STA323W 46/77 7.5 configuration register e (address 0x04) 7.5.1 max power correction variable by enabling mpc and setting mpcv = 1, the max power correction becomes variable. by adjusting the mpcc registers (address 0x27-0x28) it is possible to adjust the thd at maximum unclipped power to a lower value for a particular application. 7.5.2 max power correction setting the mpc bit corrects the power device at high power. this mode lowers the thd+n of the full ddx ? system at, and slightly below, maximum power output. 7.5.3 am mode enable the STA323W features a ddx ? processing mode that minimizes the amount of noise generated in the frequency range of am radio. this mode is intended for use when ddx ? is operating in a device with an active am tuner. the snr of the ddx ? processing is reduced to ~83 db in this mode, which is st ill greater than the snr of am radio. 7.5.4 pwm speed mode d7 d6 d5 d4 d3 d2 d1 d0 sve zce reserved pwms ame reserved mpc mpcv 11000010 table 36. max power correction variable bit r/w rst name description 0rw0mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 37. max power correction bit r/w rst name description 1rw1mpc 0: mpc disabled 1: mpc enabled table 38. am mode enable bit r/w rst name description 3rw0ame 0: normal ddx ? operation 1: am reduction mode ddx ? operation table 39. pwm speed mode bit r/w rst name description 4 rw 0 pwms normal or odd
STA323W register descriptions 47/77 7.5.5 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. 7.5.6 soft volume update enable the STA323W includes a soft volume algorithm that steps through the intermediate volume values at a predetermined rate when a volume change occurs. by setting sve = 0 this can be bypassed and volume changes will jump fr om the old to the new value directly. this feature is available only if individual channel volume bypass bit is set to 0. table 40. pwm output speed selections pwms[1:0] pwm output speed 0 normal speed (384khz) all channels 1 odd speed (341.3khz) all channels table 41. zero-crossing volume enable bit r/w rst name description 6rw1zce 1: volume adjustments will only occur at digital zero- crossings 0: volume adjustments will occur immediately table 42. soft volume update enable bit r/w rst name description 7 rw 1 sve 1: volume adjustments will use soft volume 0: volume adjustments will occur immediately
register descriptions STA323W 48/77 7.6 configuration regi ster f (address 0x05) 7.6.1 output conf iguration selection setting the ide bit enables this function, which looks at the input i 2 s data and clocking and automatically mutes all outputs if the signals are invalid. detects loss of input mclk in binary mode and outputs 50% duty cycle to prevent audible noise when input clocking is lost. d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle reserved bcle ide ocfg1 ocfg0 01011100 table 43. output configuration selection bit r/w rst name description 1:0 rw 00 ocfg[1:0] 00: 2-chan nel (full-bridge) power, 1-channel ddx is default table 44. output configuration selections ocfg[1:0] output po wer configuration 00 2 channel (full-bridge) power, 1 channel ddx: 1a/1b ? 1a/1b 2a/2b ? 2a/2b 01 2(half-bridge).1(full-bridge) on-board power: 1a ? 1a binary 2a ? 1b binary 3a/3b ? 2a/2b binary 10 reserved 11 1 channel mono-parallel: 3a ? 1a/1b 3b ? 2a/2b table 45. invalid input detect mute enable bit r/w rst name description 2rw1ide 0: disabled 1: enabled table 46. binary clock loss detection enable bit r/w rst name description 3rw1bcle 0: disabled 1: enabled
STA323W register descriptions 49/77 when ecle is active, it issues a power devi ce power down signal (eapd) on clock loss detection. eapd is used to actively power down a connected ddx ? power device. this register has to be written to 1 at start-up to enable the ddx ? power device for normal operation. table 47. auto-eapd on clock loss enable bit r/w rst name description 5rw0ecle 0: disabled 1: enabled table 48. software power down bit r/w rst name description 6rw1pwdn software power down: 0: power down mode: initiates a power-down sequence which results in a soft mute of all channels and finally asserts eapd circa 260 ms later 1: normal operation table 49. external amplifier power down bit r/w rst name description 7 rw 0 eapd 0: external power stage power down active 1: normal operation
register descriptions STA323W 50/77 7.7 volume control 7.7.1 master controls master mute register (address 0x06) master volume register (address 0x07) note: the value of volume derived from mv is dependent on the amv automodes? volume settings. 7.7.2 channel controls channel 1 volume (address 0x08) channel 2 volume (address 0x09) channel 3 volume (address 0x0a) 7.7.3 volume description the volume structure of the STA323W consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. the channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. these values are normally set at the initialization of the ic and not changed. the individual channel volumes are adjustable in 0.5-db steps from +48 db to -80 db. the master volume control is normally mapped to the master volume of the system. the values of these two settings are summed to find the actual gain or volume value for any given channel. d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved reserved reserved reserved mmute 00000000 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000
STA323W register descriptions 51/77 when set to 1, the master mute will mute all channels, whereas the individual channel mutes (cxm) will mute only that channel. bo th the master mute and the channel mutes provide a ?soft mute?, that is, a gradual muting with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate of circa 96 khz. a ?hard mute? can be obtained by setting a value of 0xff in any channel volume register or the master volume register. when volume offsets are provided, via the master volume register, any channel whose total volume is less than -100 db is muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register e) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates occur immediately. the STA323W also features a soft-volume update f unction. when sve = 1 (in configuration register e) the volume ramps between intermediate values when the value is updated, this feature can be disabled by setting sve = 0. each channel also contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting does not affect that channel. also, master soft-mute does not affect the chan nel if cxvbp = 1. each channel also contains a channel mute. if cxm = 1 a soft mute is performed on that channel. table 50. master volume offset as a function of mv[7:0] mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127 db 11111111 (0xff) hard master mute table 51. channel volume as a function of cxv[7:0] cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01100001 (0x5f) +0.5 db 01100000 (0x60) 0 db 01011111 (0x61) -0.5 db ??
register descriptions STA323W 52/77 7.8 automodes? registers 7.8.1 automodes? eq, volume, gc (address 0x0b) setting ameq to any value, other than 00, enables automodes? eq. when set, biquads 1- 4 are not user programmable. any coefficient settings for these biquads is ignored. also when automodes? eq is used the pre-scale value for channels 1 and 2 becomes hard-set to -18 db. 11111110 (0xfe) -79.5 db 11111111 (0xff) hard channel mute table 51. channel volume as a function of cxv[7:0] (continued) cxv[7:0] volume d7 d6 d5 d4 d3 d2 d1 d0 amps reserved amgc1 amgc0 amv1 amv0 ameq1 ameq0 10000000 table 52. automodes? eq ameq[1,0] mode (biquad 1-4) 00 user programmable 01 preset eq - peq bits 10 auto volume controlled loudness curve 11 not used table 53. automodes? volume amv[1,0] mode (mvol) 00 mvol 256, 0.5-db steps (standard) 01 mvol auto curve 30 steps 10 mvol auto curve 40 steps 11 mvol auto curve 50 steps table 54. automodes? gain compression/limiters amgc[1:0] mode 00 user programmable gc 01 ac no clipping 10 ac limited clipping (10%) 11 drc night time listening mode
STA323W register descriptions 53/77 7.8.2 automodes? am/pre-scale/bass management scale (address 0x0c) when ddx ? is used with an am radio tuner, it is recommended to use the amam bits to automatically adjust the output pwm switching rate so that it depends on the specific radio frequency that the tuner is receiving. the values used in amam are also dependent upon the sample rate that is determined by the adc used. table 55. amps - automodes? auto pre scale bit r/w rst name description 0 rw 0 amps automode pre-scale 0: -18 db used for pre-scale when ameq neq 00 1: user defined pre-scale when ameq neq 00 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 table 56. automodes? am switching enable bit r/w rst name description 0 rw 0 amame 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings 3:1 rw 000 amam[2:0] default: 000 table 57. automodes? am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz table 58. automodes? crossover setting bit r/w rst name description 7:4 rw 0 xo[3:0] 000: user defined crossove r coefficients are used otherwise: preset coefficients are used for the required crossover setting table 59. crossover frequency selection xo[2:0] bass management - crossover frequency 0000 user 0001 80 hz
register descriptions STA323W 54/77 7.8.3 preset eq set tings (address 0x0d) 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz table 59. crossover frequency selection (continued) xo[2:0] bass management - crossover frequency d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved peq4 peq3 peq2 peq1 peq0 00000000 table 60. preset eq selection peq[3:0] setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog
STA323W register descriptions 55/77 7.9 channel configuration registers 7.9.1 channel 1 configur ation (address 0x0e) 7.9.2 channel 2 configur ation (address 0x0f) 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 (least boost) 10001 loudness 2 10010 loudness 3 10011 loudness 4 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 (most boost) table 60. preset eq selection (continued) peq[3:0] setting d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 00000000
register descriptions STA323W 56/77 7.9.3 channel 3 configur ation (address 0x10) eq control can be bypassed on a per channel basis. if eq control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. cxeqbp: " 0: perform eq on channel x (normal operation) " 1: bypass eq on channel x tone control (bass and treble) can be bypassed on a per channel basis. if tone control is bypassed on a given channel the two filter s that tone control utilizes are bypassed. cxtcb: " 0: perform tone control on channel x - (default operation) " 1: bypass tone control on channel x each channel can be configured to output either the patented ddx pwm data or standard binary pwm encoded data. by setting the cxbo bit to ?1?, each channel can be individually set to binary operation mode. it is also possible to map each channel independently to either of the two limiters available within the STA323W. in the default mode the channels are not mapped to a limiter. each pwm output channel can receive data from any channel output of the volume block. which channel a particular pwm output receives depends on the cxom register bits for that channel. d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved reserved 00000000 table 61. channel limiter mapping selection cxls[1,0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 62. channel pwm output mapping cxom[1:0] pwm output from 00 channel 1 01 channel 2 10 channel 3 11 not used
STA323W register descriptions 57/77 7.10 tone control (address 0x11) 7.11 dynamics control 7.11.1 limiter 1 attack/rel ease threshold (address 0x12) 7.11.2 limiter 1 attack/rel ease threshold (address 0x13) 7.11.3 limiter 2 attack/rel ease rate (address 0x14) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 63. tone control boost/cut selection btc[3:0]/ttc[3:0] boost/cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12 db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010
register descriptions STA323W 58/77 7.11.4 limiter 2 attack/rel ease threshold (address 0x15) 7.11.5 dynamics control description the STA323W includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for dvds.) the two modes are selected via the drc bit in configuration register d, bit 5 address 0x03. each channel can be mapped to limiter1 or limiter2, or not mapped. if a channel is not mapped, that channel will clip normally when 0 db fs is exceeded. each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers. when the attack threshold has been exceeded, the limiter, when active, automatically starts reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. a peak-detect algorithms used to control the gain reduction. the release of limiter, when the gain is again increased, is dependent on an rms-detect algorithm. the output of the volume limiter block is passed through an rms filter. the output of this filter is compared with the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. the release threshold value can be used to set wh at is effectively a minimum dynamic range. this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?. in ac mode the attack and release thresholds are set relative to full-scale. in drc mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. figure 48. basic limiter and volume flow diagram d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001 gain attenuation saturation output input gain/volume limiter rms
STA323W register descriptions 59/77 table 64. limiter attack rate selection lxa[3:0] attack rate db/ms 0000 3.1584 fast 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 slow table 65. limiter release rate selection lxr[3:0] release rate db/ms 0000 0.5116 fast 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 slow
register descriptions STA323W 60/77 7.11.6 anti-clipping mode . table 66. limiter attack - threshold selection (ac-mode) lxat[3:0] ac (db re lative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 table 67. limiter release threshold selection (ac-mode) lxrt[3:0] ac (db re lative to fs) 0000 - 0001 -29db 0010 -20db 0011 -16db 0100 -14db 0101 -12db 0110 -10db 0111 -8db 1000 -7db 1001 -6db 1010 -5db 1011 -4db 1100 -3db 1101 -2db
STA323W register descriptions 61/77 7.11.7 dynamic range compression mode 1110 -1db 1111 -0db table 67. limiter release threshold selection (ac-mode) (continued) lxrt[3:0] ac (db re lative to fs) table 68. limiter attack - threshold selection (drc-mode) lxat[3:0] drc (db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4
register descriptions STA323W 62/77 .( table 69. limiter release threshold selection (drc-mode) lxrt[3:0] drc (db relati ve to volume + lxat) 0000 - 0001 -38 db 0010 -36 db 0011 -33 db 0100 -31 db 0101 -30 db 0110 -28 db 0111 -26 db 1000 -24 db 1001 -22 db 1010 -20 db 1011 -18 db 1100 -15 db 1101 -12 db 1110 -9 db 1111 -6 db
STA323W user-programmable settings 63/77 8 user-programmable settings 8.1 eq - biquad equation the biquads use the equation that follows. this is shown in figure 49 . y[n] = 2(b0/2)x[n] + 2(b1/2)x[n-1] + b2x[n-2] - 2(a1/2)y[n-1] - a2y[n-2] = b0x[n] + b1x[n-1] + b2x[n-2] - a1y[n-1] - a2y[n-2] where y[n] represents the output and x[n] represents the input. signed, fractional 28-bit multipliers are used, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). coefficients stored in the user defined coe fficient ram are referenced in the following manner: " cxhy0 = b1/2 " cxhy1 = b2 " cxhy2 = -a1/2 " cxhy3 = -a2 " cxhy4 = b0/2 the x represents the channel and the y the biquad number. for example c3h41 is the b0/2 coefficient in the fourth biquad for channel 3. figure 49. biquad filter 8.2 pre-scale the pre-scale block, which precedes the first biquad, is used for attenuation when filters are designed that boost frequencies above 0 db fs. the pre-scale block is a single 28-bit signed multiplier, with 0x800000 = -1 and 0x 7fffff = 0.9999998808. by default, all pre-scale factors are set to 0x7fffff. 8.3 post-scale the STA323W provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. the post-scale block is a 24-bit signed fractional multiplier. the scale factor for this multiplier is loaded in to ram using the same i 2 c registers as the biquad coefficients and the mix. all channels can use the same settings as channel 1 by setting the post-scale link bit. + + + 2 2 2 b1/2 b0/2 z -1 z -1 b2 -a2 -a1/2 z -1 z -1
user-programmable settings STA323W 64/77 8.4 mix/bass management the STA323W provides one post-eq mixing block per channel. each channel has two mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the two channels of input to the mixing block. these coefficients are accessible via the user controlled coefficient ram described below. the mix coefficients expressed as 24-bit signed, fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608), are used to provide three channels of output from two channels of filtered input. figure 50. mix/bass management block diagram after mixing, STA323W also permits the implementation of crossover filters on all channels corresponding to 2.1 bass management operation. channels 1 and 2 use a 1st order, high- pass filter and channel 3 uses a 2nd-order low-pass filter corresponding to the setting of the xo bits of i 2 c register 0x0c. if xo = 000, user specified crossover filters are used. by default these coefficients correspond to pass-through. however, the user can write these coefficients in a similar way as the eq biquads. when user-defined setting is selected, the user can only write 2nd-order crossover filters. this output is then passed on to the volume and limiter block. c1mx1 high pass xo filter c1mx2 . channel #1 from eq channel #2 from eq channel #1 to gc/vol c2mx1 high pass xo filter c2mx2 . channel #2 to gc/vol c3mx1 low pass xo filter c3mx2 . channel #3 to gc/vol crossover frequency determined by xo setting. user defined when xo = 000 user defined mix coefficients
STA323W user-programmable settings 65/77 8.5 calculating 24-bit signed fr actional numbers from a db value the pre-scale, mixing, and post-scale function s of the STA323W use 24-bit signed fractional multipliers to attenuate signals. these attenuations can also invert the phase and therefore range in value from -1 to +1. it is possible to calculate the coefficient to use for a given negative db value (attenuation) using the equations following. " non-inverting phase numbers 0 to +1: ? coefficient = round(8388607 * 10 (db/20) ) " inverting phase numbers 0 to -1: ? coefficient = 16777216 - round(8388607 * 10 (db/20) ) as can be seen by the preceding equations, th e value for positive phase 0 db is 0x7fffff and the value for negative phase 0 db is 0x800000. 8.6 user defined coefficient ram 8.6.1 coefficient addre ss register 1 (address 0x16) 8.6.2 coefficient b1data regist er bits 23:16 (address 0x17) 8.6.3 coefficient b1data regist er bits 15:8 (address 0x18) 8.6.4 coefficient b1data regi ster bits 7:0 (address 0x19) 8.6.5 coefficient b2 data regist er bits 23:16 (address 0x1a) d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000
user-programmable settings STA323W 66/77 8.6.6 coefficient b2 data regist er bits 15:8 (address 0x1b) 8.6.7 coefficient b2 data regi ster bits 7:0 (address 0x1c) 8.6.8 coefficient a1 data regist er bits 23:16 (address 0x1d) 8.6.9 coefficient a1 data regist er bits 15:8 (address 0x1e) 8.6.10 coefficient a1 data re gister bits 7:0 (address 0x1f) 8.6.11 coefficient a2 data register bits 23:16 (address 0x20) 8.6.12 coefficient a2 data register bits 15:8 (address 0x21) d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000
STA323W user-programmable settings 67/77 8.6.13 coefficient a2 data register bits 7:0 (address 0x22) 8.6.14 coefficient b0 data register bits 23:16 (address 0x23) 8.6.15 coefficient b0 data register bits 15:8 (address 0x24) 8.6.16 coefficient b0 data re gister bits 7:0 (address 0x25) 8.6.17 coefficient write co ntrol register (address 0x26) coefficients for eq, mix and scaling are handled internally in the STA323W via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. the first register contains base address of the coefficient: five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the reading or writing of the coefficients to ram. the follo wing are instructions for read ing and writing coefficients. d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved ra r1 wa w1 00000000
user-programmable settings STA323W 68/77 8.7 reading and writing coefficients 8.7.1 reading a coefficient from ram 1. write 8-bits of address to i 2 c register 0x16. 2. write 1 to bit r1 (d2) of i 2 c register 0x26. 3. read top 8-bits of coefficient in i 2 c address 0x17. 4. read middle 8-bits of coefficient in i 2 c address 0x18. 5. read bottom 8-bits of coefficient in i 2 c address 0x19. 8.7.2 reading a set of coefficients from ram 1. write 8-bits of address to i 2 c register 0x16. 2. write 1 to bit ra (d3) of i 2 c register 0x26. 3. read top 8-bits of coefficient in i 2 c address 0x17. 4. read middle 8-bits of coefficient in i 2 c address 0x18. 5. read bottom 8-bits of coefficient in i 2 c address 0x19. 6. read top 8-bits of coefficient b2 in i 2 c address 0x1a. 7. read middle 8-bits of coefficient b2 in i 2 c address 0x1b. 8. read bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 9. read top 8-bits of coefficient a1 in i 2 c address 0x1d. 10. read middle 8-bits of coefficient a1 in i 2 c address 0x1e. 11. read bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 12. read top 8-bits of coefficient a2 in i 2 c address 0x20. 13. read middle 8-bits of coefficient a2 in i 2 c address 0x21. 14. read bottom 8-bits of coefficient a2 in i 2 c address 0x22. 15. read top 8-bits of coefficient b0 in i 2 c address 0x23. 16. read middle 8-bits of coefficient b0 in i 2 c address 0x24. 17. read bottom 8-bits of coefficient b0 in i 2 c address 0x25. 8.7.3 writing a singl e coefficient to ram 1. write 8-bits of address to i 2 c register 0x16. 2. write top 8-bits of coefficient in i 2 c address 0x17. 3. write middle 8-bits of coefficient in i 2 c address 0x18. 4. write bottom 8-bits of coefficient in i 2 c address 0x19. 5. write 1 to w1 bit in i 2 c address 0x26.
STA323W user-programmable settings 69/77 8.7.4 writing a set of coefficients to ram 1. write 8-bits of starting address to i 2 c register 0x16. 2. write top 8-bits of coefficient b1 in i 2 c address 0x17. 3. write middle 8-bits of coefficient b1 in i 2 c address 0x18. 4. write bottom 8-bits of coefficient b1 in i 2 c address 0x19. 5. write top 8-bits of coefficient b2 in i 2 c address 0x1a. 6. write middle 8-bits of coefficient b2 in i 2 c address 0x1b. 7. write bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 8. write top 8-bits of coefficient a1 in i 2 c address 0x1d. 9. write middle 8-bits of coefficient a1 in i 2 c address 0x1e. 10. write bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 11. write top 8-bits of coefficient a2 in i 2 c address 0x20. 12. write middle 8-bits of coefficient a2 in i 2 c address 0x21. 13. write bottom 8-bits of coefficient a2 in i 2 c address 0x22. 14. write top 8-bits of coefficient b0 in i 2 c address 0x23. 15. write middle 8-bits of coefficient b0 in i 2 c address 0x24. 16. write bottom 8-bits of coefficient b0 in i 2 c address 0x25. 17. write 1 to wa bit in i 2 c address 0x26. the mechanism for writing a set of coefficients to ram provides a method of simultaneously updating the five coefficients corresponding to a given biquad (filter) to avoid possible unpleasant acoustic side-effects. when using this technique, the 8-bit address specifies the address of the biquad b1 coefficient (for example 0, 5, 10, 15, ?, 45 decimal), and the STA323W generates the ram addresses as an offsets from this base value to write the complete set of coefficient data. table 70. ram block for biquads, mixing, and scaling index (decimal) index (hex) coefficient default 0 0x00 channel 1 - biquad 1 c1h10 (b1/2) 0x000000 1 0x01 c1h11 (b2) 0x000000 2 0x02 c1h12 (a1/2) 0x000000 3 0x03 c1h13 (a2) 0x000000 4 0x04 c1h14 (b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000 ... ... ... ... ... 19 0x13 channel 1 - biquad 4 c1h44 0x400000 20 0x14 channel 2 - biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ??? ?? 39 0x27 channel 2 - biquad 4 c2h44 0x400000
user-programmable settings STA323W 70/77 8.8 variable max power corr ection (address 0x27-0x28) the mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 40 0x28 high-pass 2 nd -order filter for xo = 000 c12h0 (b1/2) 0x000000 41 0x29 c12h1 (b2) 0x000000 42 0x2a c12h2 (a1/2) 0x000000 43 0x2b c12h3 (a2) 0x000000 44 0x2c c12h4 (b0/2) 0x400000 45 0x2d low-pass 2 nd -order filter for xo = 000 c12l0 (b1/2) 0x000000 46 0x2e c12l1 (b2) 0x000000 47 0x2f c12l2 (a1/2) 0x000000 48 0x30 c12l3 (a2) 0x000000 49 0x31 c12l4 (b0/2) 0x400000 50 0x32 channel 1 - post scale c1pres 0x7fffff 51 0x33 channel 2 - post scale c2pres 0x7fffff 52 0x34 channel 1 - post scale c1psts 0x7fffff 53 0x35 channel 2 - post scale c2psts 0x7fffff 54 0x36 channel 3 - post scale c3psts 0x7fffff 55 0x37 thermal warning - post scale twpsts 0x5a9df7 56 0x38 channel 1 - mix 1 c1mx1 0x7fffff 57 0x39 channel 1 - mix 2 c1mx2 0x000000 58 0x3a channel 2 - mix 1 c2mx1 0x000000 59 0x3b channel 2 - mix 2 c2mx2 0x7fffff 60 0x3c channel 3 - mix 1 c3mx1 0x400000 61 0x3d channel 3 - mix 2 c3mx2 0x400000 62 0x3e unused 63 0x3f unused table 70. ram block for biquads, mixing, and scaling (continued) index (decimal) index (hex) coefficient default d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000
STA323W user-programmable settings 71/77 8.9 fault detect recovery (address 0x2b - 0x2c) fdrc bits specify the 16-bit fa ult detect recovery time delay. when fault is active, the tristate output immediately goes low and is held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c specifies approximately 0.1 ms. 8.10 status indicator re gister (address 0x2d) status register bits serve the purpose of communicating the detected error or warning condition to the user. this is a read-only register and writing to this register would not be of any consequence. 8.10.1 thermal warning indicator if the power stage thermal operating conditions are exceeded, the thermal warning indicator transmits a signal to the digital logic block to initiate a corrective procedure. this register bit is set to 0 to indicate a thermal warning and it reverts back to its default state as soon as the cause of the thermal warning has been corrected. 8.10.2 fault detect indicator as soon as the power stage issues a fault error signal, thereby initiating the fault recovery procedure described in section 8.9 , this register bit is set to 0 to indicate the error to the user. as soon as the fault condition (over-current or thermal) is corrected, this bit is reset back to its default state. d7 d6 d5 d4 d3 d2 d1 d0 frdc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 d7 d6 d5 d4 d3 d2 d1 d0 plull reserved reserved reserved reserved reserved fault twarn 00000011 table 71. thermal warning indicator bit r/w rst name description 0ro1rwran 0: thermal warning detected 1: normal operation (no thermal warning) table 72. fault detect indicator bit r/w rst name description 1ro1fault 0: fault issued from the power stage 1: normal operation (no fault)
user-programmable settings STA323W 72/77 8.10.3 pll unlock indicator under normal conditions (with the correct clock) the pll is locked into an internal clocking frequency. however, if the clock is insufficient or if it is abruptly lost, the pll lock state is lost and this information is relayed to the user via setting the pllul bit of the status register to 1. as soon as the pll reverts back to a locked state, this bit is set to 0. table 73. pll unlock indicator bit r/w rst name description 7ro0pllul 0: normal operation (pll is in a locked state) 1: pll unlock is detected (due to probable clock loss)
STA323W package information 73/77 9 package information figure 51. powerso-36 slug down outline drawing u re 1: 0096119 rev d
package information STA323W 74/77 in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. table 74. powerso-36 slug down dimensions symbol mm inch min typ max min typ max a--3.60--0.142 a1 0.10 - 0.30 .004 - .012 a2--3.30--0.130 a3 0 - 0.10 0 - .004 b 0.22 - 0.38 0.009 - 0.015 c 0.23 - 0.32 0.009 - 0.013 d 15.80 - 16.00 0.622 - 0.630 d1 9.40 - 9.80 0.370 - 0.386 e 13.90 - 14.50 0.547 - 0.571 e1 10.90 - 11.10 0.429 - 0.437 e2--2.90--0.114 e3 5.80 - 6.20 0.228 - 0.244 e - 0.65 - - 0.026 - e3 - 11.05 - - 0.435 - g0-0.100-0.004 h 15.50 - 15.90 0.610 - 0.626 h--1.10--0.043 l 0.80 - 1.10 0.031 - 0.043 m 2.25 - 2.60 0.089 - 0.102 n - - 10 degrees - - 10 degrees r - 0.30 - - 0.012 - s--8 degrees--8 degrees
STA323W trademarks and other acknowledgements 75/77 10 trademarks and other acknowledgements ddx is a registered trademark of apogee technology inc. automodes is a trademark of apogee technology inc. ecopack is a registered trademark of stmicroelectronics.
revision history STA323W 76/77 11 revision history table 75. document revision history date revision changes 01-jul-2005 1.0 initial release. 02-jan-2006 2.0 modified configurat ion register a (addr 0x00). 02-feb-2006 3.0 modified the ordering part numbers. 08-jun-2006 4.0 added new chapters. updated electrical characteristics curves . modified the minimum value of vcc paramter. 15-nov-2006 5.0 update into latest template. 22-may-2008 6 updated pin 1 connection. general presentation revision.
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