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20207 www.vishay.com 218 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors fast infrared transceiver module (mir, 1.152 mbit/s) for irda ? and remote control applications description the tfbs5700 is a low profile infrared transceiver module compliant to the la test irda physical layer standard for fast infrared data communication, sup- porting irda speeds up to 1.152 mbit/s (mir) and car- rier based remote control modes up to 2 mhz. the transceiver module consists of a pin photodiode, an infrared emitter (ired), and a low-power control ic to provide a total font-end solution in a single package. features ? irda irphy 1.4 compliant 9.6 kbit/s to 1.152 mbit/s range > 50 cm, exceeding the low power standard ? wide operating voltage range 2.4 v to 3.6 v ? i/o compatible to 1.8 v logic voltage ? low power consumption supply current in receive mode, idle: 550 a ? small package - l 6.8 mm x w 2.8 mm x h 1.6 mm ? remote control transmitter operation - typical range 12 m ? emitter wavelength: 886 nm - suited for remote control ? high immunity to fluorescence light ? high emi immunity > 200 v/m (700 mhz to 2100 mhz) ? lead (pb)-free device ? qualified for lead (pb)-free and sn/pb processing (msl4) ? device in accordance with rohs 2002/95/ec and weee 2002/96ec applications ? mobile phone ? smart phone ? pdas ? pos terminals/vending ? battery operated irda applications parts table part description qty/reel TFBS5700-TR3 oriented in carrier tape for side view surface mounting 2500 pcs e4
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 219 functional block diagram pin description pinout tfbs5700, bottom view weight 33 mg definitions: in the vishay transceiver data sh eets the following nomenclature is used for defining the irda operating modes: sir: 2.4 kbit/s to 115.2 kbit/s, equiva lent to the basic serial infrared standard with the physical layer version irphy 1.0 mir: 576 kbit/s to 1152 kbit/s fir: 4 mbit/s vfir: 16 mbit/s mir and fir were implemented with irphy 1.1, followed by irphy 1.2, adding the sir low power standard. irphy 1.3 extended the low power option to mir and fir and vfir was added with irphy 1.4. a new version of the standard in any case obsoletes the former version. pin number function description i/o active 1 ired a ired anode, v cc2 2 txd this schmitt-trigger input is used to transmit serial data when sd is low. an on-chip protection circuit disables the le d driver if the txd pin is asserted for longer than 80 s. when used in conjunc tion with the sd pin, this pin is also used to control receiver output pulse duration. the input threshold voltage adapts to and follows the internal logic voltage reference of 1.8 v ihigh 3 rxd received data output, push-pull cmos driver output capable of driving standard cmos or ttl loads. no external pull-up or pull-down resistor is required. floating with a weak pull-up of 500 k (typ.) in shutdown mode. the voltage swing is defined by the internal vlogic voltage of 1.8 v olow 4 sd shutdown. also used for setting the output pulse duration. setting this pin active for more than 1.5 ms places the module into shutdown mode. before that (t < 0.7 ms) on the falling edge of this signal, the state of the txd pin is sampled and used to set the receiver output to long pulse duration (2 s) or to short pulse duration (0.4 s) mode. the input threshold voltage adapts to and follows the internal logic voltage reference of 1.8 v ihigh 5v cc power supply. receives power supply 2.4 v to 3.6 v. this pin provides power for the receiver and transmitter drive section. 6 gnd ground ired dri v er txd sd g n d v cc ireda rxd amplifier comparator tri-state dri v er mode control pd ired asic 19291 19290
www.vishay.com 220 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors absolute maximum ratings reference point pin, gnd unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) due to the internal limitation meas ures the device is a "class1" device **) irda specifies the max. intensity with 500 mw/sr parameter test conditions symbol min ty p. max unit supply voltage range, transceiver 0 v < v cc2 < 6 v v cc1 - 0.5 6 v supply voltage range, transmitter 0 v < v cc1 < 6 v v cc2 - 0.5 6.5 v voltage at all i/o pins - 0.5 5.5 v power dissipation see derating curve p d 350 mw junction temperature note: internal protection above 125 asic temperature t j 125 c ambient temperature range (operating) t amb - 30 + 85 c storage temperature range t stg - 40 + 100 c soldering temperature see section ?recommended solder profile? 260 c average output current i ired (dc) 125 ma repetitive pulse output current < 90 s, t on < 20 % i ired (rp) 500 ma virtual source size method: (1-1/e) encircled energy d0.8 mm maximum intensity for class 1 iec60825-1 or en60825-1, edition jan. 2001 i e *) (500) **) mw/sr esd protection esd protection on all pins method: human body model d 1 kv latch up d | 100| ma
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 221 electrical characteristics transceiver t amb = 25 c, v cc = 2.4 v to 3.6 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) decision level 0.9 v parameter test conditions symbol min ty p. max unit supply voltage v cc 2.4 3.6 v dynamic supply current idle, dark ambient sd = low (< 0.8 v), e e = 0 klx i cc 550 900 a receiving sd = low, 1 mbit/s, e e = 100 mw/m 2 i cc 0.75 ma shutdown supply current dark ambient sd = high (> v cc1 - 1.3 v), t = 25 c, e e = 0 klx t = 25 c i sd 0.01 1.0 a shutdown supply current at maximum operating temperature sd = high, (> v cc1 - 1.3 v), t = 85 c i sd 5.0 a operating temperature range t a - 25 + 85 c output voltage low i ol = 0.5 ma, c load = 15 pf v ol 0.4 v output voltage high i oh = - 250 a, c load = 15 pf v oh 1.44 v output voltage high i oh = 0 a, c load = 15 pf v oh 1.98 v rxd to internal vlogic impedance sd = active, pull-up in shutdown r rxd 400 500 800 k input voltage low (txd, sd) v il - 0.5 0.5 v input voltage high (txd, sd) v ih 1.3 1.8 2.2 v input leakage current (txd, sd) *) vin = 0.9 x v cc1 is-sd, iin-sd - 1.1 4 10 a sd mode programming pulse width t sdpw 0.2 300 s input capacitance (txd, sd) c i 5pf
www.vishay.com 222 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors optoelectronic characteristics receiver t amb = 25 c, v cc = 2.4 v to 3.6 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. note: all timing data measured with 4 mbit/s are meas ured using the irda ? fir transmission header. the data given here are valid 5 s after starting the preamble. *) this parameter reflects the backlight te st of the irda physical layer specificati on to guarantee immunity against light from f luorescent lamps **) irda sensitivity definition: minimum irradiance e e in angular range , power per unit area. the receiver must meet the ber specifica- tion while the source is operati ng at the minimum intensity in angular range into the minimum half-angle range at the maximum l ink length. ***) maximum irradiance e e in angular range , power per unit area. the optic al delivered to the detector by a source operating at the maximum intensity in angular range at minimum link length must not cause receiver overdrive distortion and possi ble related link errors. if placed at the active output interface reference plane of the transmitter, the receiver must me et its bit error ratio (ber) s pecification. for more definitions see the document ?symbols and terminology ? on the vishay website (htt p://www.vishay.com/docs/82512/82512.p df). 1) some endecs are not able to decode s hort pulses as valid sir pulses. theref ore this additional mode was added in tfbs5700. tfbs5700 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (sd must ha ve been longer active than 1.5 ms). for mode c hanging see the chapter "programming". parameter test conditions symbol min ty p. max unit minimum irradiance e e in angular range **) sir mode 9.6 kbit/s to 115.2 kbit/s = 850 nm to 900 nm e e 50 (5) 81 (8.1) mw/m 2 (w/cm 2 ) minimum irradiance e e in angular range **) mir mode 1.152 mbit/s = 850 nm to 900 nm e e 50 (5) 140 (14) mw/m 2 (w/cm 2 ) maximum irradiance e e in angular range ***) = 850 nm to 900 nm e e 5 (500) kw/m 2 (mw/cm 2 ) logic low receiver input irradiance *) according to irda appendix a1, fluorescent light specification e e 4 (0.4) mw/m 2 (w/cm 2 ) rxd pulse width of output signal, dafault mode after power on or reset input pulse length t wopt > 200 ns 300 400 500 ns rise time of output signal 10 % to 90 %, c l = 15 pf t r (rxd) 10 27 60 ns fall time of output signal 90 % to 10 %, c l = 15 pf t f (rxd) 10 17 60 ns sir endec compatility mode 1 ): rxd pulse width of output signal input pulse length t wopt > 200 ns, see chapter ?programming? t pw 1.7 2.0 2.9 s stochastic jitter, leading edge input irradiance = 150 mw/m 2 , 1.152 mbit/s, 576 kbit/s 70 ns stochastic jitter, leading edge input irradiance = 150 mw/m 2 , 115.2 kbit/s 350 ns standby/shutdown delay after shutdown active or (sd low to high transition) 0.6 1.5 ms shutdown active time window for programming during this time the pulse duration of the output can be programmed to the application mode. see chapter ?programming? 600 s receiver start up time, power on delay shutdown recovery delay after shutdown inactive (sd high to low transition) and power-on 250 s latency t l 50 200 s
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 223 transmitter t amb = 25 c, v cc = 2.4 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) note: due to this wavelength restriction compared to the irda spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard remote control applications with codes as e.g. philips rc5/rc6 ? or recs 80. when operated under irda full range condi- tions (> 120 mw/sr) the rc range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. **) typ. conditions for if = 200 ma, v cc2 = 2.9 v, rs = 4.7 table 1. truth table parameter test conditions symbol min ty p. max unit recommended ired operating peak current **) the ired current must be controlled by an external resistor i d 200 600 ma output leakage ired current txd = 0 v, t amb = 25 c txd = 0 v, t amb = 85 c i ired 200 1 pa a output radiant intensity, s. figure 3, recommended appl. circuit a = 0, 15, txd = high, sd = low, v cc1 = 2.5 v, v cc2 = 2.9 v, rs = 4.7 i e 25 60 500 mw/sr output radiant intensity v cc1 = 5.0 v, = 0, 15 txd = low, sd = high (receiver is inactive as long as sd = high) i e 0.04 mw/sr peak - emission wavelength *) p 880 900 nm optical spectral bandwidth ? 45 nm optical rise time, optical fall time t ropt , t fopt 10 40 ns optical output pulse duration input pulse width 217 ns, 1.152 mbit/s t opt 180 217 240 ns input pulse width t < 80 s input pulse width t 80 s t opt t opt t txd 85 s s optical overshoot 25 % inputs outputs remark sd txd optical input irradiance mw/m 2 rxd transmitter operation high < 600 s x x weakly pulled (500 k ) to v cc1 0 time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k ) to v cc1 0 shutdown low high x low (active) i e transmitting low high > 80 s x high inactive 0 protection is active low low < 4 high inactive 0 ignoring low signals below the irda defined threshold for noise immunity low low > min. irradiance e e < max. irradiance e e low (active) 0 response to an irda compliant optical input signal low low > max. irradiance e e undefined 0 overload conditions can cause unexpected outputs
www.vishay.com 224 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors recommended circuit diagram operated at a clean low impedance power supply the tfbs5700 needs only one additional external com- ponent for setting the ired drive current. however, depending on the entire system design and board lay- out, additional components may be required (see figure 1). the capacitor c1 is buffering the supply voltage and eliminates the inductance of the power supply line. this one should be a small ceramic version or other fast capacitor to guarantee the fast rise time of the ired current. the resistor r1 is only necessary for setting the ired drive current. vishay transceivers integrate a sensitive receiver and a built-in power driver. the combination of both needs a careful circuit board layout. the use of thin, long, resistive and inductive wiring should be avoided. the inputs (txd, sd) and the output rxd should be directly (dc) coupled to the i/o circuit. the capacitor c2 co mbined with the resistor r2 is the low pass filter for smooth ing the supply voltage. r2, c1 and c2 are optional and dependent on the quality of the supply volt ages vccx and injected noise. an unstable power supply with dropping volt- age during transmission may reduce the sensitivity (and transmission range) of the transceiver. the placement of these parts is critical. it is strongly recommended to position c2 as close as possible to the transceiver power supply pins. in addition, when connecting the described circuit to the power supply, low impedance wiring should be used. when extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at v cc2 . often some power supplies are not able to follow the fast current is rise time. in that case another 10 f (type, see table under c1) at v cc2 will be help- ful. keep in mind that basic rf-design rules for circuit design should be taken into account. especially longer signal lines should not be used without termi- nation. see e.g. "the art of electronics" paul horow- itz, wienfield hill, 1989, cambridge university press, isbn: 0521370957. table 2. recommended application circuit components figure 1. recommended a pplication circuit ired anode v cc ground v cc2 v cc1 gnd sd txd rxd sd txd rxd r1 r2 c1 c2 19297 component recommended value c1, c2 0.1 f, ceramic vishay part# vj 1206 y 104 j xxmt r1 2.9 v to 5.4 v supply voltage v cc2 : add a resistor in series, e.g. 4.7 r2 47 , 0.125 w (v cc1 2.5 v)
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 225 i/o and software in the description, already different i/os are men- tioned. different combinations are tested and the function verified with the special drivers available from the i/o suppliers. in special cases refer to the i/o manual, the vishay application notes, or contact directly vishay sales, marketing or application. programming pulse duration switching after power-on the tfbs5700 is in the default short pulse duration mode. some endecs are not able to decode short pulses as valid sir pulses. therefore an additional mode with an extended pulse duration as in standard sir transceivers was added in tfbs5700. tfbs5700 is set to the ?short output pulse? as default after power on, also after recovering from the shutdown mode (sd must have been longer active than 1.5 ms). for mode changing see the fol- lowing. to switch the tr ansceivers from the short pulse duration mode to the long pulse duration mode and vice versa, the programming sequences described below are required. setting to the endec compatibility mode with an rxd pulse duration of 2 s 1. set sd input to logic "high". 2. set txd input to logic "low". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. txd must be held for t h 200 ns. after waiting t h 200 ns txd. txd is now enable as normal txd input for the longer rxd - pulse duration mode. setting back to the default mode with 400 ns rxd-output pulse duration 1. set sd input to logic "high". 2. set txd input to logic "high". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. after waiting t h 200 ns txd is limited by the max- imum allowed pulse length. txd is now enabled as normal txd input. the timing of the pulse duration changing procedure is quite uncritical. however, the whole change must not take more than 600 s. see in the spec. ?shut- down active time window for programming? simplified method setting the device to the long pulse duration is nothing else than a short active sd pulse of less than 600 s. in any case a short sd pulse will force the device to leave the default mode and go the compatibility mode. backwards also an active sd can be used to fall back into the default mode by applying that signal for a minimum of 1.5 ms. that causes a power-on- reset and sets the device to the default short pulse mode. this simplified method takes more time but may be easier to handle. figure 2. mode switching timing diagram txd sd t s t h 50 % hig h:f ir low : sir 50 % 50 % 14873
www.vishay.com 226 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors recommended solder profiles solder profile for sn/pb soldering lead (pb)-free, recommended solder profile the tfbs5700 is a lead (pb)-free transceiver and qualified for lead (pb)-free processing. for lead (pb)-free solder paste like sn(3.0-4.0)ag(0.5-0.9)cu, there are two standard reflow profiles: ramp-soak- spike (rss) and ramp-to-spike (rts). the ramp- soak-spike profile was developed primarily for reflow ovens heated by infrared radiation. with widespread use of forced convection reflow ovens the ramp-to- spike profile is used increasingly. shown below in fig- ure 4 is vishay's recommended profiles for use with the tfbs5700 transceivers. for more details please refer to application note: smd assembly instruction (http://www.vishay.com/docs/82602/82602.pdf). wave soldering for tfduxxxx and tfbsxxxx transceiver devices wave soldering is not recommended. manual soldering manual soldering is the standard method for lab use. however, for a production process it cannot be rec- ommended because the risk of damage is highly dependent on the experience of the operator. never- theless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. storage the storage and drying processes for all vishay transceivers (tfduxxxx and tfbsxxx) are equiva- lent to msl4. the data for the drying procedure is given on labels on the packing and also in the application note "taping, labeling, storage and packing" (http://www.vishay.com/docs/82601/82601.pdf). figure 3. recommended solder pr ofile for sn/pb soldering 0 20 40 60 8 0 100 120 140 160 1 8 0 200 220 240 260 0 50 100 150 200 250 300 350 time/s temperat u re/c 2...4 c/s 2...4 c/s 10 s max. at 230 c 120 s...1 8 0 s 160 c max. 240 c max. 90 s max. 19431 figure 4. solder profile, rss recommendation 0 20 40 60 8 0 100 120 140 160 1 8 0 200 220 240 260 2 8 0 0 50 100 150 200 250 300 350 time/s temperat u re/c 20 s 2 c...4 c/s 2 c...4 c/s 90 s...120 s t 217 c for 50 s max t peak = 260 c max. 50 s max. t 255 c for 20 s max 19261
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 227 package dimensions in mm figure 5. tfbs5700 mechanical dimensions, tole rance 0.2 mm if not otherwise mentioned 19325_1 figure 6. tfbs5700 soldering footprint, toler ance 0.2 mm if not otherwise mentioned 19294
www.vishay.com 228 document number 84670 rev. 2.1, 25-sep-06 tfbs5700 vishay semiconductors reel dimensions 14017 dra w ing- n o.: 9. 8 00-5090.01-4 iss u e: 1; 29.11.05 tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4
tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 229 tape dimensions in mm 19286
vishay tfbs5700 document number 84670 rev. 2.1, 25-sep-06 vishay semiconductors www.vishay.com 230 ozone depleting subst ances policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releas es of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use vishay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vishay semiconductors against all claims, costs, damages, and expenses, arising out of , directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.

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