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1/16 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. high reliability serial eeproms wl-csp eeprom family spi bus BU9829GUL-W description BU9829GUL-W is serial eeprom built-in ldo regulator by spi bus interface. features eeprom part 1) 2,048 words 8 bits architecture serial eeprom 2) wide operating voltage range (1.6v 3.6v) 3) serial peripheral interface 4) self-timed write cycle with automatic erase 5) low power consumption write (3.6v) : 1.5ma (typ.) read (3.6v) : 0.5ma (typ.) standby (3.6v) : 0.1a (typ.) 6) auto-increment of registers address for read mode 7) 32 byte page write mode 8) data security defaults to power up with write-disabled state software instructions for write-enable/disable block writes protection by status register write inhibit at low vcc 9) initial data ffh in all address, 00h in status register and 10 in vset[1:0]. 10) data retention: 10 years 11) endurance : 100,000 erase/write cycles ldo regulator part 12) low power consumption standby (3.6v) : 0.1 a (typ.) operation (3.6v) : 0.1ma (typ.) 13) power on/off by enable pin 14) initial ldo output voltage 2.9v 15) setting output voltage by eeprom command (vset write) absolute maximum rating (ta=25 ) parameter symbol rating unit supply voltage vcc1(eeprom) -0.3 4.5 v vcc2(ldo) power dissipation pd 220 mw storage temperature tstg -65 125 operating temper ature topr -30 85 terminal voltage -0.3 vcc 0.3 v eeprom recommended operating condition parameter symbol rating unit supply voltage vcc1 1.6 3.6 v input voltage vin 0 vcc1 ldo regulator recommended operating condition parameter symbol rating unit supply voltage vcc2 2.9 3.6 v input voltage vin 0 vcc2 no.10001eat13
technical note 2/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. memory cell characteristics (ta=25 , vcc1=1.6 3.6v) input/output capacity (ta=25 , frequency=5mhz) parameter limits unit parameter symbol conditions limits unit min. typ. max. min. max. write/erase cycle *1 100,000 cycle input capacitance *1 c in v in =gnd 8pf data retention *1 10 year output capacitance *1 c out v out =gnd 8pf *1 : not 100% tested *1:not 100% tested eeprom dc operating characteristics (unless otherwise specified, ta=-30 85, vcc1=1.6 3.6v) parameter symbol limits unit test condition min. typ. max. "h" input voltage1 vih1 0.7xvcc1 vcc1+0.3 v 2.5 Qvcc1 Q 3.6v "h" input voltage2 vih2 0.75xvcc1 vcc1+0.3 v 1.6 Qvcc1 2.5v "l" input voltage1 vil1 -0.3 0.3xvcc1 v 2.5v Qvcc1 Q 3.6v "l" input voltage2 vil2 -0.3 0.25xvcc1 v 1.6v Qvcc1 2.5v "l" output voltage1 vol1 0 0.2 v iol=1.0ma , 2.5v Qvcc1 Q 3.6v "l" output voltage2 vol2 0 0.2 v iol=1.0ma , 1.6v Qvcc1 2.5v "h" output voltage1 voh1 vcc1-0.2 vcc1 v ioh=-0.4ma , 2.5v Qvcc1 Q 3.6v "h" output voltage1 voh2 vcc1-0.2 vcc1 v ioh=-100a , 1.6v Qvcc1 2.5v input leakage current ili -1 1 a vin=0 vcc1 output leakage current ilo -1 1 a vout=0 vcc1 , csb=vcc1 operating current write icc1 1.5 ma vcc1=1.8v , fsck =2mhz, te/w=5ms byte write, page write, write status register icc2 2.0 ma vcc1=2.5v , fsck =5mhz,te/w=5ms byte write, page write, write status register operating current read icc3 0.2 ma vcc1=1.8v , fsck=2mhz , so=open read, read status register icc4 0.6 ma vcc1=2.5v , fsck=5mhz,so=open read, read status register standby current isb 1.0 a vcc1=3.6v , csb=vcc1 , sck , si=vcc1/gnd ,so=open this product is not designed for protection against radioactive rays. eeprom ac operating characteristics (ta=-30 85 ) parameter symbol 1.6 Qvcc1 1.8v 1.8 Qvcc1 Q 3.6v unit min. typ. max. min. typ. max. sck clock frequency fsck 2.5 5 mhz sck high time tsckwh 200 80 ns sck low time tsckwl 200 80 ns csb high time tcs 200 90 ns csb setup time tcss 150 60 ns csb hold time tcsh 150 60 ns sck setup time tscks 50 50 ns sck hold time tsckh 50 50 ns si setup time tdis 50 20 ns si hold time tdih 50 20 ns output data delay time tpd 100 80 ns output hold time toh 0 0 ns outuput disable time *1 toz 200 80 ns sck rise time *1 trc 1 1 s sck fall time *1 tfc 1 1 s output rise time *1 tro 50 50 ns output fall time *1 tfo 50 50 ns write cycle time te/w 5 5 ms wait time from vcc1 on to eeprom command ton 15 15 ms *1 : not 100% tested
technical note 3/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. synchronous data input/output timing si data is latched into the chip at the rising edge of sck clock. address and data must be transferred from msb. so data toggles at the fa lling edge of sck clock. output data toggles from msb. ac condition pin configuration pin function land no. pin name i/o function a1 vcc1 power supply (eeprom) a2 csb in chip select control a3 sck in serial data clock input b1 vcc2 power supply (ldo) b2 si in start bit, op.code, address, serial data input b3 so out serial data output c1 v out out ldo regulator output c2 gnd ground (0v) c3 ldoen in ldo regulator enable ldo regulator dc operating characteristics (unless otherwise specified ta=-30 85) parameter symbol specification unit test condition min. typ. max. output voltage1-1 v out 1-1 2.9 3.0 3.2 v 3.2v Qvcc2 Q 3.6v, iout=0, 2ma, vset=1, 0=[1:1] output voltage1-2 v out 1-2 2.9 3.0 3.1 v 3.2v Qvcc2 Q 3.6v, iout=2, 10ma, vset=1, 0=[1:1] output voltage2-1 v out 2-1 2.8 2.9 3.1 v 3.1v Qvcc2 Q 3.6v, iout=0, 2ma, vset=1, 0=[1:0] output voltage2-2 v out 2-2 2.8 2.9 3.0 v 3.1v Qvcc2 Q 3.6v, iout=2, 10ma, vset=1, 0=[1:0] output voltage3-1 v out 3-1 2.7 2.8 3.0 v 3.0v Qvcc2 Q 3.6v, iout=0, 2ma, vset=1, 0=[0:1] output voltage3-2 v out 3-2 2.7 2.8 2.9 v 3.0v Qvcc2 Q 3.6v, iout=2, 10ma, vset=1, 0=[0:1] output voltage4-1 v out 4-1 2.6 2.7 2.9 v 2.9v Qvcc2 Q 3.6v, iout=0, 2ma, vset=1, 0=[0:0] output voltage4-2 v out 4-2 2.6 2.7 2.8 v 2.9v Qvcc2 Q 3.6v, iout=2, 10ma, vset=1, 0=[0:0] operating current i cc - - 200 a vcc2=3.6v, iout=0a standby current i sb - - 1.0 a vcc2=3.6v, iout=0a, ldoen=gnd ?h? input voltage vih 1.4 - vcc2+0.3 v 2.9v Qvcc2 Q 3.6v ?l? input voltage vil -0.3 - 0.6 v 2.9v Qvcc2 Q 3.6v this product is not designed for protection against radioactive rays. parameter symbol limits unit min. typ. max. load capacitance cl - - 100 pf input rise times - - - 50 ns input fall times - - - 50 ns input pulse voltage - 0.25vcc1/0.75vcc1 v input and output timing reference voltages - 0.3vcc1/0.7vcc1 v fig.1 input timing fig.2 input and output timing 1 2 3 c b a c1 b1 a1 c2 b2 a2 index post c3 b3 a3 fig.3 pin configuration (bottom view) so si hi-z csb sck ton tcss tscks tsckwl tsckwh tdis tdih trc tfc vcc1 csb sck so si tcs tsckh tcsh hi-z toh toz tpd tro,tfo
technical note 4/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. ldo regulator ac operating characteristics parameter symbol specification unit test condition min. typ. max. vcc1 rise time tv cc 1 - - 5 msec vcc1 x 0% vcc1 x 95% point ldoen wait time t ldoen 15 - - msec vcc1 x 0%point ldoen=high output voltage depend on vset bit the 2bit data are stored into the vset memo ry and output voltage change among vout1 vout4. vset data are written into non-volatile memory array. initial vset data is 1,0 in vset[1:0] and vout is 2.9v. step vout(typ.) [v] vset1 vset0 vout1 vout2 vout3 vout4 3.0 2.9 2.8 2.7 1 1 0 0 1 0 1 0 input power supply regulation timing using eeprom part in case of using eeprom part, be sure to raise vcc1 up to operating voltage. in this time, vcc2 has no connection with operating. using ldo regulator part in case of using ldo regulator part, be sure to raise vcc1 and vcc2 up to operating voltage. after rising vcc1, wait 15msec and rising ldoen. when ldoen is raised, vcc1 must be operating voltage. ldo regulato r power supply not operating t ldoen : min 15msec vcc1 eeprom power suppl y vcc2 ldoen tvcc1:max 5msec tvcc1:max 5msec not operating not operating operating operating t ldoen : min 15msec fig.4 using eeprom part, regulation timing fig.5 using ldo regulator part, regulation timing vcc2 ldo?`? vcc1 eeprom? eeprom? eeprom? eeprom power supply not operating operating not operating operating not operating ldo regulator power supply
technical note 5/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. block diagram characteristic data (the following characteristic data are typical values.) fig.6 block diagram instruction decode control clock generation voltage detection write inhibition high voltage generator instruction register 16,384 bit eeprom address register csb b.r vout setting register 2bit + resistor amp ldoen sck si address decoder 11bit data register so 11bit r/w amp 8bit 8bit vout 0 0.5 1 1.5 2 2.5 01234 vcc[v] icc3(read)[ma] fsck=2mhz data=aah spec ta=-30 ta=25 ta=85 0 2 4 6 8 10 12 01234 vcc[v] isb[a] spec ta=-30 ta=25 ta=85 0 1 2 3 4 5 01234 vcc[v] ili[a] spec ta=-30 ta=25 ta=85 0 0.5 1 1.5 2 2.5 3 0 0.4 0.8 1.2 ioh[ma] voh[v] spec ta=-30 ta=25 ta=85 0 1 2 3 4 5 01234 vout[v] ilo[a] spec ta=-30 ta=25 ta=85 0 1 2 3 4 01234 vcc[v] icc1[ma]] fsck=2mhz data=00h spec ta=-40 ta=-30 ta=25 ta=85 0 1 2 3 4 5 01234 vcc[v] vih[v] spec ta=-30 ta=25 ta=85 spec 0 0.2 0.4 0.6 0.8 1 0123 iol[ma] vol[v] spec ta=-30 ta=25 ta=85 fig.9 "l" output voltage vol 0 1 2 3 4 5 01234 vcc[v] vil[v] ta=-30 ta=25 ta=85 fig.10 "h" output voltage voh fig.11 input leak current ili fig.12 output leak current ilo fig.13 current consumption at write operation icc1 fig.14 consumption current at read operation icc3 fig.15 standby operation isb (eeprom) spec fig.7 "h" input voltage vih (eeprom) fig.8 "l" input voltage vil (eeprom)
technical note 6/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. characteristic data 0 20 40 60 80 100 120 01234 vcc[v] tpd [ns] spec ta=-30 ta=25 ta=85 spec 0 2 4 6 8 01234 vcc[v] te/w[ms] spec ta=-30 ta=25 ta=85 0 40 80 120 160 200 01234 vcc[v] tcss[ns] spec ta=-30 ta=25 ta=85 spec 0.1 1 10 100 01234 vcc[v] fsck[mhz] spec ta=-30 ta=25 ta=85 spec 0 40 80 120 160 200 01234 vcc[v] tcsh[ns] spec ta=-30 ta=25 ta=85 spec 0 50 100 150 200 250 01234 vcc[v] tsckwh [ns] spec ta=-30 ta=25 ta=85 spec fig.17 sck high time tsckwh 0 50 100 150 200 250 01234 vcc[v] tsckwl [ns] spec ta=-30 ta=25 ta=85 spec fig.18 sck low time tsckwl 0 50 100 150 200 250 01234 vcc[v] tcs[ns] spec ta=-30 ta=25 ta=85 spec fig.20 csb setup time tcss fig.21 csb hold time tcsh fig.23 si hold time tdih 0 50 100 150 200 250 01234 vcc[v] toz [ns] spec ta=-30 ta=25 ta=85 spec fig.26 write cycle time te/w 0 20 40 60 01234 vcc[v] tdis[ns] ta=-30 ta=25 ta=85 spec spec 0 20 40 60 01234 vcc[v] tdih[ns] spec ta=-30 ta=25 ta=85 spec 0 2 4 6 8 01234 vcc[v] isb[us] spec ta=-30 ta=25 ta=85 fig.27 standby operation isb (ldo) 0 0.5 1 1.5 2 2.5 3 01234 vcc[v] vih[v] spec ta=-30 ta=25 ta=85 0 0.5 1 1.5 2 2.5 3 01234 vcc[v] vil[v] spec ta=-30 ta=25 ta=85 fig.30 vcc1 rise time tvcc1 0 40 80 120 160 01234 vcc[v] tvcc1[us] spec = 5000ns ta=-30 ta=25 ta=85 fig.16 sck frequency fsck fig.31 vout response (ldo) 2.7 2.8 2.9 3 3.1 3.2 0246810121416 iout[ma] vout[v] ( vset=1 , 0 ) ta=-30 ta=25 ta=85 spec spec spec fig.32 current consumption icc (ldo) 0 50 100 150 200 250 01234 vcc[v] icc[ua] spec ta=-30 ta=25 ta=85 fig.22 si setup time tdis fig.19 csb high time tcs fig.24 data output delay time tpd fig.25 output disable time toz fig.28 "h" input voltage vih (ldo) fig.29 "l" input voltage vil (ldo)
technical note 7/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. functional description status register the device has status register. status register consists of 8bits and is shown following parameters. 2 bits (bp0 and bp1) are set by ?write status register? commands, which are non-volatile. specification of endurance and dat a retention are as well as memory array. wen bit is set by ?write enable? and ?write disable? commands. after power become on, the device is disable mode. b/r bit is a read-only and status bit. the device is clocked out value of the status r egister by ?read status register? command input. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 bp1 bp0 wen b/r bit definition bp1 bp0 block write protection bp0/bp1 block write protection for memory array (eeprom) 0 0 1 1 0 1 0 1 none 600h-7ffh 400h-7ffh 000h-7ffh wen write enable/disable status bit wen=0 : write disable wen=1 : write enable b/r ready/busy status bit b/r =0 : ready b/r =1 : busy instruction code instruction operation op.code address wren write enable 0000 0110 - wrdi write disable 0000 0100 - read read data from memory array 0000 0011 a10 a0 write write data to memory array 0000 0010 a10 a0 rdsr read status register 0000 0101 - wrsr write status registe 0000 0001 - vset_read read vset data 0000 0011 800h vset_write write vset data 0000 0010 800h timing chart 1. write enable 2. write disable the device has both of the enable and dis able mode. after ?write enable? is exec uted, the device becom es in the enable mode. after ?write disable? is executed, the device becomes in the disable mode. after csb goes low, each of op.code is recognized at the rising edge of 7th clo ck. each of instructions is effective i nputting seven or more sck clocks. this ?write enable? instruction must be pr oceeded before the any write commands. the device ignores inputting the any write commands in the disable mode. once the any write commands is executed in the enable mode, the device becomes the disable mode. after the power become on, the device is in the disable mode. fig.33 write enable cycle timing fig.34 write disable cycle timing hi-z 76 03 csb sck so si 12 45 00001 010 hi-z 0 si 0 0100 6 03 12 4 7 00 csb sck 5 so
technical note 8/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. 3. read the data stored in the memory are clocked out after ?read? in struction is received. after csb goes low, the address need to be sent following by op.code of ?read?. the data at the address specified are clock ed out from d7 to d0, which is start at the falling edge of 23th clock. this device has the auto-increment feature that provides the whole data of the memory array with one read command, outputs the next address data following the addressed 8bits of data by keeping sck clocking. when the highest address is reached, the address counter rolls over to the lowest address allowing the continuous read cycle. 4. write this ?write? command writes 8bits of data into the specif ied address. after csb goes low, the address need to be sent following by op.code of ?write?. between the rising edge of the 29th clock and it of the 30th cl ock, the rising edge of csb initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if csb is high except that period. it takes maximum 5ms in high vo ltage cycle (te/w). the device does not receive any command except for ?read status register? command during this high voltage cycle. this device is ca pable of writing the data of maximum 32byte into me mory array at the same time, which keep inputting two or more byte data with csb ?l? after 8bits of data input. for this page write commands, the eight higher order bits of address are set, the six low order address bits are internally incremented by 5bits of data i nput. if more than 16 words, ar e transmitted the address counter ?roll over?, and the previous transmitted data is overwritten. 5. rdsr (read status register) the data stored in the status register is clocked out after ?read status register? instruction is received. after csb goes low, op.colde of ?read status register? need to sent. the data stored in the stat us register is clocked out of the device on the falling edge of 7th clock. bit7, bit6, bit5 and bit4 in the status register are read as 0. this device has the auto-increment featur e as well as ?read? that output the 8bits of the same data following it to keep sck clocking. it is possible to see ready and busy state by executing this command during te/w. if more than 16 words, are transmitted the address counter ?roll over? and the previous transmitted data is overwritten. hi -z *=don't care 14 11 0 0 3 7 1 2 d6 so csb sck si 4 5 0 a 10 6 8 ** a 0 a 1 d7 23 30 24 d0 0 0 0 0 0 d 2 d1 fig.35 read cycle timing fig. 36 write cycle timing hi-z *=don't care 31 d0 0 0 0 0 0 d2 d1 d7 23 30 24 d6 0 a 0 a 1 * 1 1 2 4 0 csb sck si so 0 3 7 8 5 6 0 a 1 0 14 fig.37 read status register cycle timing hi-z bit7 bit6 bit5 bit4 00 bp0 0 bp1 bit3 bit2 bit1 bit0 13 csb sck si 1 1 10 6 0 so 14 1 2 wen r/b 11 15 3 7 9 0 5 12 0 0 0 0 0 4 8 0
technical note 9/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. 6. wrsr (write status resister) this ?write status register? command writes the data, two ( bp1, bp0) of the eight bits, into the status register. write protection is set by bp1 and bp0 bits. after csb goes low, op.code of ?read status register? need to sent. between the rising edge of the 15th clock and it or the 16th clock, the rising edge of csb initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is c ancelled if csb is high except that period. it takes maximum 5ms in high voltage cycle (te/w) as well as ?write?.block wr ite protection is determined by bp1 and bp0 bits, which is selected from quarter, half and the entire memory array. (see table2 block write protection>) 7. vset read the vset data stored in the memory are clocked out after ?vset read? instruction set address 800h is received. after csb goes low, the address (800h) need to be sent follow ing by op.code of ?read?. 0 are clocked out from d7 to d2 and the vset data are clocked out from d1 to d0, wh ich is start at the falling edge of 23th clock. 8. vset write this ?write? command set address 800h writes vset data into vset1 and vset0 memory array. after csb goes low, the address (800h) and vset data need to be sent following by op .code of ?vset write?. betw een the rising edge of the 29th clock and it of the 30th clock, t he rising edge of csb initates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if c sb is high except that period. it takes maximum 5ms in high voltage cycle (te/w). the device does not receive any command except for ?read status register? command during this high voltage cycle. fig. 38 write status register write cycle timing fig.39 vset read cycle timiing fig. 40 vset write cycle timing so bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 13 csb sck si 1 1 10 6 0 14 1 2 11 15 3 7 9 0 5 12 0 0 0 0 0 4 8 hi-z * don?t care * * * * bp1 bp0 * * * don?t care so csb sck si 1 12 6 0 23 1 2 13 24 3 7 5 0 0 0 0 0 4 8 hi-z * * 1 0 0 1 0 0 0 0 0 0 30 vset 1 vset 0 so * don?t care csb sck si 0 12 6 0 23 1 2 13 24 3 7 5 0 0 0 0 0 4 8 hi-z * * 1 0 0 0 0 0 1 30 vset 1 vset 0 * * * * 31
technical note 10/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. eeprom soft ware read, vset_read, rdsr command cancel cancel of these commands is possible by changing csb pin to ?high? in all sections. write, page_write, vset_write wrsr command cancel cancel of these write command is possible by changing csb pin to ?high? in opecode, address and data input sections (section a~b), but it is impossible after data input section (section c~d), if vcc1 is off during te/w, please write again because write data is not guaranteed in sp ecified address, if sck and csb rise at the same time in section c, command is instability. it is recommend to rise csb in ?sck=l? section. wren, wrdi command cancel cancel of these commands is possible by changing csb pin to ?high? of opecode to rising 8 clk, but it is impossible after rising 8 clk. in the case, please send wren or wrdi cancel timing command again. data polling if rdsr command is carried out daring te/w, according to out put data ( b/r bit), to monitor ready/busy state is possible. because of this, it is possible to send next comm and earlier than regular programming time (te/w max=5ms). if b/r bit is ?1?, eeprom?s state is ?busy?. if this becomes ?0?, it is possible to send next command to change eeprom to ?ready? state. status register data read by this command in te/w is not data written by wrsr command but old data before. status register dat a in each section is shown below. csb sck si so busy ready during wrsr command te/w d=0ch e=00h read status registor write status registor read status registor read status registor read status registor a=0ch b=(00h) c=0fh fig.43 write, page_write, vset_wr ite read vset_read cancel timing d7 b d6 d5 d4 d3 d2 d1 d0 sck si c an enlargement d1 d0 sck si 14 15 16 17 c b d fig.44 wrsr cancel timing opecode 8bit address data(n) te/w 8bit 8bit a b d c opecode 8bit data(n) te/w 8bit 8bit an enlargement opecode 8bit a b 78 9 a b fig.45 wren, wrdi cancel timing an enlargement a b d c opecode data 8bit 8bit cancel is possible fig.42 rdsr cancel timing opecode address data 8bit 8bit 8bit cancel is possible fig.41 read, vset_read cancel timing fig.46 status register data in each section
technical note 11/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. eeprom part 1. hardware connection of eeprom eeprom may have malfunction owing to noise signal for input pin, and movement in the low voltage region at power on/off. these malfunctions may occur, especially at min voltage limit of eeprom or below. to avoid this, please note about hardware connection showed as follows. 1.1 input terminals input equivalent circuits of csb, sck and si are showed fig.47, 48. input terminal is connected between cmos schmitt tri gger input circuit and input protection circuit. these pin are not pull up or pull down, therefore please don?t input hi-z in us e. and please make csb ?high? in the low voltage region at power on/off. if csb is "low" at power on/off, malfunction may occur. to make other input terminals pull up or pull down is recommendable. 1.2 output terminals output equivalent circuit of so is showed fi g.49. this output terminal is 3 states buffer. the data is output from so at output timing by read command, so is hi-z except this timing. if eeprom malfunction occur by hi-z input of the microcontroll er port connected with so, please make so pull up or pull down. if it doesn?t affected the microcontroller movement to make so open, it is no problem. load capacity of so disturb high speed movement of eeprom. if this load capacity is 10 0pf or below, BU9829GUL-W can move in 2.5mhz (vcc1=1.6v~1.8v) or 5mhz (vcc1=1.8v~3.6v) 1.3 input pin pull up, pull down resistance the design method of pull up/pull down resist ance for input and output are as follows. 1.3.1 pull up resistance rpu of input terminals csb fig.47 csb terminals equivalent circuit sck, si example) when vcc=5v, v ile =1.5v, v olm =0.4v, i olm =2ma, from the equation , ?v ile : eeprom v il specifications ?v olm : microcontroller v ol specifications ?i olm : microcontroller i ol specifications fig.50 input terminal pull up resistance rpu R 2.3[k] rpu R 5 0.4 210 -3 with the value of rpu to satisfy the above equation, v olm becomes 0.4v or below, and with v ile (=1.5v), the equation is also satisfied. rpu R v olm Q v ile v cc v olm i olm microcontroller eeprom ?l? input ?l? output rpu i olm v olm v ile fig.48 sck,si terminals equivalent circuit fig.49 so terminals equivalent circuit
technical note 12/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. 1.3.2 pull down resistance rpd of input terminals 1.3.3 pull up resistance rpu of so pin 1.3.4 pull up resistance rpu of so pin example) when vcc=5v, v ihe =3.5v, v ohm =2.4v, i ohm =2ma, from the equation , fig.51 input terminals pull down resistance rpd R 1.2 [k ] rpd R 2.4 210 -3 rpd R v ohm Q v ihe v ohm i ohm ?v ihe : eeprom v ih specifications ?v ohm : microcontroller v oh specifications ?i ohm : microcontroller i oh specifications with the value of rpd to satisfy the above equation, v ohm becomes 2.4v or higher, and with v ihe (=3.5v), the equation is also satisfied. microcontroller eeprom ?h? input ?h? output rpd v ohm v ihe i ohm example) when vcc=5v, v ole =0.4v, v ilm =1.5v, i ole =2.1ma, from the equation , fig.52 so pull up resistance rpu R 2.2 [k ] rpu R 5-0.4 2.110 -3 rpu R v ole Q v ilm v cc -v ole i ole with the value of rpd to satisfy the above equation, v ole becomes 0.4v or higher, and with v ilm (=1.5v), the equation is also satisfied. ?v ole : eeprom v ol specifications ?i ole : microcontroller i ol specifications ?v ilm : microcontroller v il specifications microcontroller eeprom ?l? output ?l? input rpu v ilm v ole i ole fig.53 so pull down resistance rpd R 11.3 [k ] rpd R 5-0.5 0.410 -3 rpd R v ohe R v ihm v ohe i ohe with the value of rpu to satisfy the above equation, v ohe becomes 4.5v or higher, and with v ihm (=3.5v), the equation is also satisfied. ?v ohe : eeprom v oh specifications ?i ohe : eeprom i oh specifications ?v ihm : microcontroller v ih specifications microcontroller eeprom ?h? output ?h? input rpd v ihm v ohe i ohe example) when vcc=5v, v ohe =vcc-0.5v, v ihm =vccx0.7v, i ohe =0.4ma, from the equation ,
technical note 13/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. ldo regulator part ldo regulator part of bu9829 gul-w is cmosldo of low power consumptio n. the data are stored into eeprom and output voltage change among 2.7~3.0v. 1s tep is 0.1v. ldo regulator part had ld oen pin and vout pin. to make this ldoen pin low is standby mode of low power consumption. ldoen input terminals input equivalent circuit of ldoen is showed fig.54. input terminal is connected between input circuits made from nmos and pull up and input protection circuit. this pin is not pull up or pull down, therefore please don?t input hi-z. if ldoen is low, all circuit don?t move and ldo part is standby mode of low power consumption. vout output terminals output equivalent circuit of vout is showed fig.55. if ldoen is high, ldo re gulator output regulate voltage from vout pin. if ldoen is low, vout pin is gnd by vout-g nd resistance. output overshoots change by output capacity, in actual use, please evaluate and decide output capacity. ldoen fig.54 vout output terminals vref - + vout fig.55 vout output terminals fig.56 cl=0f transitional response fig.57 cl=0.1f transitional response fig.58 cl=1.0f transitional response fig.59 cl=10f transitional response BU9829GUL-W evaluation result (i out =0ma 4ma,c out =1.0uf) BU9829GUL-W evaluation result (i out =0ma 4ma,c out =1.0uf) rising 1us iout=0 4ma 13.6us 172mv vout oscilloscope tektronix tds3034b power source showa 317b vcc vout ldo_e n vcc=3.0v 0.1uf 700 rohm k2095n input pulse current measurement circuit probe 20us 88mv vout rising 1us iout=0 4ma oscilloscope tektronix tds3034b power source showa 317b vcc vout ldo_e n vcc=3.0v 0.1uf 700 rohm k2095n input pulse current measurement circuit probe 40mv vout rising1us iout=0 4ma 12us oscilloscope tektronix tds3034b power source showa 317b vcc vout ldo_e n vcc=3.0v 0.1uf 700 rohm k2095n input pulse current measurement circuit probe 40mv vout 120us rising 1us iout=0 4ma oscilloscope tektronix tds3034b power source showa 317b vcc vout ldo_e n vcc=3.0v 0.1uf 700 rohm k2095n input pulse current measurement circuit probe BU9829GUL-W evaluation result (i out =0ma 4ma,c out =1.0uf) BU9829GUL-W evaluation result (i out =0ma 4ma,c out =0.1uf)
technical note 14/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. package power dissipation package power dissipation of BU9829GUL-W is 220mw. it is the value at environ mental temperature is 25 . in the case of use at 25 or higher, degradation is done at 2.2w/ . if output current is very large, please take care of package power dissipation. large current protection circuit vout terminal has large current protection circuit. this circui t protects ic from large current. however, this protection circuit effective unexpected accident. please avoid continual use of protection circuit. por circuit this ic has a por (power on reset) circuit as mistake writ e countermeasure. after por acti on, it gets in write disable. the por circuit is valid only when power is on, and does not work when power is off. when power is on, if the recommended conditions of the following tr, toff, and vbot are not satisfied, it may become write enable status owing to noise the likes. fig.62 rise waveform recommended conditions of tr, toff, vbot tr toff vbot 10ms or below 10ms or higher 0.3v or below 100ms or below 10ms or higher 0.2v or below toff tr vbot 0 v 1 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 vout load current [ma] vout output voltage[v] 0 100 200 300 -50 -25 0 25 50 75 100 125 150 ??(ta)[] S?p?(pd) [mw] pd [mw] ta [] fig.60 package power dissipation fig.61 large current protection circuit
technical note 15/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. lvcc circuit lvcc (vcc-lockout) circuit prevents data rewrite ac tion at low power, and prevents wrong write. at lvcc voltage (typ. =1.9v) or below, it prevent data rewrite. noise countermeasures vcc noise (bypass capacitor) when noise or surge gets in the power source line, malfunc tion may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1f) between ic v cc and gnd. at that moment, atta ch it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. recommendable application circuit notes for use ? absolute maximum ratings we pay attention to quality control of this ic, but if there is special mode e xceeded absolute maximum rating, please take a physical safety measures. because we ca n?t specify short mode and open made, etc. ? heat design in consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. ? absolute maximum ratings if the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperatur e exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. ? common impedance please pay attention to vcc and gnd wiring. for example, lower common impedance and to make wiring think, etc. ? gnd electric potential set the voltage of gnd terminal lowest at any action condition. and, please ma ke pin except gnd voltage of gnd or over. ? test of set base if low impedance pin connect with capacity at test of set ba se, please discharge each test progress to stress ic. please embroider earth for static electricity n easures at structure progre ss, pay attention to carry and conservation. when set base connect with test base at test progress, please connect and remove from power off. fig.63 vcc noise countermeasures example r pu csb sck si ldoen vout gnd vcc2 so vcc1 c vcc1(1.8v) BU9829GUL-W ( 0.1f) fig.64 recommendable application circuit vcc2(3.3v) r pd c l c ( 0.1f) r pd r pu capacitor 10 100f ic print base capacitor 0.01 0.1f gnd vcc 1. it is recommended to attach bypass condensers on power line. 2. be sure to make csb pull up. at power on, mat cause the abnormal function. 3. please make ldoen pull down. 4. if eeprom malfunction occur by hi-z input of the microcontroller part connected with so, please make so pull up or pull down. 5. please attach capacity at vout terminal. outputs overshoot change by output capacity. in actual use, please evaluate and decide output capacity.
technical note 16/16 BU9829GUL-W www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. ordering part number b u 9 8 2 9 g u l - w e 2 part no. part no. package gul : vcsp50l1 w-cell packaging and forming specification e2: embossed tape and reel (unit : mm) vcsp50l1 (BU9829GUL-W) 0.3250.05 s 0.08 s a b ba 0.05 1pin mark 3 0.370.05 9- 0.250.05 1.740.05 2 ( 0.15)index post c 1 b 0.55max 1.650.05 a 0.10.05 p=0.52 p=0.52 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () direction of feed reel 1pin
r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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