? semiconductor components industries, llc, 2002 april, 2002 rev. 1 1 publication order number: ntqs6463/d ntqs6463 power mosfet 6.8 amps, 20 volts pchannel tssop8 features ? new low profile tssop8 package ? ultra low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? diode exhibits high speed, soft recovery ? avalanche energy specified ? i dss and v ds(on) specified at elevated temperatures applications ? power management in portable and batterypowered products, i.e.: computers, printers, pcmcia cards, cellular and cordless telephones ? lithium ion battery applications ? note book pc maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 20 vdc gatetosource voltage v gs 12 vdc drain current (note 1) continuous @ t a = 25 c continuous @ t a = 70 c pulsed (note 3) i d i d i dm 5.5 4.4 30 adc total power dissipation (note 1) @ t a = 25 c p d 0.93 w drain current (note 2) continuous @ t a = 25 c continuous @ t a = 70 c pulsed (note 3) i d i d i dm 6.8 5.4 30 adc total power dissipation (note 2) @ t a = 25 c p d 1.39 w operating and storage temperature range t j , t stg 55 to +150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 40 v, i l = 18.4 a, l = 5.0 mh, r g = 25 ) e as 845 mj thermal resistance junctiontoambient (note 1) junctiontoambient (note 2) r ja 134 90 c/w 1. minimum 3 x 3 fr4 board, steady state. 2. mounted on 1 square (1 oz.) board, steady state. 3. pulse test: pulse width = 300 s, duty cycle = 2%. device package shipping ordering information ntqs6463 tssop8 100 units/rail tssop8 case 948s plastic 1 pin assignment 8 2 d s s g 3 4 1 7 6 5 8d s s d top view ntqs6463r2 tssop8 3000/tape & reel 463 yww n d s g pchannel 6.8 amperes 20 volts r ds(on) = 20 m w marking diagram 463 = device code y = year ww = work week n = mosfet http://onsemi.com
ntqs6463 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit static gate threshold voltage (v ds = v gs , i d = 250 m a) v gs(th) 0.45 0.9 vdc gatebody leakage (v gs = 0 vdc, v gs = 8 vdc) i gss 100 nadc zero gate threshold voltage drain current (v ds = 16 vdc, v gs = 0 vdc) (v ds = 16 vdc, v gs = 0 vdc, t j = 70 c) i dss 1.0 10 ma dc drainsource onstate resistance (note 4) (v gs = 4.5 vdc, i d = 6.8 adc) (v gs = 2.5 vdc, i d = 5.5 adc) r ds(on) 0.016 0.022 0.020 0.027 w forward transconductance (v ds = 15 vdc, i d = 6.8 adc) (note 4) g fs 21 s diode forward voltage (i s = 1.3 adc, v gs = 0 vdc) (note 4) v sd 0.71 1.1 vdc dynamic total gate charge (v ds = 10 vdc, q g 28 50 nc gatesource charge (v ds = 10 vdc , v gs = 5.0 vdc, i 68ad ) q gs 5.5 gatedrain charge gs i d = 6.8 adc) q gd 9.0 turnon delay time (v = 10 vdc t d(on) 15 25 ns rise time (v dd = 10 vdc, i d @ 1.0 adc, t r 22 40 turnoff delay time i d @ 1 . 0 adc , v gs = 4.5 vdc, r g =60 w ) t d(off) 90 150 fall time r g = 6 . 0 w ) t f 53 90 sourcedrain reverse recovery time (i f = 1.3 adc, di/dt = 100 a/ m s) t rr 45 80 ns 4. pulse test: pulse width 300 m s, duty cycle 2%.
ntqs6463 http://onsemi.com 3 t j = 55 c t j = 100 c 2.4 v figure 1. onregion characteristics figure 2. transfer characteristics v ds , draintosource voltage (v) v gs , gatetosource voltage (v) 1.75 1.5 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 2 1.5 1 0.5 0 0 4 8 12 figure 3. onresistance versus gatetosource voltage figure 4. onresistance versus drain current and gate voltage v gs , gatetosource voltage (v) i d , drain current (a) 10 8 6 4 2 0 0 0.01 0.02 0.03 0.05 14 12 10 8 6 4 2 0.01 0.015 0.02 0.025 0.03 figure 5. onresistance variation versus temperature figure 6. draintosource leakage current versus voltage t j , junction temperature ( c) v ds , draintosource voltage (v) 150 125 100 75 50 25 0 0.6 0.8 1 1.2 1.6 16 12 8 4 10 100 1000 i d , drain current (a) 2 2.5 16 i d , drain current (a) 0.04 r ds(on) , draintosource resistance ( ) r ds(on) , draintosource resistance ( ) 1.4 r ds(on) , draintosource resistance (normalized) 20 i dss , leakage (na) v gs = 1.4 v 1.6 v 1.8 v 2 v 2.2 v 6 v 4 v 10 v 2.8 v t j = 25 c v ds 10 v t j = 25 c i d = 7.4 a t j = 25 c t j = 25 c v gs = 2.5 v gs = 4.5 25 50 i d = 7.4 a v gs = 4.5 v t j = 125 c v gs = 0 v t j = 100 c
ntqs6463 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. figure 7. capacitance variation gatetosource or draintosource voltage (v) 15 10 5 0 5 10 0 1000 2000 3000 4000 5000 6000 c, capacitance (pf) 20 t j = 25 c v ds = 0 v v gs = 0 v gs v ds c iss c iss c oss c rss c rss
ntqs6463 http://onsemi.com 5 figure 8. gatetosource and draintosource voltage versus total charge figure 9. resistive switching time variation versus gate resistance q g , total gate charge (nc) r g , gate resistance ( ) 24 20 16 12 8 4 0 0 1 2 3 4 5 10 1 10 100 figure 10. diode forward voltage versus current v sd , sourcetodrain voltage (v) 0.7 0.6 0.5 0.4 0 0.4 0.8 v gs , gatetosource voltage (v) 28 100 1000 t, time (ns) 1.2 i s , source current (a) v dd = 16 v i d = 6.8 a v gs = 4.5 v v gs = 0 v t j = 25 c t j = 25 c i d = 6.8 a v gs = 4.5 qt q1 q2 t d(off) t d(on) t f t r v ds , draintosource voltage (v) safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r , t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature. maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntqs6463 http://onsemi.com 6 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c --- 1.10 --- 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.70 0.020 0.028 g 0.65 bsc 0.026 bsc l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. seating plane pin 1 1 4 85 detail e b c d a g l 2x l/2 u s u 0.20 (0.008) t s u m 0.10 (0.004) v s t 0.076 (0.003) t v w 8x ref k ident k 0.19 0.30 0.007 0.012 s u 0.20 (0.008) t p1 p detail e f m 0.25 (0.010) ??? ??? k1 k jj1 section nn j 0.09 0.20 0.004 0.008 k1 0.19 0.25 0.007 0.010 j1 0.09 0.16 0.004 0.006 p --- 2.20 --- 0.087 p1 --- 3.20 --- 0.126 n n tssop8 case 948s01 issue o
ntqs6463 http://onsemi.com 7 notes
ntqs6463 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntqs6463/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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