KM64258E cmos sram preliminary rev 0.0 - 1 - august 1998 document title 64kx4 bit (with oe ) high speed static ram(5v operating), evolutionary pin out. revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of th is device. if you have any questions, please contact the samsung branch office near your office, call or contact headquarters. rev no. rev. 0.0 remark preliminary history initial draft draft data aug. 1. 1998
KM64258E cmos sram preliminary rev 0.0 - 2 - august 1998 pin function pin name pin function a 0 - a 15 address inputs we write enable cs chip select oe output enable i/o 1 ~ i/o 4 data inputs/outputs v cc power(+5.0v) v ss ground n.c no connection 64k x 4 bit high-speed cmos static ram the KM64258E is a 262,144-bit high-speed static random access memory organized as 65,536 words by 4 bits. the KM64258E uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. the device is fabricated using samsung s advanced cmos process and designed for high-speed circuit technology. it is particularly well suited for use in high-density high-speed system applications. the KM64258E is packaged in a 300 mil 28-pin plastic soj . general description features ? fast access time 10,12,15ns(max.) ? low power dissipation standby (ttl) : 20 ma (max.) (cmos) : 2 ma (max.) operating KM64258E - 10 : 70 ma (max.) KM64258E - 12 : 70 ma (max.) KM64258E - 15 : 70 ma (max.) ? single 5.0v 10% power supply ? ttl compatible inputs and outputs ? i/o compatible with 3.3v device ? fully static operation - no clock or refresh required ? three state outputs ? standard pin configuration KM64258Ej : 28-soj-300 clk gen. a 0 i/o 1 ~i/o 4 cs we oe a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 r o w s e l e c t data cont. column select clk gen. pre-charge-circuit memory array 512 rows 128x4 columns i/o circuit a 9 a 10 a 11 a 12 pin configuration (top view) soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc a 15 a 14 a 13 a 12 a 11 a 10 n.c. n.c. i/o 4 i/o 3 i/o 2 i/o 1 we n.c a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 cs oe v ss a 13 a 14 a 15 functional block diagram
KM64258E cmos sram preliminary rev 0.0 - 3 - august 1998 recommended dc operating conditions (t a =0 to 70 c) * v il (min) = -2.0(pulse width 7ns) for i 20ma ** v ih (max) = v cc +2.0v(pulse width 7ns) for i 20ma parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc +0.5** v input low voltage v il -0.5* - 0.8 v dc and operating characteristics (t a =0 to 70 c,v cc =5.0v 10% unless otherwise specified) * v cc =5.0v, temp.=25 c parameter symbol test conditions min max unit input leakage current i li v in = v ss to v cc -1 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il v out = v ss to v cc -1 1 m a operating current i cc min. cycle, 100% duty cs =v il, v in = v ih or v il, i out =0ma 10ns - 70 ma 12ns - 70 15ns - 70 standby current i sb min. cycle, cs =v ih - 20 ma i sb1 f=0mhz, cs 3 v cc -0.2v, v in 3 v cc -0.2v or v in 0.2v - 2 ma output low voltage level v ol i ol =8ma - 0.4 v output high voltage level v oh i oh =-4ma 2.4 - v v oh1* i oh1 =0.1ma - 3.95 v capacitance* (t a =25 c, f=1.0mhz) * note : capacitance is sampled and not 100% tested. item symbol test conditions min max unit input/output capacitance c i/o v i/o =0v - 8 pf input capacitance c in v in =0v - 7 pf absolute maximum ratings* * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to 7.0 v voltage on v cc supply relative to v ss v cc -0.5 to 7.0 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a 0 to 70 c
KM64258E cmos sram preliminary rev 0.0 - 4 - august 1998 test conditions parameter value input pulse levels 0v to 3v input rise and fall times 3ns input and output timing reference levels 1.5v output loads see below ac characteristics (t a =0 to 70 c, v cc =5.0v 10%, unless otherwise noted.) output loads(a) output loads(b) d out 5pf* 480 w 255 w for t hz , t lz , t whz , t ow, t olz & t ohz +5.0v d out 30pf* 480 w 255 w +5.0v * including scope and jig capacitance read cycle parameter symbol KM64258E-10 KM64258E-12 KM64258E-15 unit min max min max min max read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip select to output t co - 10 - 12 - 15 ns output enable to valid output t oe - 5 - 6 - 7 ns chip enable to low-z output t lz 3 - 3 - 3 - ns output enable to low-z output t olz 0 - 0 - 0 - ns chip disable to high-z output t hz 0 5 0 6 0 7 ns output disable to high-z output t ohz 0 5 0 6 0 7 ns output hold from address change t oh 3 - 3 - 3 - ns chip selection to power up time t pu 0 - 0 - 0 - ns chip selection to power downtime t pd - 10 - 12 - 15 ns
KM64258E cmos sram preliminary rev 0.0 - 5 - august 1998 address data out previous valid data valid data timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) cs address oe data ou t t aa t olz t lz(4,5) t oh t rc t oe t co t pu t pd t hz(3,4,5) 50% 50% v cc current i cc i sb valid data t ohz write cycle parameter symbol KM64258E-10 KM64258E-12 KM64258E-15 unit min max min max min max write cycle time t wc 10 - 12 - 15 - ns chip select to end of write t cw 8 - 9 - 10 - ns address setup time t as 0 - 0 - 0 - ns address valid to end of write t aw 8 - 9 - 10 - ns write pulse width( oe high) t wp 8 - 9 - 10 - ns write pulse width( oe low) t wp1 10 - 12 - 15 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 5 0 6 0 7 ns data to write time overlap t dw 5 - 6 - 7 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 0 - 0 - 0 - ns
KM64258E cmos sram preliminary rev 0.0 - 6 - august 1998 notes (read cycle) 1. we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs =v il. 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. timing waveform of write cycle(1) ( oe = clock) address cs t wp(2) t dw t dh valid data we data in data out t wc t wr(5) t aw t cw(3) high-z(8) high-z oe t ohz(6) t as(4) timing waveform of write cycle(2) ( oe =low fixed) address cs t wp1(2) t dw t dh t ow t whz(6) valid data we data in data out t wc t as(4) t wr(5) t aw t cw(3) (10) (9) high-z(8) high-z
KM64258E cmos sram preliminary rev 0.0 - 7 - august 1998 timing waveform of write cycle(3) ( cs =controlled) address cs t aw t dw t dh valid data we data in data out high-z high-z(8) t cw(3) t wp(2) t as(4) t wc t wr(5) high-z high-z t lz t whz(6) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low cs and we . a write begins at the latest transition cs going low and we going low ; a write ends at the earliest transition cs going high or we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. if cs goes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. functional description * note : x means don t care. cs we oe mode i/o pin supply current h x x* not select high-z i sb , i sb1 l h h output disable high-z i cc l h l read d out i cc l l x write d in i cc
KM64258E cmos sram preliminary rev 0.0 - 8 - august 1998 package dimensions units:millimeters/inches #1 28-soj-300 #28 18.41 0.12 0.725 0.005 7 . 6 2 0 . 3 0 0 + 0.10 max 18.82 0.741 0.20 - 0.05 + 0.004 0.008 - 0.002 6.86 0.25 0.270 0.010 max 0.148 3.76 min 0.69 0.027 1.30 ( ) 0.051 1.30 ( ) 0.051 #14 #15 0.95 ( ) 0.0375 + 0.10 0.43 - 0.05 + 0.004 0.017 - 0.002 + 0.10 0.71 - 0.05 + 0.004 0.028 - 0.002 1.27 0.050 0.004 0.10 max 8.51 0.12 0.335 0.005
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