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STP16CP596 2/18 table 2: typical current accuracy figure 1: pin connection (note 1) note 1: the exposed pad is electrically not connected. table 3: pin description output voltage output current between bits between ics 0.1v 3 ma/v cc = 5v 3% 6% 0.15v 5 ma/v cc = 5v 2% 6% 0.25v 10 ma/v cc = 5v 2% 6% 0.5v 20 ma/v cc = 5v 1% 6% 1.2v 40 ma/v cc = 5v 1% 6% 1.4v 50 ma/v cc = 5v 1% 6% pin n symbol name and function 1 gnd ground terminal 2 sdi serial data input terminal 3 clk clock input terminal 4 /le latch input terminal 5-20 out 0-15 output terminal 21 /oe input terminal of output enable (active low) 22 sdo serial data out terminal 23 r-ext input terminal of an external resistor for constant current programing 24 v dd supply voltage terminal
STP16CP596 3/18 table 4: absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. under these conditions, functional opera tion is not implied. table 5: thermal data (*) the exposed pad should be soldered directly to the pcb to realize the thermal benefits. table 6: recommended operating conditions symbol parameter value unit v dd supply voltage 0 to 7 v v o output voltage -0.5 to 16 v i o output current 50 ma v i input voltage -0.4 to v dd +0.4 v i gnd gnd terminal current 800 ma f clk clock frequency 25 mhz t opr operating temperature range -40 to +125 c t stg storage temperature range -65 to +150 c symbol parameter dip-24 so-24 tssop24 tssop24 (*) (exposed pad) unit r thj-amb thermal resistance junction-ambient 60 75 85 37.5 c/w symbol parameter test conditions min. typ. max. unit v dd supply voltage 3.0 5.5 v v o output voltage 16.0 v i o output current outn 3 50 ma i oh output current serial-out +1 ma i ol output current serial-out -1 ma v ih input voltage 0.7v dd v dd +0.3 v v il input voltage -0.3 0.3v dd v t wlat /le pulse width v dd = 3.0 to 3.6v 20 ns t wclk clk pulse width 20 ns t wen /oe pulse width 400 ns t setup(d) setup time for data 20 ns t hold(d) hold time for data 15 ns t rem(l) removal time for latch 15 ns f clk clock frequency cascade operation 25 mhz
STP16CP596 4/18 table 7: electrical characteristics (v dd =3.3v to 5v, t = 25c, unless otherwise specified.) table 8: switching characteristics (v dd =3v, t = 25c, unless otherwise specified.) symbol parameter test conditions min. typ. max. unit v ih input voltage high level 0.7v dd v dd v v il input voltage low level gnd 0.3v dd v i oh output leakage current v oh = 16 v 10 a v ol output voltage (serial-out) i ol = 1ma 0.4 v v oh output voltage (serial-out) i oh = -1ma v dd -0.4v v i ol1a output current v o = 0.2v, r ext =6.2k ? , v dd =3.3v 2.85 3 3.15 ma i ol2a v o = 0.5v, r ext =1k ? , v dd = 3.3v 19.6 20 20.4 ma ? i ol1a output current error between bit (all output on) v o = 0.2v, r ext =6.2k ? , v dd =3.3v 4 6 % ? i ol2a v o = 0.5v, r ext =1k ? , v dd = 3.3v 2 3 % i ol1b output current v o = 0.2v, r ext =6.2k ? , v dd =5v 2.9 3 3.1 ma i ol2b v o = 0.5v, r ext =1k ? , v dd = 5v 19.6 20 20.4 ma ? i ol1b output current error between bit (all output on) v o = 0.2v, r ext =6.2k ? , v dd =5v 2 3.5 % ? i ol2b v o = 0.5v, r ext =1k ? , v dd = 5v 1 2 % r sin(up) pull-up resistor 150 300 600 k ? r sin(down) pull-down resistor 100 200 400 k ? i dd(off1) supply current (off) r ext = open out 0 to 15 = off 0.3 ma i dd(off2) r ext = 6.2k ? out 0 to 15 = off 1 i dd(off3) r ext = 1k ? out 0 to 15 = off 3 i dd(on1) supply current (on) r ext = 6.2k ? out 0 to 15 = on 1 i dd(on2) r ext = 1k ? out 0 to 15 = on 3 symbol parameter test conditions min. typ. max. unit t plh1 propagation delay time, clk-outn , /le = h, /oe = l v dd = 3 v v ih = v dd v il = gnd c l = 13pf i o = 40ma v l = 3 v r ext = 470 ? r l = 65 ? 250 280 ns t plh2 propagation delay time, /le -outn , /oe = l 220 250 ns t plh3 propagation delay time, /oe -outn , /le = h 200 250 ns t plh propagation delay time, clk-sdo 25 50 ns t phl1 propagation delay time, clk-outn , /le = h, /oe = l 25 50 ns t phl2 propagation delay time, /le -outn , /oe = l 25 50 ns t phl3 propagation delay time, /oe -outn , /le = h 50 70 ns t phl propagation delay time, clk-sdo 25 50 ns t on output rise time 10 ~ 90% of voltage waveform 260 400 ns t off output fall time 90 ~ 10% of voltage waveform 50 80 ns
STP16CP596 5/18 equivalent circuit of inputs and outputs figure 2: /oe terminal figure 3: /le terminal figure 4: clk, sdi terminal
STP16CP596 6/18 figure 5: sdo terminal figure 6: block diagram
STP16CP596 7/18 table 9: truth table note 1: out0 to out15 = on when dn = h; out0 to out15 = off when dn = l. figure 7: timing diagram note: the latches circuit holds data when the le terminal is low. when le terminal is at high level, latch circuit doesn?t hold the data it passes from the input to the output. when oe terminal is at low level, output terminals out0 to out15 respond to the data, either on or off. when oe terminal is at high level, it switches off all the data on the output terminal. clock /le /oe serial-in out0 .................. out7 .................. out15 sdo h l dn dn ..... dn - 7 ..... dn -15 dn - 15 l l dn + 1 no change dn - 14 h l dn + 2 dn - 2 ..... dn - 5 ..... dn -13 dn - 13 x l dn + 3 dn - 2 ..... dn - 5 ..... dn -13 dn - 13 xldn + 3 off dn - 13
STP16CP596 8/18 figure 8: clock, serial-in, serial-out figure 9: clock, serial-in, latch, enable, outputs
STP16CP596 9/18 figure 10: outputs test circuit figure 11: dc characteristic figure 12: ac characteristic
STP16CP596 10/18 figure 13: output current-r ext resistor figure 14: power dissipation vs temperature package figure 15: output current vs dropout voltage figure 16: output current vs ? i ol (%)
STP16CP596 11/18 dim. mm. inch min. typ max. min. typ. max. a 4.32 0.170 a1 0.38 0.015 a2 3.3 0.130 b 0.41 0.46 0.51 0.016 0.018 0.020 b1 1.40 1.52 1.65 0.055 0.060 0.065 c 0.20 0.25 0.30 0.008 0.010 0.012 d 31.62 31.75 31.88 1.245 1.250 1.255 e 7.62 8.26 0.300 0.325 e1 6.35 6.60 6.86 0.250 0.260 0.270 e 2.54 0.100 e1 7.62 0.300 l 3.18 3.43 0.125 0.135 m 0? 15? 0? 15? plastic dip-24 (0.25) mechanical data 0034965/d stand-off a1 b e b1 d 13 12 24 1 la e1 a2 c e1 gage plane .015 0,38 m e
STP16CP596 12/18 dim. mm. inch min. typ max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.598 0.614 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k0 8 0 8 ddd 0.100 0.004 so-24 mechanical data 0070769c
STP16CP596 13/18 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.15 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 7.7 7.8 7.9 0.303 0.307 0.311 d1 2.7 0.106 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.5 0.169 0.173 0.177 e2 1.5 0.059 e 0.65 0.0256 k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop24 exposed pad mechanical data 7100778c
STP16CP596 14/18 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc h 6.25 6.5 0.246 0.256 k0 8 0 8 l 0.50 0.70 0.020 0.028 tssop24 mechanical data 7047476b c h b a2 a e d 1 pin 1 identification a1 l k e
STP16CP596 15/18 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 10.8 11.0 0.425 0.433 bo 15.7 15.9 0.618 0.626 ko 2.9 3.1 0.114 0.122 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel so-24 mechanical data
STP16CP596 16/18 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.8 7 0.268 0.276 bo 8.2 8.4 0.323 0.331 ko 1.7 1.9 0.067 0.075 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop24 mechanical data
STP16CP596 17/18 table 10: revision history date revision description of changes 08-apr-2005 1 first release. 02-may-2005 2 typing error on the description features. 25-jul-2005 3 add note on fig. 1 and table 5.
STP16CP596 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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