1 ? fn6127.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil, inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL23711 volatile digitally controll ed potentiometer (xdcp?) terminal voltage 3v or 5v, 128 taps i 2 c serial interface the intersil ISL23711 is a digi tally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, and a control section. the wiper position is controlled by an i 2 c interface. the potentiometer is implemen ted by a resistor array composed of 127 resistive elements and a wiper switching network. the wiper terminal can be connected to either end of the resistor array or at any one of the tap positions in between, providing 128 steps of resolution between r l and r h . the ?position? of the wiper is determined by the value assigned to the volatile wiper register (wr). the wr can be directly written to and read from using standard i 2 c interface protocol. the device is available in either a 10k ? or 50k ? version. the device can be used as a th ree-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: ? industrial and automotive control ? parameter and bias adjustments ? amplifier bias and control features ?i 2 c serial interface with hardwire slave address allows up to four devices ? dcp terminal voltage, from v- to v cc ? 127 resistive elements - typical r total tempco 50ppm/ c - typical ratiometric tempco 4ppm/ c - end to end resistance range 20% - wiper resistance = 70 ? typ at v cc = 3.3v ? low power cmos - standby current, 500na max - active current, 200 a max -v cc = 2.7v to 5.5v - v- = -2.7v to -5.5v ?r total values = 10k ?, 50k ? ? volatile wiper storage ? package -10 ld msop ? pb-free plus anneal available (rohs compliant) pinout ISL23711 (10 ld msop) top view ordering information part number (brand) resistance option ( ? ) temp range (c) package pkg. dwg. # ISL23711wiu10z (aoe) (notes 1, 2) 10k -40 to +85 10 ld msop (pb-free) m10.118 ISL23711uiu10z (aod) (notes 1, 2) 50k -40 to +85 10 ld msop (pb-free) m10.118 notes: 1. add ?-t? suffix for tape and reel. 2. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak refl ow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. gnd scl sda v- 1 2 3 4 10 9 8 7 r h r w a0 v cc 5 r l 6 a1 data sheet august 16, 2005
2 fn6127.0 august 16, 2005 block diagram 7-bit wiper register recall control circuitry one of 128 decoder resistor array r h sda scl transfer gates r l r w interface v- r h r w r l simple block diagram detailed block diagram 0 1 2 124 125 126 127 v cc (volatile) slave address decode a1 a0 sda scl a1 a0 gnd and control pin descriptions pin number symbol description 1 sda data i/o for i 2 c serial interface. it has an open drain output and may be wire ored with other open drain active low outputs. 2 v- negative supply voltage for the potentiometer wiper control. 3 gnd ground. should be connected to a digital ground 4 a1 a1 and a0 are address select pins used to set the slave address for the i 2 c serial interface. 5 a0 a1 and a0 are address select pins used to set the slave address for the i 2 c serial interface. 6r h a fixed terminal for one end of the potentiometer resistor. 7r w the wiper terminal which is equivalent to the movable terminal of a potentiometer. 8r l a fixed terminal for one end of the potentiometer resistor. 9v cc positive logic supply voltage. 10 scl clock input for the i 2 c serial interface. ISL23711
3 fn6127.0 august 16, 2005 absolute maximum rati ngs thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on sda, scl, a0, and a1 with respect to gnd . . . . . . . . . . . . . . . . . . . . . -0.3 to v cc +0.3v voltage on v- (referenced to gnd) . . . . . . . . . . . . . . . . . . . . . . . -6v ? v = |v (rh) -v (rl) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v r h , r l , r w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- to v cc esd rating (mil-std-883, method 3015.7 . . . . . . . . . . . . . . .>2kv thermal resistance (typical, note 3) ja (c/w) msop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 recommended operating conditions temperature range (industrial) . . . . . . . . . . . . . . . . .-40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7v to -5.5v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. note: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. analog specifications over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ (note 1) max unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % v rh, v rl r h , r l terminal voltage v- v cc v r w wiper resistance v- = -5.5v; v cc = +5.5v wiper current = (v cc -v-)/r total 70 200 ? c h /c l /c w potentiometer capacitance (note 13) 10/10/25 pf i lkgdcp leakage on r h , r l , r w pins voltage at pins; v- to v cc -1 0.1 1 a voltage divider mode (v- @ r l ; v cc @ r h ; voltage at r w = v rw unloaded) inl (note 6) integral non-linearity -1 1 lsb (note 2) dnl (note 5) differential non-linearity w, u options -0.5 0.5 lsb (note 2) zserror (note 3) zero-scale error w option 0 1 4 lsb (note 2) u option 0 0.5 2 fserror (note 4) full-scale error w option -4 -1 0 lsb (note 2) u option -2 -0.5 0 tc v (notes 7, 13) ratiometric temperature coefficient dcp register set from 16 to 120d, t = -40c to +85c 4 ppm/c resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 11) integral non-linearity dcp register set between 20 hex and 7f hex. monotonic over all tap positions -1 1 mi (note 8) rdnl (note 10) differential non-linearity -0.5 0.5 mi (note 8) roffset (note 9) offset dcp register set to 00 hex, w option 0 2 5 mi (note 8) dcp register set to 00 hex, u option 0 0.5 2 mi (note 8) tc r (notes 12, 13) resistance temperature coefficient dcp register set from 16 to 127d, t = -40c to +85c 50 ppm/c ISL23711
4 fn6127.0 august 16, 2005 operating specifications over the recommended operating condi tions unless otherwise specified. symbol parameter test conditions min typ (note 1) max unit i cc1 v cc supply current, volatile write/read f scl = 400khz; sda = open; (for i 2 c, active, read and write states only) 200 a i v- v- supply current, volatile write/read f scl = 400khz; sda = open; (for i 2 c, active, read and write states only) -100 -1 a i sb v cc current (standby) v cc = +5.5v, i 2 c interface in standby state 500 na v cc = +3.6v, i 2 c interface in standby state 300 na i v-sb v- current (standby) v- = -5.5v, i 2 c interface in standby state -500 na v- = -2.7v, i 2 c interface in standby state -300 -1 na i lkgdig leakage current, at pins sda, scl, a0, and a1 voltage at pin from gnd to v cc -10 10 a t dcp (note 13) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper change 1s vpor power-on recall for v cc 2.5 v serial interface specs v il a0, a1, sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a0, a1, sda, and scl input buffer high voltage 0.7*v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05* v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin (note 14) a0, a1, sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition setup time from sda rising edge to scl falling edge. both crossing 70% of v cc 600 ns ISL23711
5 fn6127.0 august 16, 2005 sda vs scl timing a0, a1 pin timing t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r (note 14) sda, scl, a0, a1 rise time from 30% to 70% of v cc 20 + 0.1 * cb 250 ns t f (note 14) sda, scl, a0, a1 fall time from 70% to 30% of v cc 20 + 0.1 * cb 250 ns cb (note 14) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 14) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2~2.5k ? for cb = 40pf, max is about 15~20k ? 1k ? t su:a a0, a1 setup time before start condition 600 ns t hd:a a0, a1 hold time after stop condition 600 ns operating specifications over the recommended operating condi tions unless otherwise specified. (continued) symbol parameter test conditions min typ (note 1) max unit t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:a scl sda in a0, a1 t su:a clk 1 start stop ISL23711
6 fn6127.0 august 16, 2005 notes: 1. typical values are for t a = 25c and 5v supply voltage. 2. lsb: [v(rw) 127 ? v(rw) 0 ] / 127. v(rw) 127 and v(rw) 0 are v(rw) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 3. zs error = (v(rw) 0 ? v-) / lsb. 4. fs error = [v(rw) 127 ? v cc ] / lsb. 5. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 6. inl = v(rw) i ? (i ? lsb ? v(rw) 0 ) for i = 1 to 127. 7. for i = 16 to 120 decimal, max( ) is the maximum value of the wi per voltage and min ( ) is the minimum value of the wiper volta ge over the temperature range. 8. mi = | r 127 ? r 0 | / 127. r 127 and r 0 are the measured resistances for the dcp regi ster set to 7f hex and 00 hex respectively. 9. roffset = r 0 / mi, when measuring between r w and r l . roffset = r 127 / mi, when measuring between r w and r h . 10. rdnl = (r i ? r i-1 ) / mi, for i = 16 to 127. 11. rinl = [r i ? (mi ? i) ? r 0 ] / mi, for i = 16 to 127. 12. for i = 16 to 127, max( ) is the maximum value of the resistanc e and min ( ) is the minimum value of the resistance over the te mperature range. 13. this parameter is not 100% tested. 14. these are i 2 c specific parameters and are not directly tested, however they are used during device testing to validate device specification . test circuit equivalent circuit pin descriptions potentiometer pins r h and r l the high (r h ) and low (r l ) terminals of the ISL23711 are equivalent to the fixed terminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the terminal in relation to wiper movement direction selected by the i 2 c serial input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the control inputs. bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for the i 2 c interface. it receives devi ce address, operation code, wiper register address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. sda requires an external pull-up resistor, since it?s an open drain output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. device address (a1-a0) the address inputs are used to set the least significant 2 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream must be made with the address input pins in order to initiate communication with the ISL23711. a maximum of 4 ISL23711 devices may occupy the i 2 c serial bus. principles of operation the ISL23711 is an integrated circuit incorporating one dcp with it?s associated register, and an i 2 c serial interface providing direct communication between a host and the potentiometer and memory. the resistor array is comprised tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 125c ---------------- - = tc r max ri () min ri () ? [] max ri () min ri () + [] 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - = force current test point r w c h c l r w r total c w r h r l ISL23711
7 fn6127.0 august 16, 2005 of 127 individual resistors connec ted in series. at either end of the array and between each resistor is an electronic switch that transfers the potent ial at that point to the wiper. the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. that is, the counte r does not wrap around when clocked to either extreme. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of the dcp are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l pins). the r w pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal is controlled by a 7-bi t volatile wiper register (wr). when the wr contains all zeroes (00h), the wiper terminal (r w ) is closest to its ?low? terminal (r l ). when the wr contains all ones (7fh), the wiper terminal (r w ) is closest to its ?high? terminal (r h ). as the value of the wr increases from all zeroes (0 decimal) to all ones (127 decimal), the wiper moves monotonically from the position closest to r l to the position closest to r h . at the same time, the resistance between r w and r l increases monotonically, while the resistance between r h and r w decreases monotonically. while the ISL23711 is being powered up, the wr is reset to 20h (64 decimal), which locates the r w at the center between r l and r h . the wr can be read or written directly using the i 2 c serial interface as described in the following sections. memory description ? a read operation to address 0 outputs the value of the volatile wr. ? a write operation to address 0 only writes to the volatile wr. i 2 c serial interface the ISL23711 supports a bidirectional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operatio ns. therefore, the ISL23711 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 1). on power-up of the ISL23711 the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transiti on of sda while scl is high. the ISL23711 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 1). all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 1). a stop condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 2). the ISL23711 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the ISL23711 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation a valid identification byte contains 01010 as the five msbs, and the following two bits matching the logic values present at pins a1, and a0. the lsb is in the read/write bit. its value is ?1? for a read operation, and ?0? for a write operation. (see table 1.) table 1. identification byte format write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL23711 responds with an ack. read operation a read operation is initiated by a master using the following sequence: a start, the identification byte (slave address) with the r/w bit set to ?1?. at the moment of the first acknowledge by the ISL23711 (slave device), the master- transmitter becomes a master receiver and receives the data byte from the slave-transmitter .the master receives the data byte and issues a non-acknowledge (sda is high), then a stop to terminate the read operation. since the isl 23711 has just one wr, it will transmit only one byte (see figure 4). 01010a1a0r/w (msb) (lsb) logic values at pins a1, and a0 respectively ISL23711
8 fn6127.0 august 16, 2005 figure 1. valid data changes, start, and stop conditions figure 2. acknowledge response from receiver figure 3. byte write sequence figure 4. read sequence sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the ISL23711 a c k 0 0 0 11 a c k write signal at sda 0000 a0 a1 000 0000 signals from the master signals from the slave signal at sda s t o p 0 1 0 11 identification byte with r/w =1 a c k s t a r t data byte read by master 0 a1 a0 ISL23711
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6127.0 august 16, 2005 ISL23711 mini small outline plastic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. dimension ?b? does not inclu de dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02
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