application note 1 of 4 www.xicor.com july, 2001 vref support bus description output vddq vtt system industry driver components examples gtl+ gunning open drain 5v or 3.3v 1.5v 10% 1.0v 2% processor: transceiver (v ddq ) pc chipsets: bus plus gtlp 16xxx buffers: fairchild, texas instr. sstl_2 series stub symmetric 2.5v 10% 0.5x (v ddq ) 2.5v sstl sdram: terminated drive, series 3% hitachi logic for 2v resistance fujitsu, nec, micro, mitsubishi rambus rambus open drain none 2.5v 2.0v ndram, signaling specified rambus, logic intel, toshiba lv-ttl low voltage symmetric 3.3v 10% v ddq /2 3.3v processors or ttl logic or drive backplanes: pecl or lv-ttl 3.3v vme sdram, edo ram an 146 improving system performance through intelligent power management by tony ochoa as the processor speeds have increased in the last few years, so has the speed or bandwidth of the data busses between the microprocessors, memory, and the system controller chips. several bus standards and there respec- tive signaling characteristics are now in use: gtl (gunning transceiver logic) is used primarily for host cpu and the pci/memory host controller; sstl (series stub terminated logic) is used for host controller to main memory (ddr sdram) or rambus (re?ctive wave switching) is used as an alternative for host controller to main memory (rdram). each of these bus schemes require a particular electrical bus termination scheme and a bus termination voltage. in addition, along the termination voltages of these buses (vtt), additional voltage references are sometimes needed to support the bus i/o operations. these voltage references are designated as vref and vddq. see table 1 for common voltage requirements for each of the buses. in applications where data throughput is foremost and speed is critical, regulating the termination voltages and providing accurate voltage references can be very table 1: typical bus termination voltage & reference voltage
2 of 4 an 146 application note www.xicor.com july, 2001 vmon 2 vmon 1 pgood logic csr & bus i/o fault detection register eeprom sm bus, i 2 c x4023x v ref - good, v tt - good sda scl v reg-in2 v ref out2 v ref out 1 v ref-in1 168/184/208-pin dimm connectors and sdram/sgram modules termination resistors data line, clock lines, address lines, control lines termination resistors vreg v ref pc chip set northbridge vtt serial id# option 2 windows - labview i/f c option1 v ref - good (v1fail) v tt - good (v2fail) gd i/o scl master sda important. embedded applications and multiprocessor applications with shared memory architectures (large memory arrays) commonly will design for higher perfor- mance specs by margining the vtt and vref of the bus. for example, figure 1 shows a typical ddr sdram main memory termination scheme (double parallel stub termination). the sstl standard specs by jedec list the vtt as 1.25v (vref of 2.5v); however, system designers are ?ding that the host controller chips (or graphics chips) and the memory chips can figure 1: x4023x used as high speed bus voltage monitor and vref output control
an 146 application note 3 of 4 www.xicor.com july, 2001 actually vary in performance based upon the vref and vtt voltages. for example the design in figure 1 could operate with high data throughput at a vtt of 1.35v (vref of 2.7v). the same concept can be applied to gtl or rambus bus schemes as well. xicor provides a solution using the x4023x that can monitor and adjust the vtt and vref voltages of the bus via either system control or through manufacturing calibration using a windows-labview interface. the x4023x contains two voltage monitors, one to two digi- tally controlled potentiometers, a fault detection register, eeprom, and a two-wire bus interface. figure 1 depicts the use of the x4023x in a ddr sdram application. the two voltage monitors can be programmed to track the vref and vtt signals. the voltage monitors issue an output signal when the vtt and vref signals are valid (i.e. vref_good and vtt_good) and also update the fault detection register. this allows the system to also query the x4023x for remote sensing of the condition of the vtt and vref signals via the two- wire bus by reading the fault detection register status bits. the x4023x contains one to two (optional) digitally- controlled potentiometers (xdcp ) that are used in a voltage-divider con?uration to set and control the vtt and vref levels (see figure 1). each xdcp acts as a voltage dac that is programmed via the two-wire inter- face. the x4023x contains one of three possible xdcps that can provide various voltage resolution and accuracy. for example, the 256-tap xdcp can provide 0.4% reso- lution. as a practical example, vtt can be selected from 2.5v to 0v with 0.4% resolution (256 levels). in addition, since the xdcp is used in a voltage divider con?uration or a ?atiometric?mode the voltage varia- tion vs. temperature is typically 20 ppm per degree celsius. furthermore if higher accuracy is needed the potentiometer voltages (vh and vl) can be set such that higher resolutions may be achieved by setting vl to a voltage above ground (see figure 1 vref_in2). note that once the wiper position of the xdcp has been optimized the position of the wiper is stored in non- volatile memory and is recalled during power up ?this feature allows ?et-and-forget?applications and provides automation in manufacturing for calibration. system control vs. manufacturing tuning the x4023x can be used to make adjustments in a closed-loop system or in an open-loop system. for closed-loop applications a simple microcontroller can be used to monitor the vref and vtt status signals of the x4023x and to make real-time adjustments of the vtt or vref signals via the two-wire bus (see figure 1). for open-loop applications, where the vtt and vref are set in manufacturing or calibration modes, xicor offers labview-window drivers for the x4023x. this soft- ware tool requires only a pc and the free software from xicor (www.xicor.com) to program the x4023x. customers can use the parallel port, serial port, ieee- 488 or any customer interface to access the dut (device under test). the labview drivers emulate the 2-wire commands set to program the x4023x while windows 98 / nt / 2000 provides the gui interface to program the device (see figure 2).
4 of 4 an 146 application note www.xicor.com july, 2001 in summary, the x4023x provides excellent bus voltage monitoring and vtt and vref output voltage adjustment to improve high speed data throughput and signal integrity. it also provides system level monitoring of the vtt and vref signals. the x4023x is easy to use via system control for ?et and forget?applications. the x4023x is ideal for applications with embedded controller designs, fault tolerant systems, large memory array or multiprocessor systems. figure 2: using labview-windows interface to program vtt and vref
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