features atmel?s prochip designer v4.0 with the mentor graphics ? software update seam- lessly integrates the following software components into one integrated development environment (ide): precision ? rtl synthesis - vhdl and verilog ? synthesis supports from mentor graphics modelsim ? - vhdl and verilog simulation supports from mentor graphics peakfpga ? - vhdl synthesis and simu lation support from altium ? protel ? 99se - schematic and cupl ? design entry, synthesi s and simulation supports from altium fit15xx - fitters for the atf15xx cplds from atmel hdl planner - vhdl and verilog design en try and text editing support from atmel atmel isp - jtag in-system progra mming (isp) support from atmel description atmel?s prochip designer is a fully featured eda software suite incorporating state-of- the-art synthesis and simulation tools from mentor graphics and altium with atmel?s user-friendly interface/design navigator and powerful fitter technologies. the combi- nation of these tools will enable cpld designers to achieve the highest possible logic utilization from the atme l atf15xxas/asl/asv/asvl/be series cplds (complex programmable logic device s) with logic doubling ? features. through all of the software components available within the prochip designer soft- ware suite, the following features are supported: design entry & synthesis ? vhdl ? verilog ? cupl ?schematic simulation ? vhdl functional and timing simulation ? verilog functional and timing simulation ? cupl functional simulation device ? atf15xxbe - 1.8v ultra-low-power cpld ? atf15xxas/asl - 5.0v standard and low-power cpld ? atf15xxasv/asvl - 3.3v standard and low-power cpld programming ?jtag isp software suite components the software components within the prochip designer software suite are divided into two groups. these two software groups, thei r contents, license terms and ordering code are described in table 1 in detail. prochip designer ? software suite overview 3628a?pld?03/06
2 3628a?pld?03/06 prochip designer software suite overview note: atmel?s software tools are supported on microsoft ? windows ? operating systems. the details of the operating system supports for other vendors? tools can be obtained from the third-party tool vendors? websites or documentation. for the prochip designer v4.0 evaluation edition, it comes with the 30-day trial version of altium peakfpga and protel 99se. a license is not needed to install the trial version software. however, they can be installed onto a pc only once. when the trial period expires, users can purchase the licensed edition of prochip desi gner v4.0 from atmel using the ordering code [atds1500pc]. upon the purchase, a prochip designer v4.0 software cd along with the 16- digit access code (permanent license) will be ma iled. users can then follow the installation instructions to uninstall the evaluation edition software and install the licensed edition software. the prochip designer v4.0 evaluation edition is available on the prochip designer v4.0 soft- ware cd and the atmel website at www.atmel.com/dyn/products/t ools_card.asp?tool_id=2756 . after successfully installing prochip designer v4.0 (evaluation or licensed edition), the mentor graphics software update should be installed by following the installation instructions provided with the update. this update adds the support for the atf15xxbe, mentor graphics precision and modelsim, latest fitters, and latest atmel cpld isp software into the prochip designer v4.0 software suite. to use precision or modelsim, a flexlm ? license file from atmel is required. a 6-month evalu- ation license can be obtained from atmel by registering online at www.atmel.com/products/pld /forms/reg_license.asp. atmel also offers annual (1-year) licenses for precision/modelsim, which can be purchased using the ordering code [ATDS15XXKSW1]. upon the purchase, a prochip designer v4.0 soft ware cd along with a serial number will be mailed. users can then request for the annual license from atmel online at the url shown above with the serial number provided. table 1. prochip designer software suite contents and license terms software content license term prochip designer v4.0 evaluation edition prochip designer v4.0 free 30-day trial version of altium peakfpga free 30-day trial period 30-day trial version of altium protel99se licensed edition prochip designer v4.0 free licensed version of altium peakfpga permanent license [p/n: atds1500pc] licensed version of altium protel99se mentor graphics software update prochip 4.0 software patch free mgc precision rtl synthesis free 6-month evaluation license 1-year license [p/n: ATDS15XXKSW1] mgc modelsim license configuration utility free atmel isp free
3 3628a?pld?03/06 prochip designer software suite overview note: the license terms for altium peakfpga/pro tel 99se and mentor graphics precision/modelsim are independent of each other. ther efore, even after the 30-day trial period for the altum tools has expired, precision and modelsim can continue to be used until the license period for them expires. similarly, protel 99se and peakfpga can continue to be used even after the license period for precision/modelsim has expired. software design flow the prochip designer v4.0 ide is shown in figure 1 . the design flow chart on the right pro- vides push-button access to all the stages of a design cycle. description of the features for each design flow stage is described in table 2 . figure 1. prochip designer v4.0 ide men u bar shortc u t bar transcript project tree design flo w
4 3628a?pld?03/06 prochip designer software suite overview for details on how to use prochip, refer to the prochip designer help file, tutorials, and online resources. these resources are available under the prochip help menu. technical support submit questions online at: http://www.atmel.com/dyn/products/support.asp faq: http://www.atmel.com/dyn/products/tech_support.asp?faq=y table 2. description of design flow stages design flow stage description source manager to specify the new or existing design file(s). launches the appropriate design entry tool for editing based on the selected tool-flow. logic synthesis to synthesize the design file(s ) to generate the appropriate netlist file. device fitter to fit the netlist into the target device with the user selected fitter options. testbench manager to specify the new or existing testbe nch file(s). launches the appropriate testbench entry tool for editing based on the selected tool-flow. functional simulation to perform functional simulation on the design file(s). timing simulation to perform timing simulation on the output netlist generated by the fitter after fitting. atmel isp to program the target atf15xx cpld through jtag-isp.
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