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MCM63P636 1 motorola fast sram advance information 64k x 36 bit pipelined burstram synchronous fast static ram the MCM63P636 is a 2mbit synchronous fast static ram designed to provide burstable, high performance, secondary cache for advanced microprocessors. it is organized as 64k words of 36 bits each. this device integrates input regis- ters, an output register, a 2bit address counter, and a high speed sram onto a single monolithic circuit for reduced parts count in cache data ram applica- tions. synchronous design allows for precise cycle control with the use of an ex- ternal clock (k) and external strobe clock (sk). addresses (sa), data inputs (dqx), and all control signals are clock (k) controlled through positiveedgetriggered noninverting registers. data strobes strba, strba , strbb, and strbb are strobe clock (sk) controlled through positiveedgetriggered noninverting registers. strobe clock, 180 degrees out of phase with clock (k), is only used with the data strobes such that they are centered with data output on read cycles. burst sequences are initiated with ads input pin, and subsequent burst addresses are generated internally by MCM63P636. write cycles are internally selftimed and are initiated with address and control logic by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. special logic enables the memory to accept data on the rising edge of clock (k) a cycle after address and control signals. for read cycles, the srams output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the second rising edge of clock (k) for a read latency of three cycles. data strobes rise and fall with sram output to help external devices receiving the data to latch the data. the MCM63P636 operates from a 3.3 v core power supply, a 2.0 v input power supply, and a 2.0 v i/o power supply. these power supplies are designed so that power sequencing is not required. ? MCM63P636250 = 3.9 ns access/4 ns cycle (250 mhz) MCM63P636225 = 4.3 ns access/4.4 ns cycle (225 mhz) MCM63P636200 = 4.9 ns access/5 ns cycle (200 mhz) ? 3.3 v 200 mv v dd supply, 2.0 v v ddi and v ddq supply ? internally selftimed late write cycle ? threecycle singleread latency ? strobe clock input and data strobe output pins ? onchip output enable control ? onchip burst advance control ? fourtick burst ? poweron reset pin ? low power stop clock operation ? boundary scan (pbga only) ? jedec standard 153pin pbga and 100pin tqfp packages this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by MCM63P636/d semiconductor technical data MCM63P636 zp package pbga case 110701 tq package tqfp case 983a01 3/16/98 ? motorola, inc. 1998
MCM63P636 2 motorola fast sram pbga pin assignment 153bump pbga top view 6 5 4 3 2 17 b c ads g a d e f h j v ss k v ss v ss nc sa sa sa v ddq sa se2 nc v ss w reset dqa sa sa0 sa sa v ss dqb v ddq sa nc v dd v dd v dd v ddi v ss strbb v ddi v dd strbb dqb sa1 sa tck sa tdi v ddq dqa dqa dqa dqa sa v ss v ss sa v ss v ss v dd v ddq v ss dqa dqa v ddi v ss v dd v ss v ss v dd v ddq v ss dqa dqa strba v dd nc dqa v dd v ss nu/v ss v ss v ss v ddq v ss dqa strba v dd v dd v dd dqa v ddi v dd v ss v ss v dd v ddq v ss dqa dqa v dd dqa v dd nu/v ss v ss dqa dqa sa se3 se1 k l m n p r t u v ss sa nu/v dd v ss v ddq v ss 89 dqb dqb v ss dqb v ddq tdo dqb v ss v ss dqb v ss dqb dqb v ss dqb dqb dqb v ddq dqb dqb v ddq dqb dqb dqb v ss dqb v ss v ss v ddq v ddq v ddq v ddq dqa v ss v ddq v dd sk v ss v dd v ddq v ss v ddq tms trst
MCM63P636 3 motorola fast sram tqfp pin assignment 71 72 dqa dqb 69 70 66 67 68 64 65 61 62 63 37 38 34 35 36 42 43 39 40 41 45 46 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 dqb dqb v ss dqb dqb dqb dqb v ss dqb dqb v ddq v ss v ss dqa dqa dqa dqa dqa dqa dqa strba sa sa se1 k nu/v nc ads reset sa0 sa sa sa sa nc v nc ddi v ss nc sa1 v dd v dd strbb dqb v ss dqb dqb dqb dqb v ss dqb dqb v ss dqb dqb dqa v dd v ss v ss dqa dqa dqa dqa dqa 73 dqa 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 sa sa v se2 sk se3 v ss v dd w strbb strba v ss dqa dqa dqa sa nc sa sa sa sa sa v ddq v ddq v ddq v ddq v ddq v ddq v ddq ddi v ddi v ddi dd nu/v ss nu/v ss
MCM63P636 4 motorola fast sram pbga pin descriptions pin locations symbol type description 5d ads input synchronous address status: active low, used to initiate read or write state machines latch in external addresses, or deselect chip. (a) 1b, 2b, 1d, 2d, 3d, 1f, 2f, 1h, 2h, 1k, 2k, 1m, 2m, 1p, 2p, 3p, 1t, 2t (b) 8b, 9b, 7d, 8d, 9d, 8f, 9f, 8h, 9h, 8k, 9k, 8m, 9m, 7p, 8p, 9p, 8t, 9t dqx i/o synchronous data i/o: axo refers to the word being read or written (i/os a and b). 5f k input clock: this signal registers the address, data in, and all control signals. 6c reset input asynchronous poweron reset: active low at power up, resets internal state machines. 3a, 7a, 3b, 7b, 5m, 5n, 4p, 5p, 6p, 4r, 6r, 3t, 4t, 6t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 5r, 5t sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 4a se1 input synchronous chip enable: active low to enable chip. 5a se2 input synchronous chip enable: active high to enable chip. 4b se3 input synchronous chip enable: active low to enable chip. 5g sk input data strobe clock: 180 degrees outofphase with k. used only with data strobes. 3k strba output data strobe: used in reference to dqa i/os. 3h strba output data strobe: used in reference to dqa i/os. 7k strbb output data strobe: used in reference to dqb i/os. 7h strbb output data strobe: used in reference to dqb i/os. 5u tck input boundary scan pin, test clock: if boundary scan is not used, tck must be tied to v dd or v ss . 3u tdi input boundary scan pin, test data in. 7u tdo output boundary scan pin, test data out. 4u tms input boundary scan pin, test mode select. 6u trst input boundary scan pin, asynchronous test reset. if boundary scan is not used, trst must be tied to v ss . 5c w input synchronous write. 4d, 6d, 3e, 7e, 4f, 6f, 3g, 7g, 4h, 6h, 4k, 6k, 3l, 7l, 4m, 6m, 3n, 7n v dd supply core power supply. 3f, 7f, 3m, 7m v ddi supply input power supply. 2a, 8a, 2c, 8c, 2e, 8e, 2g, 8g, 2j, 8j, 2l, 8l, 2n, 8n, 2r, 8r, 2u, 8u v ddq supply i/o power supply. 1a, 9a, 1c, 3c, 7c, 9c, 1e, 4e, 5e, 6e, 9e, 1g, 4g, 6g, 9g, 5h, 1j, 3j, 4j, 6j, 7j, 9j, 1l, 4l, 5l, 6l, 9l, 1n, 4n, 6n, 9n, 1r, 3r, 7r, 9r, 1u, 9u v ss supply ground. 6a, 5b, 5k, 7t nc e no connection: there is no connection to the chip. 6b nu/v dd e not usable: there is an internal connection to the chip. this pin may be left unconnected or tied to v dd . 4c, 5j nu/v ss e not usable: there is an internal connection to the chip. this pin may be left unconnected or tied to v ss .
MCM63P636 5 motorola fast sram tqfp pin descriptions pin locations symbol type description 85 ads input synchronous address status: active low, used to initiate read or write state machines latch in external addresses, or deselect chip. (a) 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 (b) 51, 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 80 dqx i/o synchronous data i/o: axo refers to the word being read or written (i/os a and b). 89 k input clock: this signal registers the address, data in, and all control signals. 84 reset input asynchronous poweron reset: active low at power up, resets internal state machines. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 98 se1 input synchronous chip enable: active low to enable chip. 97 se2 input synchronous chip enable: active high to enable chip. 92 se3 input synchronous chip enable: active low to enable chip. 93 sk input data strobe clock: 180 degrees outofphase with k. used only with data strobes. 16 strba output data strobe: used in reference to dqa i/os. 14 strba output data strobe: used in reference to dqa i/os. 64 strbb output data strobe: used in reference to dqb i/os. 66 strbb output data strobe: used in reference to dqb i/os. 88 w input synchronous write. 15, 41, 65, 91 v dd supply core power supply. 38, 43, 87, 94 v ddi supply input power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 31, 39, 42, 50, 86 nc e no connection: there is no connection to the chip. 83 nu/v dd e not usable: there is an internal connection to the chip. this pin may be left unconnected or tied to v dd . 95, 96 nu/v ss e not usable: there is an internal connection to the chip. this pin may be left unconnected or tied to v ss .
MCM63P636 6 motorola fast sram truth table (see notes 1 and 2) k e ads w next cycle (n) input command code dq (n + 1) dq (n+2) l h false 0 x deselect d highz e l h true 0 0 load address, begin write bw data in e l h true 0 1 load address, begin read br e data out l h x 1 0 continue write cw data in e l h x 1 1 continue read mask write cr mw e highz data out e notes: 1. x = don't care, 1 = logic high, 0 = logic low. 2. e = true if se1 and se3 = 0, and se2 = 1. burst address table 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 deselect new read* figure 1. functional state diagram burst read 1* burst read 2* burst read 3* new write* burst write 1* burst write 2* burst write 3* masked write 1* masked write 2* masked write 3* d, cw, cr mw br bw cr cr cr br bw bw d, cw, mw cw cw cw br mw mw mw mw mw br bw d, cw, mw d, cw, mw * command code inputs not shown from this state are not valid.
MCM63P636 7 motorola fast sram highz 4 intermediate highz 1, 4 figure 2. data i/o state diagram d, cw, cr mw br cr cr cr d, cw, cr cw, mw mw cw, mw notes: 1. command code inputs not shown from this state are not valid. 2. strba and strbb transition from logic 1 to 0. strba and strbb transition from logic 0 to 1. 3. strba and strbb transition from logic 0 to 1. strba and strbb transition from logic 1 to 0. 4. data strobes are driven to highz. intermediate highz 1, 4 dataout/ q(1)valid 1, 2 dataout/ q(2)valid 1, 3 dataout/ q(3)valid 1, 2 dataout/ q(4)valid 1, 3 dataout/ q(4)valid 1, 3 datain (1)/ highz 1, 4 cw cw cw datain (2)/ highz 1, 4 datain (3)/ highz 1, 4 datain (4)/ highz 1, 4 mask (2)/ highz 1, 4 mw mw mw mask (3)/ highz 1, 4 mask (4)/ highz 1, 4 highz 1, 4 mw mw mw highz 1, 4 br cr br cr bw cr
MCM63P636 8 motorola fast sram absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd v ss 0.5 to + 4.0 v i/o supply voltage v ddq v ss 0.5 to 2.5 v 2, 3 input supply voltage v ddi v ss 0.5 to 2.5 v 2, 3 voltage relative to v ss for any pin except v dd v in v ss 0.5 to v ddi + 0.5 v 2, 4 input voltage (threestate i/o) v it v ss 0.5 to v ddq + 0.5 v 2, 4 output current (per i/o) i out 20 ma package power dissipation p d 2.75 w 5 temperature under bias t bias 10 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. this is a steadystate dc parameter that is in effect after the power supply has achieved its nominal operating level. power sequencing is not necessary. 3. v ddi = v ddq . 4. max v in and v it are not to exceed max v dd . 5. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics e pbga rating symbol max unit notes junction to ambient (@ 200 lfm) r q ja 25 c/w 1, 2 junction to board (bottom) r q jb 12 c/w 3 junction to case (top) r q jc 10 c/w 4 package thermal characteristics e tqfp rating symbol max unit notes junction to ambient (@ 200 lfm) r q ja 25 c/w 1, 2 junction to board (bottom) r q jb 17 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit.
MCM63P636 9 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v 200 mv, t a = 0 to 70 c, unless otherwise noted) recommended operating conditions and dc characteristics (voltage referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.1 3.3 3.5 v input supply voltage v ddi 1.8 e 2.2 v i/o supply voltage v ddq 1.8 e 2.2 v input low voltage (v ddi = v ddq ) v il 0.5 e 0.35 x v ddi v input high voltage (v ddi = v ddq ) v ih 0.65 x v ddi e v ddi + 0.5 v input leakage current (0 v v in v dd ) i lkg(i) e e 1 m a output leakage current (0 v v in v ddq ) i lkg(o) e e 1 m a output low voltage (i ol = 1 ma) v ol 0.5 e 0.4 v output high voltage (i ol = 1 ma) v oh v ddq 0.4 e v ddq + 0.5 v v ih 20% t khkh v ss v ss 0.5 v figure 3. undershoot voltage v ss 0.25 v supply currents parameter symbol min max unit notes ac supply current (device selected, all outputs open, freq = max, v dd = max) i dda 250 i dda 225 i dda 200 e tbd ma 1, 2, 3, 4 input and i/o supply current desktop (all 40 outputs toggling, freq = max, v ddi = max, v ddq = max, v ddi = v ddq , c dt = 24 pf) i ddq 250 i ddq 225 i ddq 200 e 311 280 249 ma 2, 5 static standby supply current (device deselected, freq = max, v dd = max, ads (v ddi 0.2 v), w static (v ss + 0.2 v) or (v ddi 0.2 v), sa and dqx inputs static (v ss + 0.2 v), outputs disabled) i sb1 250 i sb1 225 i sb1 200 e 63 57 50 ma 1, 2, 4 idle standby supply current (device deselected, freq = 0, v dd = max, ads (v ddi 0.2 v), w static (v ss + 0.2 v) or (v ddi 0.2 v), sa and dqx inputs static (v ss + 0.2 v), outputs disabled) i sb2a e tbd ma 1, 3, 4 idle input standby supply current (device deselected, freq = 0, v dd = max, ads (v ddi 0.2 v), w static (v ss + 0.2 v) or (v ddi 0.2 v), sa and dqx inputs static (v ss + 0.2 v), outputs disabled) i sb2b e tbd ma 1, 3, 5 notes: 1. device is selected and deselected as defined by the truth table. 2. reference ac operating conditions and characteristics for input and timing. 3. data states are all zero. 4. includes supply current for v dd only. 5. includes supply currents for v ddi and v ddq only.
MCM63P636 10 motorola fast sram capacitance and inductance (see notes 1, 2, and 3) pi d i i tqfp pbga pi d i i capacitance (pf) inductance (nh) capacitance (pf) inductance (nh) pin description min max min max min max min max i/o pins 5 7 2 10 5.5 7.5 2.5 4.5 data strobe pins 5 7 2 10 5.5 7.5 2.5 4.5 input pins 3 5 2 10 3.5 5.5 2.5 4 ads pin 5 7 2 10 5.5 7.5 2.5 4.5 k and sk pins 3.5 4.5 2 10 4 5 1.5 3 tck boundary scan pin e e e e e 5 e e boundary scan input pins e e e e e 8 e e tdo boundary scan pin e e e e e 8 e e notes: 1. parameters are periodically sampled rather than 100% tested. 2. capacitance variation part to part on the same pin is 0.25 pf. 3. inductance variation part to part on the same pin is 1 nh. ac operating conditions and characteristics (v dd = 3.3 v 200 mv, unless otherwise noted) ac test conditions parameter value unit input timing reference level v ddq /2 v input pulse levels 0 to 2.0 v input rise/fall time (20 to 80%) 1 v/ns output timing reference level v ddq /2 v die temperature t j 250 t j 225 t j 200 115 115 115 c output r l figure 4. ac output test load z 0 = 50 w 1.0 v figure 5. lumped capacitive load and typical derating curve (tbd)
MCM63P636 11 motorola fast sram read/write cycle timing (see notes 1 and 2) p sbl MCM63P636250 MCM63P636225 MCM63P636200 ui n parameter symbol min max min max min max unit notes clock cycle time t khkh 4 e 4.4 e 5 e ns 3, 4 clock high time t kh 1.06 e 1.24 e 1.46 e ns 4 clock low time t kl 1.06 e 1.24 e 1.46 e ns 4 strobe clock cycle time t skhskh 4 e 4.4 e 5 e ns 3, 4 strobe clock high time t skh 1.06 e 1.24 e 1.46 e ns 4 strobe clock low time t skl 1.06 e 1.24 e 1.46 e ns 4 rising k to rising sk t khskh 1.6 2.4 1.8 2.6 2.1 2.9 3 clock access time t khqv e 3.9 e 4.3 e 4.9 ns 3 clock to output lowz t khqx 0 e 0 e 0 e ns 5, 6 clock to output highz t khqz e 3.9 e 4.3 e 4.9 ns 5, 6 strobe clock access time t skhstv e 3.9 e 4.3 e 4.9 ns 3 setup times: address ads chip enable data in data out write t avkh t svkh t evkh t dvkh t qvstv t wvkh 0.5 1.2 0.5 1.2 1 1.2 e 0.5 1.5 0.5 1.5 1.1 1.5 e 0.5 1.5 0.5 1.5 1.15 1.5 e ns 3 hold times: address ads chip enable data in data out write t khax t khsx t khex t khdx t stvqx t khwx 4 0.5 4 0.5 1 0.5 e 4.4 0.5 4.4 0.5 1.1 0.5 e 5 0.5 5 0.5 1.15 0.5 e ns 3 notes: 1. reads and writes are as defined in the truth table. 2. all read and write cycle timings are referenced from k, sk, or data strobes. 3. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some design exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is known and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other reference levels. 4. refer to figure 5 for input reference levels. 5. this parameter is sampled and not 100% tested. 6. measured at 200 mv from steady state. v ih v il v ddq v ss v ddq /2 t kh , t skh t kl , t skl t khkh , t skhskh figure 6. ac timing diagram clock reference
MCM63P636 12 motorola fast sram (a) pullup voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.2 0.4 0.6 0.8 1 1.2 32 32 32 28 24 20 16 12 72 72 72 72 64 56 48 40 2.2 1.8 1.6 0.6 0 0 72 current (ma) voltage (v) 1.4 1.6 8 4 32 24 32 0.2 1.8 2 2.2 0 4 8 16 8 0 (b) pulldown voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.2 0.4 0.6 0.8 1 1.2 10 0 4 8 12 16 20 24 20 0 8 16 24 32 40 48 v ddq 1.8 1.4 0.6 0 072 current (ma) voltage (v) 1.4 1.6 28 28 56 64 28 0.2 1.8 2 2.2 28 28 28 72 72 72 figure 7. typical output buffer characteristics pbga only
MCM63P636 13 motorola fast sram (a) pullup voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.2 0.4 0.6 0.8 1 1.2 23 23 23 20 17 14 11 9 60 60 60 60 53 47 40 33 2.2 1.8 1.6 0.6 0 0 60 current (ma) voltage (v) 1.4 1.6 6 3 27 20 23 0.2 1.8 2 2.2 0 3 6 13 7 0 (b) pulldown voltage (v) pullup i (ma) min i (ma) max 0.5 0 0.2 0.4 0.6 0.8 1 1.2 7 0 3 6 9 11 14 17 17 0 7 13 20 27 33 40 v ddq 1.8 1.4 0.6 0 060 current (ma) voltage (v) 1.4 1.6 20 20 47 53 20 0.2 1.8 2 2.2 20 20 20 60 60 60 figure 8. typical output buffer characteristics tqfp only
MCM63P636 14 motorola fast sram w t avkh sk k ads e q(a) sa a read cycles t khax dqx strba/b b q(a +1) q(a + 2) q(a + 3) q(b) q(b + 1) q(b + 2) q(b + 3) t stvqx strba/b t svkh t khsx t wvkh t khwx t evkh t khex t khqx t khqv t qvstv t skhstv t khqz note: e low = se1 and se3 low and se2 high.
MCM63P636 15 motorola fast sram w sk k ads e d(a) sa a write cycles dqx strba/b b d(a + 1) d(a + 2) d(a + 3) d(b) d(b + 1) strba/b t dvkh t khskh t khdx highz
MCM63P636 16 motorola fast sram w sk k ads e q(a) sa a read/write cycles dqx strba/b b q(a +1) q(a + 2) q(a + 3) d(b) d(b + 1) d(b + 2) d(b + 3) strba/b c q(c) q(c + 1) q(c + 2) q(c + 3) burst read burst write burst read deselect
MCM63P636 17 motorola fast sram functional operation power up and initialization the reset input is used to reset the sram internal logic at power on. at power on, this pin is held low and then driven high at some later time. eight cycles after the reset is as- serted high, standard sram functionality may begin. data strobes the data strobes strba, strba , strbb, and strbb are driven by the sram to be used by the device receiving the output data. the data strobes toggle only at the approxi- mate center of each output data valid window such that the external device can reliably latch in this data. following a burst read, the data strobes will be driven to highz. write cycles the address is sampled on the first rising edge of clock of each burst write sequence, and the write data is sampled on the subsequent rising clock edges. during a burst write the last, last two, or last three addresses may be blocked from being written by asserting the w synchronous write pin high. however, once w is asserted high, it must remain in this state through the remainder of the burst write sequence. all burst write (and masked write) sequences must be followed by an inactive cycle to reset internal state machines. low power stopclock operation in the stopclock mode of operation, the sram will hold all state and data values even though the clock is not running (full static operation). the sram design allows the clock to start with ads , and stops the clock after the last write data is latched, or the last read data is driven out. when starting and stopping the clock, the initial clocks be- ing driven may not meet the ac clock timing parametrics, but will meet those parametrics at least two clocks prior to ads being asserted low. to achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: ? force the clock to a low state. ? force the control signals to an inactive state (this guar- antees any potential source of noise on the clock input will not start an unplanned on activity). ? force the address inputs to a low state (v il ), preferably < 0.2 v. v il k ads sa d in q out a b v ih v il v il highz highz stopclock with read timing ads initiates burst read end burst read k clock stop stopclock low power operation wakeup/ invalid clock invalid clock first valid clock q(a) q(a +1) q(a +2) q(a +3)
MCM63P636 18 motorola fast sram v il k ads sa d in q out a b v ih v il highz stopclock with write timing ads initiates burst write end burst write k clock stop stopclock low power operation wakeup/ invalid clock invalid clock first valid clock w v ih highz v il d(a) d(a +1) d(a +2) d(a +3) v il k ads sa d in q out a v ih v il stopclock with deselect timing continue burst read end read/ deselect k clock stop stopclock low power operation wakeup/ invalid clock invalid clock first valid clock e highz v il q(3) q(4)
MCM63P636 19 motorola fast sram serial boundary scan test access port operation overview the serial boundary scan test access port (tap) on this ram is designed to operate in a manner consistent with ieee standard 1149.11990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra delays in the rams critical speed path. nevertheless, the ram supports the standard tap controller architecture (the tap controller is the state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee standard 1149.1 compliant taps. the tap operates using a 2.5 v tolerant logic level signaling. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, trst should be tied low and tck, tdi, and tms should be pulled through a resistor to 2.0 v. tdo should be left unconnected. tap dc operating characteristics (t a = 0 to 70 c, unless otherwise noted) parameter symbol min max unit notes input logic low v il 1 0.5 0.35 x v ddq v input logic high v ih 1 0.65 x v ddq 2.5 v input leakage current i lkg e 10 m a 1 output logic low v ol 1 v ss 0.5 0.4 v 2 output logic high v oh 1 v ddq 0.4 v ddq + 0.5 v notes: 1. 0 v v in v ddq for all logic input pins. 2. for v ol = 0.4 v, 14 ma i ol 28 ma.
MCM63P636 20 motorola fast sram tap ac operating conditions and characteristics (t a = 0 to 70 c, unless otherwise noted) ac test conditions parameter value unit input timing reference level v ddq /2 v input pulse levels 0 to 2.0 v input rise/fall time (20 to 80%) 1 v/ns output timing reference level v ddq /2 v output load (see figure 4 unless otherwise noted) e e tap controller timing parameter symbol min max unit notes tck cycle time t thth 60 e ns tck clock high time t th 25 e ns tck clock low time t tl 25 e ns tdo access time t tlqv 1 10 ns trst pulse width t tsrt 40 e ns setup times capture tdi tms t cs t dvth t mvth 5 5 5 e ns 1 hold times capture tdi tms t ch t thdx t thmx 13 14 14 e ns 1 note: 1. t cs and t ch define the minimum pauses in ram i/o transitions to assure accurate pad data capture. t thdx t tlqv t dvth t tlth t thmx t mvth tap controller timing diagram t thth test clock (tck) test mode select (tms) test data in (tdi) test data out (tdo) t thtl
MCM63P636 21 motorola fast sram boundary scan order bit no. signal name bump id 1 dqa 3d 2 dqa 1b 3 dqa 2b 4 dqa 1d 5 dqa 2d 6 dqa 1f 7 dqa 2f 8 dqa 1h 9 dqa 2h 10 strba * 3h 11 strba* 3k 12 dqa 2k 13 dqa 1k 14 dqa 2m 15 dqa 1m 16 dqa 2p 17 dqa 1p 18 dqa 2t 19 dqa 1t 20 dqa 3p 21 sa 3t 22 sa 4p 23 sa 4r 24 sa 4t 25 sa1 5r 26 sa0 5t 27 sa 5m 28 sa 5n 29 sa 5p 30 sa 6p 31 sa 6r 32 sa 6t 33 nc* 7t bit no. signal name bump id 34 dqb 7p 35 dqb 8t 36 dqb 9t 37 dqb 9p 38 dqb 8p 39 dqb 9m 40 dqb 8m 41 dqb 9k 42 dqb 8k 43 strbb* 7k 44 strbb 7h 45 dqb 8h 46 dqb 9h 47 dqb 8f 48 dqb 9f 49 dqb 8d 50 dqb 9d 51 dqb 8b 52 dqb 9b 53 dqb 7d 54 sa 7a 55 sa 7b 56 reset 6c 57 ads 5d 58 w 5c 59 k 5f 60 se3 4b 61 sk 5g 62 nu/v ss 5j 63 se2 5a 64 se1 4a 65 sa 3a 66 sa 3b * scans as logic 0.
MCM63P636 22 motorola fast sram test access port pins tck e test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms e test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will not produce the same result as a logic one input level (not ieee 1149.1 compliant). tdi e test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 10, tap controller state diagram). an undriven tdi pin will not produce the same result as a logic one input level (not ieee 1149.1 compliant). tdo e test data out (output) output that is active depending on the state of the tap state machine (refer to figure 10, tap controller state dia- gram). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. trst e tap reset the trst is an asynchronous input that resets the tap controller and preloads the instruction register with the idcode command. this type of reset does not affect the operation of the system logic. the reset affects test logic only. test access port registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the taps registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected it is aplacedo between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruction when trst is asserted or whenever the controller is placed in the testlogicreset state. the two least significant bits of the serial instruction register are loaded with a binary aoro pattern in the captureir state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is identical in length to the number of active input and i/o connections on the ram (not counting the tap pins). this also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. there are a total of 66 bits in the case of the x36 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. the bump/bit scan order table describes which device bump connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. identification (id) register the id register is a 32bit register that is loaded with a device and vendor specific 32bit code when the controller is put in capturedr state with the idcode command loaded in the instruction register. the code is loaded from a 32bit onchip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shiftdr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register presence indicator bit # 0 value 1 motorola jedec id code (compressed format, per ieee standard 1149.11990 bit # 11 10 9 8 7 6 5 4 3 2 1 value 0 0 0 0 0 0 0 1 1 1 0 reserved for future use bit # 16 15 14 13 12 value 0 0 0 1 0 device width bit # 20 19 18 17 value 0 0 1 1 device depth bit # 24 23 22 21 value 0 0 1 0 revision number bit # 31 30 29 28 27 26 25 value 0 0 0 0 0 0 1 figure 9. id register bit meanings
MCM63P636 23 motorola fast sram tap controller instruction set overview there are two classes of instructions defined in the ieee standard 1149.11990; the standard (public) instructions and device specific (private) instructions. some public instructions, are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in pre- scribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully imple- mented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the ram or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/preload command. when the tap controller is placed in captureir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shiftir state the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to updateir state. the tap instruction sets for this device are listed in the following tables. standard (public) instructions bypass the bypass instruction is loaded in the instruction regis- ter when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shiftdr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is an ieee 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller out of the capturedr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metast- able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup, plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shiftdr state then places the boundary scan register between the tdi and tdo pins. be- cause the preload portion of the command is not im- plemented in this device, moving the controller to the updatedr state with the sample/preload instruction loaded in the instruction register has the same effect as the pausedr command. this functionality is not ieee 1149.1 compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capturedr mode and places the id register between the tdi and tdo pins in shiftdr mode. the idcode instruction is the default instruction loaded in at trst assertion and any time the con- troller is placed in the testlogicreset state. the device specific (public) instruction samplez if the highz instruction is loaded in the instruction regis- ter, all dq pins are forced to an inactive drive state (highz) and the bypass register is connected between tdi and tdo when the tap controller. is moved to the shiftdr state. the device specific (private) instruction no op do not use these instructions; they are reserved for future use.
MCM63P636 24 motorola fast sram standard and device specific (public) instruction codes instruction code* description idcode 001** preloads id register and places it between tdi and tdo. does not affect ram operation. highz 010 captures i/o ring contents. places the bypass register between tdi and tdo. forces all dq pins to highz. not ieee 1149.1 compliant. bypass 011 places bypass register between tdi and tdo. does not affect ram operation. not ieee 1149.1 compliant. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect ram operation. does not implement ieee 1149.1 preload function. not ieee 1149.1 compliant. * instruction codes expressed in binary, msb on left, lsb on right. ** default instruction automatically loaded when trst asserted or in testlogicreset state. standard (private) instruction codes instruction code* description no op 000 do not use these instructions; they are reserved for future use. no op 101 do not use these instructions; they are reserved for future use. no op 110 do not use these instructions; they are reserved for future use. no op 111 do not use these instructions; they are reserved for future use. * instruction codes expressed in binary, msb on left, lsb on right. capturedr exit1dr exit2dr updatedr captureir exit1ir exit2ir updateir shiftir pauseir shiftdr pausedr testlogic reset runtest/ idle select drscan select irscan 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. 0 figure 10. tap controller state diagram
MCM63P636 25 motorola fast sram mcm 63p636 xx xxx x motorola memory prefix part number full part numbers e MCM63P636tq200 MCM63P636tq200r MCM63P636zp200 MCM63P636zp200r MCM63P636zp225 MCM63P636zp225r MCM63P636zp250 MCM63P636zp250r package (tq = tqfp, zp = pbga) blank = trays, r = tape and reel speed (250 = 250 mhz, 225 = 225 mhz, 200 = 200 mhz) ordering information (order by full part number) zp package 9 x 17 bump pbga case 110701 0.20 (0.008) dim min max min max inches millimeters a 14.00 bsc 0.551 bsc b 22.00 bsc 0.866 bsc c 2.40 0.094 d 0.60 0.90 0.024 0.035 e 0.50 0.70 0.020 0.028 f 1.30 1.70 0.051 0.067 g 1.27 bsc 0.050 bsc k 0.80 1.00 0.031 0.039 n 11.90 12.10 0.469 0.476 p 19.40 19.60 0.764 0.772 r 10.16 bsc 0.400 bsc s 20.32 bsc 0.800 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. w b r a s g l p n top view d c bottom view 0.15 (0.006) t 0.25 (0.010) t 4x s w s 0.30 (0.012) l s t u t r p n m l k j h g f e d c b a 12345678 s 0.10 (0.004) t 153x 16x g 8x 9 f k e t side view 0.035 (0.014) t package dimensions
MCM63P636 26 motorola fast sram tq package tqfp case 983a01 dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d
MCM63P636 27 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shagawa-ku, tokyo, japan. 03-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 MCM63P636/d ?

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