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philips semiconductors pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator product data supersedes data of 2001 sep 07 2003 jul 31 integrated circuits
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2 2003 jul 31 features ? 3.3 v operation ? three differential cpu clock pairs ? ten pci clocks at 3.3 v ? six 66 mhz clocks at 3.3 v ? two 48 mhz clocks at 3.3 v ? one 14.318 mhz reference clock ? 66,100, 133 or 200 mhz operation ? power management control pins ? cpu clock skew less than 200 ps cycle-to-cycle ? cpu clock skew less than 150 ps pin-to-pin ? 1.5 ns to 3.5 ns delay on pci pins ? spread spectrum capability description the pck2023 is a clock synthesizer/driver for a pentium iv and other similar processors. the pck2023 has three differential pair cpu current source outputs. there are ten pci clock outputs running at 33 mhz and two 48 mhz clocks. there are six 3v66 outputs. finally, there is one 3.3 v reference clock at 14.318 mhz. all clock outputs meet intel?s drive strength, rise/fall times, jitter, accuracy, and skew requirements. the part possesses a dedicated power-down input pin for power management control. this input is synchronized on-chip and ensures glitch-free output transitions. pin configuration sw00695 1 2 3 4 5 6 7 8 9 10 11 12 45 46 47 48 49 50 51 52 53 54 55 56 v dd xtal_out v ss pcif0 pcif1 pcif2 v dd v ss pci0 pci1 ref_0 s1 cpu_stop cpu0 cpu0 v dd cpu1 cpu1 v ss v dd cpu2 pci2 13 14 15 16 17 18 39 40 41 42 43 44 pci3 v dd v ss pci4 pci5 cpu2 iref mult0 v ss iref s2 pci6 19 38 usb 48 mhz v dd 20 21 22 23 24 25 32 33 34 35 36 37 v ss 66buff0/3v66_2 66buff1/3v66_3 66buff2/3v66_4 66in/3v66_5 dot 48 mhz 3v66_1/vch v dd 48 mhz pci_stop 3v66_0 v dd pwrdwn 26 31 v ss v dd a 27 30 sclk v ss a 28 29 vtt_pwrgd sdata xtal_in v ss 48 mhz s0 ordering information packages temperature range order code drawing number 56-pin plastic ssop 0 to +70 c pck2023dl sot371-1 56-pin plastic tssop 0 to +70 c pck2023dgg sot364-1 intel and pentium are registered trademarks of intel corporation.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 3 pin description pin number symbol function 56 ref 3.3 v 14.318 mhz clock output. 2 xtal_in 14.318 mhz crystal input. 3 xtal_out 14.318 mhz crystal output. 44, 45, 48, 49, 51, 52 cpu & cpu [2:0] differential cpu clock outputs. 33 3v66_0 3.3 v 66 mhz clock output. 35 3v66_1/vch 3.3 v selectable through i 2 c to be 66 mhz or 48 mhz 24 66in/3v66_5 66 mhz input to buffered 66buff and pci or 66 mhz clock from internal vco. 21, 22, 23 66buff [2:0] / 3v66 [4:2] 66 mhz buffered outputs from 66 input or 66 mhz clocks from internal vco. 5, 6, 7 pcif [2:0] 33 mhz clocks divided down from 66 input or divided down from 3v66. 10, 11, 12, 13, 16, 17, 18 pci [6:0] pci clock outputs divided down from 66 input or divided down from 3v66. 39 usb fixed 48 mhz clock output. 38 dot fixed 48 mhz clock output. 40 s2 special 3.3 v 3 level input for mode selection. 54, 55 s1, s0 3.3 v lvttl inputs for cpu frequency selection. 42 i ref a precision resistor is attached to this pin which is connected to the internal current reference. 43 mult0 3.3 v lvttl input for selecting the current multiplier for the cpu outputs. 25 pwrdwn 3.3 v lvttl input for powerdown active low. 34 pci_stop 3.3 v lvttl input for pci_stop active low. 53 cpu_stop 3.3 v lvttl input for cpu_stop active low. 28 vtt_pwrgd 3.3 v lvttl input is a level sensitive strobe used to determine when s [2:0] and mult0 inputs are valid and ok to be sampled (active low). 29 sdata i 2 c compatible sdata. 30 sclock i 2 c compatible sclock. 1, 8, 14, 19, 32, 37, 46, 50 v dd 3.3 v power supply for outputs. 26 v dd a 3.3 v power supply for pll. 4, 9, 15, 20, 31, 36, 41, 47 v ss ground for outputs. 27 v ss a ground for pll.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 4 block diagram pwrdwn syspll usbpll 14.318 mhz osc pwrdwn x x x x x x x ref [0](14.318 mhz) pwrdwn xin xout dot/usb 48 mhz cpu [0-2](100/133 mhz) 66ln/3v66_5(66 mhz) pci stop sw00861 pwrdwn x 3v66_0 (66 mhz) pwrdwn x x x cpu stop cpu [0-2](100/133 mhz) pwrdwn pwrdwn pwrdwn pwrdwn x pci [0-6](33 mhz) x pcif [0-2] (33 mhz) 3v66_1/vch(48/66 mhz) pwrdwn x 3v66 [2-4] (66 mhz) x ibias iref x logic s2 x s1 x s0 x mult0 x v tt pwrgd x sda x scl x
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 5 frequency select/function table s2 s1 s0 cpu 3v66 66buff/ 3v66 66in/ 3v66_5 pcif/pci ref 0 usb/dot 3v66_1/ vch 1 0 0 66 mhz 66 mhz 66 in 66 input 66 in/2 14.318 mhz 48 mhz 66/48 mhz 1 0 1 100 mhz 66 mhz 66 in 66 input 66 in/2 14.318 mhz 48 mhz 66/48 mhz 1 1 0 200 mhz 66 mhz 66 in 66 input 66 in/2 14.318 mhz 48 mhz 66/48 mhz 1 1 1 133 mhz 66 mhz 66 in 66 input 66 in/2 14.318 mhz 48 mhz 66/48 mhz 0 0 0 66 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 66/48 mhz 0 0 1 100 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 66/48 mhz 0 1 0 200 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 66/48 mhz 0 1 1 133 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 66/48 mhz mid 0 0 low hi z hi z hi z hi z hi z hi z hi-z mid 0 1 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 tclk/4 note: 1. mid is defined as a voltage level between 1.0 v and 1.8 v for 3 level input functionality. low is below 0.8 v. high is above 2.0 v. 2. 3v66_1/vch output frequency is set by the i 2 c. 3. frequency of the 48 mhz outputs must be +167 ppm to match usb default. 4. rref output min = 14.316 mhz, nominal = 14.31818, max = 14.32 mhz. 5. tclk is a test clock over-driven on the xtal_in input during test mode. power down mode pwrdwn cpu cpu 3v66 66buff/ 3v66 66in/ 3v66_5 pcif/pci ref 0 usb/dot 3v66_1/ vch 1 normal normal normal normal normal normal normal normal normal 0 i ref *2 float low low low low low low low host swing select functions - ck408 mult 0 board impedance i ref i oh v oh @ 50 w 0 50 ? r ref = 221.1% i ref = 5.00 ma i oh = 4*i ref 1.0 v 1 50 ? r ref = 475.1% i ref = 2.32 ma i oh = 6*i ref 0.7 v conditions configuration load min. max. i out v dd = 3.3 v all combinations, see table above nominal test load for given configuration -7% of i oh see table above +7% of i oh see table above i out v dd = 3.3 v 5% all combinations, see table above nominal test load for given configuration -12% of i oh see table above +12% of i oh see table above
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 6 absolute maximum ratings 1, 2 limits symbol parameter condition min max unit v dd3 dc 3.3 v supply -0.5 +4.6 v i ik dc input diode current v i < 0 ? -50 ma v i dc input voltage note 2 ? ? v i ok dc output diode current v o > v dd or v o < 0 ? 50 ma v o dc output voltage note 2 -0.5 v dd + 0.5 v i o dc output source or sink current v o = 0 to v dd ? 50 ma t stg storage temperature range -65 +150 c p tot power dissipation per package plastic medium-shrink (ssop) for temperature range: -40 to +125 c above +55 c derate linearly with 11.3 mw/k ? 850 mw notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. dc operating conditions limits symbol parameter conditions min max unit notes v dd3 dc 3.3 v supply voltage 3.135 3.465 v av dd dc 3.3 v analog supply voltage 3.135 3.465 v v ih 3.3 v high-level input voltage 2.0 v dd + 0.3 v v il 3.3 v high-level input voltage v ss - 0.3 0.8 v v ol3 3.3 v low-level input voltage i ol = 1.0 ma ? 0.4 v v oh3 3.3 v high-level input voltage i oh = 1.0 ma 2.4 ? v i li input leakage current 0 < v in < v dd -5 +5 a 1 f ref reference frequency, oscillator normal value 14.31818 14.31818 mhz c in input pin capacitance ? 5 pf 2 c xtal xtal pin capacitance 13.5 22.5 pf 3 c out output pin capacitance ? 6 pf 2 l pin pin inductance ? 7 nh 2 t amb operating ambient temperature range in free air 0 +70 c notes: 1. input leakage current does not include inputs with pull up or pull down resistors. 2. this is a recommendation, not an absolute requirement. 3. as seen by the crystal. device is intended to be used with a 17-20 pf at crystal.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 7 power management condition maximum 3.3 v supply consumption maximum discrete cap loads, v ddl = 3.465 v all static inputs = v dd3 or v ss power-down mode (pwrdwn = 0) 25 ma @ i ref = 2.32 ma 46 ma @ i ref = 5.0 ma full active 280 ma cpu stop functionality cpu_stop cpu cpu 3v66 66buff pcif/pci usb/dot 1 normal normal 66 mhz 66 input 66 input/2 48 mhz 0 i ref *2 float 66 mhz 66 input 66 input/2 48 mhz dc characteristics limits symbol parameter test conditions t amb = 0 to +70 c unit v dd (v) other min typ max 3.135 v out = 1.0 v type 3a -29 ? ? i oh 48 mhz usb, vch 3.465 v out = 3.135 v type 3a 12-60 ? ? ? -23 ma 3.135 v out = 1.95 v type 3a 29 ? ? i ol 48 mhz usb, vch 3.465 v out = 0.4 v type 3a 12-60 ? ? ? 27 ma 3.135 v out = 1.0 v type 3b -29 ? ? i oh 48 mhz dot 3.465 v out = 3.135 v type 3b 12-60 ? ? ? -23 ma 3.135 v out = 1.95 v type 3b 29 ? ? i ol 48 mhz dot 3.465 v out = 0.4 v type 3b 12-60 ? ? ? 27 ma ref, pci, pcif, 3.135 v out = 1.0 v type 5 -33 ? ? i oh ref, pci, pcif, 3v66, 66buff 3.465 v out = 3.135 v type 5 12-55 ? ? ? -33 ma ref, pci, pcif, 3.135 v out = 1.95 v type 5 30 ? ? i ol ref, pci, pcif, 3v66, 66buff 3.465 v out = 0.4 v type 5 12-55 ? ? ? 38 ma v ol cpu/cpu v ss = 0.0 r s = 33.2 ? r p = 49.9 ? type x1 0.0 ? 0.05 v i i input leakage current 3.365 0 < v in < v dd3 ? -5 ? 5 a i oz 3-state output off-state current 3.465 v out = v dd or gnd i o = 0 ? ? 10 a note: 1. all clock outputs loaded with maximum lump capacitance test load specified in ac characteristics section.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 8 ac characteristics v dd3 = 3.3 v -5%; f crystal = 14.31818 mhz 3v66 66 mhz timing requirements symbol parameter limits t amb = 0 to +70 c unit notes symbol parameter min max unit notes t period period 15.0 15.3 ns 8, 13 t high high time 4.95 n/a ns 9 t low low time 4.55 n/a ns 10 t rise rise time 0.5 2.0 ns 12 t fall fall time 0.5 2.0 ns 12 t jitter cycle-to-cycle jitter ? 250 ps edge rate rising edge rate 1.0 4.0 v/ns 12 edge rate falling edge rate 1.0 4.0 v/ns 12 t skew pin-to-pin skew 3v66 [1:0] 0.0 250 ps t skew pin-to-pin skew 3v66 [5:2] 0.0 250 ps t skew pin-to-pin skew 3v66 [5:0] 0.0 450 ps 66 mhz buffered timing requirements symbol parameter limits t amb = 0 to +70 c units notes symbol parameter min max units notes t rise rise time 0.5 2.0 ns 12 t fall fall time 0.5 2.0 ns 12 t pd propagation delay from 66in to 66buff [2:0] 2.5 4.5 ns edge rate rising edge rate 1.0 4.0 v/ns 12 edge rate falling edge rate 1.0 4.0 v/ns 12 t skew 66 mhz buffered pin-to-pin skew 0.0 175 ps pcif/pci ac timing requirements symbol parameter limits t amb = 0 to +70 c units notes symbol parameter min max units notes t period period 30.0 n/a ns 8, 13 t high high time 12.0 n/a ns 9 t low low time 12.0 n/a ns 10 t rise rise time 0.5 2.0 ns 12 t fall fall time 0.5 2.0 ns 12 t jitter cycle-to-cycle jitter ? ? ps edge rate rising edge rate 1.0 4.0 v/ns 12 edge rate falling edge rate 1.0 4.0 v/ns 12 t skew pin-to-pin skew 0.0 500 ps t pci 3v66 [5:0] leads 33 mhz pci 1.5 3.5 ns
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 9 usb 48 mhz ac timing requirements symbol parameter limits t amb = 0 to +70 c units notes symbol parameter min max units notes t period (average) period nominal = 20.829 ns t high high time 8.094 10.036 ns t low low time 7.694 9.836 ns f frequency 48.000 48.008 mhz 8 t rise rise time 1.0 2.0 ns 12 t fall fall time 1.0 2.0 ns 12 t jitter cycle-to-cycle jitter 0 350 ps edge rate rising edge rate 1.0 2.0 v/ns edge rate falling edge rate 1.0 2.0 v/ns dot 48 mhz ac timing requirements symbol parameter limits t amb = 0 to +70 c units notes symbol parameter min max units notes t period (average) period nominal = 20.829 ns t high high time 8.094 10.036 ns t low low time 7.694 9.836 ns f frequency 48.000 48.008 mhz 8 t rise rise time 0.5 1.0 ns 12 t fall fall time 0.5 1.0 ns 12 t jitter cycle-to-cycle jitter ? 350 ps edge rate rising edge rate 2.0 4.0 v/ns edge rate falling edge rate 2.0 4.0 v/ns t skew usb to dot ? 1000 ps
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 10 cpu 0.7 v ac timing requirements cpu 200 mhz cpu 133 mhz cpu 100 mhz cpu 66 mhz symbol parameter min max min max min max min max units notes t period average period 5.0 5.1 7.5 7.65 10.0 10.2 15.0 15.3 ns 1, 7 t absmin absolute minimum host clock period 4.8 ? 7.3 ? 9.8 ? 14.8 ? ns 1, 7 t rise rise time 175 600 175 600 175 600 175 600 ps 2, 7, 14 t fall fall time 175 600 175 600 175 600 175 600 ps 2, 7, 14 ? t rise rise time variation ? 150 ? 150 ? 150 ? 150 ps 2, 7 ? t fall fall time variation ? 150 ? 150 ? 150 ? 150 ps 2, 7 v cross absolute crossing point voltages 280 430 280 430 280 430 280 430 mv 7 ? v cross total variation of v cross for rising edge of host ? 90 ? 90 ? 90 ? 90 mv 3, 7 total ? v cross total variation of v cross over all edges ? 110 ? 110 ? 110 ? 110 mv 4, 7 t ccjitter cycle-to-cycle jitter ? 150 ? 150 ? 150 ? 150 ps 7, 15 duty cycle 45 55 45 55 45 55 45 55 % 7 overshoot maximum voltage allowed at output ? 850 ? 850 ? 850 ? 850 mv 7 undershoot minimum voltage allowed at output ? -150 ? -150 ? -150 ? -150 mv 7 t skew pin-to-pin ? 150 ? 150 ? 150 ? 150 ps
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 11 cpu 1.0 v ac timing requirements cpu 200 mhz cpu 133 mhz cpu 100 mhz cpu 66 mhz symbol parameter min max min max min max min max units notes t period average period 5.0 5.1 7.5 7.65 10.0 10.2 15.0 15.3 ns 1, 15 t absmin absolute minimum host clock period 4.85 ? 7.35 ? 9.85 ? 14.85 ? ns 1, 15 diff-t rise rise time 175 467 175 467 300 467 300 467 ps 15, 16 diff-t fall fall time 175 467 175 467 175 467 175 467 ps 15, 16 se ? skew absolute single-ended rise/fall waveform symmetry ? 325 ? 325 ? 325 ? 325 ps 17, 18 v cross absolute crossing point voltages 0.51 0.76 0.51 76 0.51 76 ? ? v 18 t ccjitter cycle-to-cycle jitter ? 150 ? 150 ? 150 ? 150 ps 15, 19 duty cycle ? 45 55 45 55 45 55 45 55 % 15 se-v oh maximum voltage allowed at output .92 1.45 .92 1.45 .92 1.45 .92 1.45 v 18 se-v ol minimum voltage allowed at output -200 350 -200 350 -200 350 -200 350 mv 18 diff- v ring_rise rising edge ringback 0.35 ? 0.35 ? 0.35 ? 0.35 ? v 15 diff- v ring_fall falling edge ringback ? -0.35 ? -0.35 ? -0.35 ? -0.35 v 15
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 12 all outputs symbol parameter limits t amb = 0 to +70 c units notes symbol parameter min max units notes t pzl /t pzh output enable delay (all outputs) 1.0 10.0 ns t pzl /t pzh output disable delay (all outputs) 1.0 10.0 ns t stable all clock stabilization from power-up ? 3 ms 11 notes: 1. measured at crossing points or where subtraction of clk-clk crosses 0 v. 2. measured from v ol = 0.175 v to v oh = 0.525 v. 3. these crossing points refer to only crossing points containing a rising edge of a cpu output (as opposed to a cpu output). 4. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cro ssing. 5. measured from v ol = 0.2 v to v oh = 0.8 v. 6. determined as a fraction of 2* (t rise -t fall )/(t rise +t fall ). 7. test load is r s = 33.2 ? , r p = 49.9 ? . 8. period, jitter, offset and skew measured at rising edge @ 1.5 v for 3.3 v clocks. 9. t high is measured at 2.4 v for non-cpu outputs. 10. t low is measured at 0.4 v for all outputs. 11. the time specified is measured from when v ddq achieves its normal operating level (typical condition v ddq = 3.3 v) until the frequency output is stable and operating within specification. 12. the 3.3 v clock t rise and t fall are measured as a transition through the threshold region v ol = 0.4 v and v oh = 2.4 v (1 ma) jedec specification. 13. the average period over any 1 s period of time must be greater than the minimum specified period. 14. designed for 150-420 ps (1 v/ns minimum rise time across 0.42 v). 15. measurement taken from differential waveform. 16. measurement taken from differential waveform from -0.35 to +0.35 v. 17. measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 v. rise/fall time matching is define d as ? the instantaneous difference between maximum clk rise (fall) and minimum clk fall (rise) time, or minimum clk rise (fall) and maximum clk fall (rise) time ? . this parameter is designed for waveform symmetry. 18. measured in absolute voltage, single ended. 19. cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-cpu outputs.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 13 ac waveforms v m = 1.25 v @ v ddl and 1.5 v @ v dd3 v x = v ol + 0.3 v v y = v oh - 0.3 v v ol and v oh are the typical output voltage drop that occur with the output load. host clk 50% 50% v oh v ss v oh v ss t skew sw00850 host clk t period figure 1. host clock v ddl v oh = 2.4 v v ih = 2.0 v 1.5 v v il = 0.7 v v ol = 0.4 v v ss component measurement points system measurement points sw00851 figure 2. 3.3 v clock waveforms t plz t pzl v i sel1, sel0 gnd v dd output low-to-off off-to-low v ol v oh output high-to-off off-to-high v ss outputs enabled outputs enabled outputs disabled t phz v m v m v m t pzh v x v y sw00571 figure 3. state enable and disable times
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 14 pulse generator r t v i d.u.t. v o c l v dd test s 1 t plh /t phl open t plz /t pzl 2 v dd t phz /t pzh v ss open v ss s 1 2 v dd v dd = v ddl or v dd3 , depends on the output 500 ? 500 ? sw00852 figure 4. load circuitry for switching times sw00853 pwrdwn host clk (internal) pciclk (internal) pciclk (external) host clk (external) pwrdwn osc & vco usb (48 mhz) figure 5. power management
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 15 power-up sequence figure 6 shows the power-up sequence for the pck2023. once power is applied to the device, an internal sense circuit generates a signal when the supply is above approximately 2 volts. this signal generates a series of timed signals that control the sequential eve nt inside the device. first, the multifunction pins are latched into the device. these latched signals are then used to define the mode of op eration of the device. a short time later, the pll is enabled and begins running. after xx ms, the clock outputs are enabled and begin running internal 3.3 v supply internal power good signal latch operating mode set/pll start outputs enabled sw00854 figure 6. power-up sequence dut c l v dd r p = 500 ? sw00855 r s r s r s = 33.2 ? r p = 50 ? host host crystal 14.318 mhz figure 7. host clock measurements
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 16 t pkp t pkh t rise t fall t pkl 3.3 v clocking interface 2.4 v 1.5 v 0.4 v sw00856 duty cycle figure 8. 3.3 v clock waveforms
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 17 i 2 c specification s 000000 0 12345678 a s a s a s 1010 0 slave address dummy byte 2 start condition r/w slave acknowledge slave acknowledge slave acknowledge 9 0 000000 0 dummy byte 1 0 a s slave acknowledge byte 0 a s a s a s slave acknowledge slave acknowledge slave acknowledge a s slave acknowledge byte 4 sw00848 a s byte 5 a s byte 6 p byte 3 byte 2 byte 1 slave acknowledge slave acknowledge stop condition 1 0 1 figure 9. i 2 c write s 12345678 a s a m a m 1010 0 slave address start condition r/w slave acknowledge master acknowledge master acknowledge 9 0 000001 1 byte count byte (always 8) a m master acknowledge a m a m a m a m byte 5 sw00849 a m byte 6 p byte 4 byte 3 byte 2 stop condition 1 1 1 master acknowledge master acknowledge master acknowledge master acknowledge master acknowledge byte 0 byte 1 figure 10. i 2 c read
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 18 byte 0 bit description/function type power up condition output(s) affected pin affected source pin 0 s0 reflects the value of the sel_0 pin sampled on power-up r externally selected n/a n/a 54 1 s1 reflects the value of the sel_1 pin sampled on power-up r externally selected n/a n/a 55 2 s2 reflects the value of the sel_2 pin sampled on power-up r externally selected n/a n/a 40 3 pci_stop. this bit is anded with the pci_stop pin for i 2 c readback and control of pci outputs rw externally selected all pci clock outputs except pci[2:0] pins 10, 11, 12, 13, 16, 17, 18 34 4 cpu_stop reflects the current value of the external cpu_stop pin r externally selected all cpu clock pairs 44, 45, 48, 49, 51, 52 53 5 vch select 66 mhz/48mhz enabled rw 0 = 66mhz enabled 3v66_1/vch 35 n/a 6 not used ? 0 ? ? ? 7 spread spectrum enabled rw 0 = spread off cpu[2:0], 3v66[1:0] 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 n/a byte 1 bit description/function type power up condition output(s) affected pin affected source pin 0 cpu0 output enable 1 = enabled 0 = disabled rw 1 = enabled cpu0 cpu0 51, 52 n/a 1 cpu1 output enable 1 = enabled 0 = disabled rw 1 = enabled cpu1 cpu1 48, 49 55 2 cpu2 output enable 1 = enabled 0 = disabled rw 1 = enabled cpu2 cpu2 44, 45 40 3 allow control of cpu0 with assertion of cpu_stop 1 = enabled 0 = disabled rw 0 = not free running, is affected by cpu_stop cpu0 cpu0 51, 52 34 4 allow control of cpu1 with assertion of cpu_stop 1 = enabled 0 = disabled rw 0 = not free running, is affected by cpu_stop cpu1 cpu1 48, 49 53 5 allow control of cpu2 with assertion of cpu stop 1 = enabled 0 = disabled rw 0 = not free running, is affected by cpu_stop cpu2 cpu2 44, 45 n/a 6 not used ? 0 ? ? ? 7 cpu mult0 value sampled at startup r externally selected n/a n/a 43
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 19 byte 2 bit description/function type power up condition output(s) affected pin affected source pin 0 pci0 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci0 10 n/a 1 pci1 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci1 11 n/a 2 pci2 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci2 12 n/a 3 pci3 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci3 13 n/a 4 pci4 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci4 16 n/a 5 pci5 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci5 17 n/a 6 pci6 output enabled 1 = enabled 0 = disabled rw 1 = enabled pci6 18 n/a 7 not used ? 0 n/a n/a n/a byte 3 bit description/function type power up condition output(s) affected pin affected source pin 0 pcif0 output enabled rw 1 = enabled pcif0 5 n/a 1 pcif1 output enabled rw 1 = enabled pcif1 6 n/a 2 pcif2 output enabled rw 1 = enabled pcif2 7 n/a 3 allow control of pcif0 with assertion of pci_stop 0 = free running 1 = stopped with pci_stop rw 0 = free running not affected by pci_stop pcif0 5 n/a 4 allow control of pcif1 with assertion of pci_stop 0 = free running 1 = stopped with pci_stop rw 0 = free running not affected by pci_stop pcif1 6 n/a 5 allow control of pcif2 with assertion of pci_stop 0 = free running 1 = stopped with pci_stop rw 0 = free running not affected by pci_stop pcif2 7 n/a 6 usb 48mhz output enabled rw 1 = enabled usb 48mhz 39 n/a 7 dot 48 mhz output enabled rw 1 = enabled dot 48mhz 38 n/a
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 20 byte 4 bit description/function type power up condition output(s) affected pin number 0 66buff0/3v66_2 output enabled 1 = enabled 0 = disabled rw 1 = enabled 66buff0/3v66_2 21 1 66buff1/3v66_3 output enabled 1 = enabled 0 = disabled rw 1 = enabled 66buff1/3v66_3 22 2 66buff2/3v66_4 output enabled 1 = enabled 0 = disabled rw 1 = enabled 66buff2/3v66_4 23 3 3v66_5 output enabled 1 = enabled 0 = disabled rw 1 = enabled 3v66_5 24 4 3v66_1/vch output enabled 1 = enabled 0 = disabled rw 1 = enabled 3v66_1/vch 35 5 3v66_0 output enabled 1 = enabled 0 = disabled rw 1 = enabled 3v66_0 33 6 not used ? 0 ? ? 7 not used ? 0 ? ? byte 5 bit description/function type power up condition output(s) affected pin number 0 rw 0 usb 39 1 usb edge rate control rw 0 usb 39 2 rw 0 dot 38 3 dot edge rate control rw 0 dot 38 4 not used ? 0 ? ? 5 not used ? 0 ? ? 6 not used ? 0 ? ? 7 not used ? 0 ? ? byte 6 bit description/function type power up condition output(s) affected pin number 0 vendor id bit 0 r 1 n/a n/a 1 vendor id bit 1 r 1 n/a n/a 2 vendor id bit 2 r 1 n/a n/a 3 vendor id bit 3 r 0 n/a n/a 4 revision code bit 0 r 0 n/a n/a 5 revision code bit 1 r 0 n/a n/a 6 revision code bit 2 r 0 n/a n/a 7 revision code bit 3 r 0 n/a n/a
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 21 application notes optimum performance of the pck2023 can only be achieved through correct implementation in the system board. this application note addresses many of the issues associated with integrating the pck2023 on a system board. descriptions for circuit board layout and decoupling are provided in this application note. circuit board layout it is possible to generate a circuit board with the proper characteristics using four-layer configuration. figure 11 shows the layer stack-up. it is critical to keep the clock signals on a plane next to a ground plane to ensure they are ground referenced otherwise the clock signals may experience significant distortion and added jitter. static signals (such as spread , pwrdwn, etc.) can be placed on a layer next to the power plane. the components associated with the clocks should be placed on the same layer as the pck2023 ic. this will allow the layout to avoid the use of vias for interconnect, thereby reducing node capacitance and trace inductance. all components should be placed as close to the ic as possible. clock signals ground power static signals sw00857 figure 11. optimum board layout
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 22 component decoupling decoupling is another important consideration to ensure optimum operation of the pck2023. a first pass decoupling capacitor value may be determined by applying the following equation: c bypass 1 2pf psw x max where x max v i f psw x max 2pl psw ? v is the maximum supply noise permitted (20 mv, for example) ? i is the maximum current draw for the clock l psw is the power supply lead inductance f psw is the frequency below which the power supply wiring is adequate the maximum current may be determined by considering the switching of the clock outputs and the capacitive load on these outputs. the following equation may be used to determine the current per output. once the current for each clock output is determined, they can be summed to determine the total switching current. i c load dv dt most of these values can be determined from the usage in the board design. for example, the ioclk has a specified edge rate of 1.25 ns typical when slewing between 0.7 and 2.4 volts and the maximum c load is 30 pf. the host outputs are a special case since, although the output either drives current or is off, only one drives at a time, so the current is really steered rather than switched. the act of steering the current reduces switching noise on these supplies, therefore the host supplies require less decoupling. as a starting point, assume the supply current for each host output is equal to 1/2 the programmed output current. decoupling capacitors should be located as close to the power pins on the ic as possible. the use of too much decoupling should be avoided since it could cause oscillations on the part because of the lc circuit (the ic leads act as inductors). also, it is possible to cause oscillations from resonance between the board inductance and board capacitance. two capacitors may be placed in parallel to effectively extend the capacitance range of the decoupling since the larger capacitor will have a self-resonance at a lower frequency than the smaller capacitor. when using this method, the split between values should be 100 (i.e., 0.1 f and 0.001 f). another consideration when selecting the decoupling capacitors is the dielectric material of the capacitor. this will depend on the frequency range of concern. for lower frequencies, z5u material may be used since this type of capacitor has a self-resonance in the 1 mhz to 20 mhz range. capacitors of npo have a self-resonance much higher and are more for high frequency decoupling. consult a capacitor manufacture ? s datasheet to determine the optimum material type to use. additional filtering on the analog supplies (av dd ) may be used to reduce the noise coupled from the circuit board global v dd to the internal v dd of the pck2023. one way to do this is to use a pi filter. the specific values should be selected to allow proper decoupling on the pin side while rejecting the digital switching noise. a spectrum analyzer can provide considerable insight to ensure optimum values are selected. measure the frequency content of the supply on either side of the inductor to verify the values selected reduce the noise on the component side of the filter. to provide the maximum isolation, each av dd line should have a separate filter since the internal circuitry using these lines have very different switching requirements. in general, pin 26 is strictly a static current draw and should not have any switching noise. great care has been taken to reduce the sensitivity to supply noise, but there is a finite limit to the capability to do this, therefore added filtering on the board should enhance performance. pin 46 is used as a supply to the internal plls. this node will contain some high frequency switching noise since the internal plls operate up to 200 mhz. again, additional filtering will improve the performance of the part. if a single filter is used for both supplies, noise from the pll supply (pin 46) can couple int the i ref supply (pin 42) and increase the jitter of the host outputs. av dd v dd3.3 sw00858 figure 12. pi filter for all analog v dd lines i ref decoupling filtering on the i ref supply has already been discussed, but additional filtering can be added on the i ref pin (pin 42) to perform additional filtering of the reference current. this reference current is critical to the performance of the host outputs since variation in this current is directly proportional to jitter on the host outputs. on-die decoupling has been included to reduce noise on this node, but additional decoupling could also be used to further reduce any noise. care must be taken with this approach to ensure the capacitor and reference resistor share the same ground. placing both components side by side is an optimum configuration. this external capacitor should not exceed tbd pf to ensure the current source inside the pck2023 can supply enough charge for this node to reach reference value (1.1 volt).
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 23 functional connection figure 13 shows a partial diagram of the pck2023 in an application. the host outputs are differential current drivers, therefore the output current is converted to a voltage by using some type of load resistor (in this case, r s and r p ). the output current is based on two, the value of r ref and the setting on multsel0 and multsel1 pins. the i ref pin is actually a reference voltage which is fixed at 1.1 volts, therefore, i ref is 1.1/r ref . there are limitations on how large the current can be made. this is coupled to the termination resistors used. the maximum voltage which should be observed at the host or host pins of the pck2023 is 1.1 volts. this value may be determined by using: v max ( r s r p ) n mult 1.1 r ref where r s and r p are the termination resistor values, n mult is the current multiplier set by multsel0 and multsel1, and r ref is the current reference resistor. v max should not exceed 1.1 volts because of the internal current source configuration. r s r s r p r p r ref hi i ref hclk hclkb pck2023 load hi sw00859 figure 13. pck2023 implementation in a circuit board
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 24 pulse generator r t v i d.u.t. v o c l v dd test s 1 t plh /t phl open t plz /t pzl 2 v dd t phz /t pzh v ss open v ss s 1 2 v dd v dd = v ddq2 or v ddq3 , depends on the output 500 ? 500 ? sw00574 figure 14. host clock measurements t period duty cycle t high t rise t fall t low t period t high t rise t fall t low 2.5 v clocking interface 3.3 v clocking interface (ttl) 2.0 v 1.25 v 0.4 v 2.4 v 1.5 v 0.4 v sw00860 duty cycle figure 15. 2.5 v/3.3 v clock waveforms
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 25 ac waveforms v m = 1.25 v @ v ddl and 1.5 v @ v dd3 v x = v ol + 0.3 v v y = v oh - 0.3 v v ol and v oh are the typical output voltage drop that occur with the output load. cpuclk @133mhz 1.5v 1.25v v ddq2 v ss v ddq3 v ss t hpoffset sw00569 3v66 @66mhz cpu leads 3v66 figure 16. host clock v ddq2 2.5volt measure points v oh = 2.0v v ih = 1.7v 1.25v v il = 0.7v v ol = 0.4v v ss system measurement points v ddq3 3.3volt measure points v oh = 2.4v v ih = 2.0v 1.5v v il = 0.7v v ol = 0.4v v ss component measurement points system measurement points component measurement points sw00570 figure 17. 3.3 v clock waveforms t plz t pzl v i sel1, sel0 gnd v dd output low-to-off off-to-low v ol v oh output high-to-off off-to-high v ss outputs enabled outputs enabled outputs disabled t phz v m v m v m t pzh v x v y sw00571 figure 18. state enable and disable times
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 26 pulse generator r t v i d.u.t. v o c l v dd test s 1 t plh /t phl open t plz /t pzl 2 v dd t phz /t pzh v ss open v ss s 1 2 v dd v dd = v ddq2 or v ddq3 , depends on the output 500 ? 500 ? sw00572 c l includes jig and probe capacitance figure 19. load circuitry for switching times sw00573 pwrdwn cpuclk (internal) pciclk (internal) pciclk (external) cpuclk (external) pwrdwn osc & vco usb (48 mhz) figure 20. power management
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 27 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 28 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 29 revision history rev date description _2 20030731 product data (9397 750 11763); ecn 853-2278 30053 dated 18 june 2003. supersedes data of 2001 september 07 (9397 750 09142). modifications: ? minor changes or corrections to existing product specifications. _1 20010907 product data (9397 750 09142); ecn 853-2278 27052 of 07 september 2001.
philips semiconductors product data pck2023 ck408 (66/100/133/200 mhz) spread spectrum differential system clock generator 2003 jul 31 30 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 07-03 document order number: 9397 750 11763 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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