km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 1 document title 64kx8 bit low power and low voltage cmos static ram revision history the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision no. 0.0 0.1 1.0 2.0 3.0 remark advance preliminary final final final history design target initial draft - one datasheet for commercial, extended and industrial product. - add 85ns part on km68v512a family. finalize revise - add 32-stsop type package on product. revise - change datasheet format - improve power dissipation 0.7 to 1.0w draft data january 17, 1996 april 15, 1996 june 17, 1996 september 10, 1996 february 12, 1998
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 2 64kx8 bit low power and low voltage cmos static ram general description the km68v512a and KM68U512A families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and have various package types for user flexibility of system design. the family also support low data retention voltage for battery back-up operation with low data retention current. features process technology : poly load organization : 64kx8 power supply voltage km68v512a family : 2.7~3.3v KM68U512A family : 3.0~3.3v low data retention voltage : 2v(min) three state output and ttl compatible package type : 32-sop-525, 32-tsop1-0820f, 32-tsop1-0813.4f pin description name name function cs 1 ,cs 2 chip select inputs oe output enable input we write enable input a 0 ~a 15 address inputs i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground n.c no connection product family 1. the parameter is measured with 30pf test load. product family operating temperature v cc range speed(ns) power dissipation pkg type standby (isb 1 , max) operating (icc 2 , max) km68v512al-l commercial(0~70 c) 3.0 ~ 3.6v 70 1) /85/100 10 m a 40ma 32-sop 32-tsop1-f 32-stsop1-f KM68U512Al-l 2.7 ~ 3.3v 85 1) /100 10 m a km68v512ale-l extended(-25~85 c) 3.0 ~ 3.6v 70 1) /85/100 20 m a KM68U512Ale-l 2.7 ~ 3.3v 85 1) /100 15 m a km68v512ali-l industrial (-40~85 c) 3.0 ~ 3.6v 70 1) /85/100 20 m a KM68U512Ali-l 2.7 ~ 3.3v 85 1) /100 15 m a functional block diagram 32-tsop type1 - forward (8mm x 20mm) (8mm x 13.4mm) 32-sop n.c a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n.c cs2 a11 a9 a8 a13 we cs2 a15 vcc n.c n.c a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 a11 a9 a8 a13 we cs2 a15 vcc n.c n.c a14 a12 a7 a6 a5 a4 samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 512 rows 128 8 columns i/o circuit column select clk gen. row select a0 a1 a2 a3 a9 a11 a10 a4 a5 a6 a7 a8 a12 a14 cs 1 cs2 we i/o 1 data cont data cont oe i/o 8 a13 a15 32-stsop type1 - forward control logic
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 3 product list commercial temperature products (0~70 c) extended temperature products (-25~85 c) industrial temperature products (-40~85 c) part name function part name function part name function km68v512alg-7l km68v512alg-8l km68v512alg-10l km68v512alt-7l km68v512alt-8l km68v512alt-10l km68v512altg-7l km68v512altg-8l km68v512altg-10l KM68U512Alg-8l KM68U512Alg-10l KM68U512Alt-8l KM68U512Alt-10l KM68U512Altg-8l KM68U512Altg-10l 32-sop, 70ns, 3.3v, ll 32-sop, 85ns, 3.3v, ll 32-sop, 100ns, 3.3v, ll 32-tsop f, 70ns, 3.3v, ll 32-tsop f, 85ns, 3.3v, ll 32-tsop f, 100ns, 3.3v,ll 32-stsop f,70ns,3.3v,ll 32-stsop f,85ns,3.3v,ll 32-stsop f,100ns,3.3v,ll 32-sop, 85ns, 3.0v, ll 32-sop, 100ns, 3.0v, ll 32-tsop f, 85ns, 3.0v, ll 32-tsop f, 100ns, 3.0v, ll 32-stsop f, 85ns, 3.0v, ll 32-stsop f, 100ns,3.0v, ll km68v512alge-7l km68v512alge-8l km68v512alge-10l km68v512alte-7l km68v512alte-8l km68v512alte-10l km68v512altge-7l km68v512altge-8l km68v512altge-10l KM68U512Alge-8l KM68U512Alge-10l KM68U512Alte-8l KM68U512Alte-10l KM68U512Altge-8l KM68U512Altge-10l 32-sop, 70ns, 3.3v, ll 32-sop, 85ns, 3.3v, ll 32-sop, 100ns, 3.3v, ll 32-tsop f, 70ns, 3.3v, ll 32-tsop f, 85ns, 3.3v, ll 32-tsop f, 100ns, 3.3v,ll 32-stsop f,70ns,3.3v,ll 32-stsop f,85ns,3.3v,ll 32-stsop f,100ns,3.3v,ll 32-sop, 85ns, 3.0v, ll 32-sop, 100ns, 3.0v, ll 32-tsop f, 85ns, 3.0v, ll 32-tsop f, 100ns, 3.0v, ll 32-stsop f, 85ns, 3.0v, ll 32-stsop f, 100ns,3.0v, ll km68v512algi-7l km68v512algi-8l km68v512algi-10l km68v512alti-7l km68v512alti-8l km68v512alti-10l km68v512altgi-7l km68v512altgi-8l km68v512altgi-10l KM68U512Algi-8l KM68U512Algi-10l KM68U512Alti-8l KM68U512Alti-10l KM68U512Altgi-8l KM68U512Altgi-10l 32-sop, 70ns, 3.3v, ll 32-sop, 85ns, 3.3v, ll 32-sop, 100ns, 3.3v, ll 32-tsop f, 70ns, 3.3v, ll 32-tsop f, 85ns, 3.3v, ll 32-tsop f, 100ns, 3.3v,ll 32-stsop f,70ns,3.3v,ll 32-stsop f,85ns,3.3v,ll 32-stsop f,100ns,3.3v,ll 32-sop, 85ns, 3.0v, ll 32-sop, 100ns, 3.0v, ll 32-tsop f, 85ns, 3.0v, ll 32-tsop f, 100ns, 3.0v, ll 32-stsop f, 85ns, 3.0v, ll 32-stsop f, 100ns,3.0v, ll functional description 1. x means don t care(must be low or high state.) cs 1 cs 2 oe we i/o mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v - voltage on vcc supply relative to v cc -0.3 to 4.6 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c km68v512al-l, KM68U512Al-l -25 to 85 c km68v512ale-l, KM68U512Ale-l -40 to 85 c km68v512ali-l, KM68U512Ali-l soldering temperature and time t solder 260 c, 10sec (lead only) - -
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 4 recommended dc operating conditions 1) note: 1. commercial product : t a =0 to 70 c, otherwise specified extended product : t a =-25 to 85 c, otherwise specified industrial product : t a =-40 to 85 c, otherwise specified 2. overshoot : v cc +3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested item symbol product min typ max unit supply voltage vcc km68v512a family 3.0 3.3 3.6 v KM68U512A family 2.7 3.0 3.3 v ground vss all family 0 0 0 v input high voltage v ih km68v512a, KM68U512A family 2.2 - vcc+0.3v 2) v input low voltage v il km68v512a, KM68U512A family -0.3 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 6 pf input/output capacitance c io v io =0v - 8 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v ih or v il - - 5 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 1 0.2v, cs 2 3 vcc-0.2v, v in 0.2v or v in 3 vcc-0.2v - - 5 ma i cc2 cycle time=min, 100% duty, i io =0ma cs 1 =v il , cs 2 =v ih , v in =v il or v ih - - 40 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v il or v ih - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v, or cs 2 0.2v , other inputs=0~vcc km68v512al-l - - 10 m a km68v512ale-l km68v512ali-l - - 20 m a KM68U512Al-l - - 10 m a KM68U512Ale-l KM68U512Ali-l - - 15 m a
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 5 ac characteristics (km68v512b family:vcc=3.0~3.6v, km68u512b family:vcc=2.7~3.3v, commercial product:t a =0 to 70 c, extended product:t a =-25 to 85 c, industrial product:t a =-40 to 85 c) parameter list symbol speed bins units 70ns 85ns 100ns min max min max min max read read cycle time t rc 70 - 85 - 100 - ns address access time t aa - 70 - 85 - 100 ns chip select to output t co - 70 - 85 - 100 ns output enable to valid output t oe - 35 - 45 - 50 ns chip select to low-z output t lz 10 - 10 - 10 - ns output enable to low-z output t olz 5 - 5 - 5 - ns chip disable to high-z output t hz 0 25 0 30 0 30 ns output disable to high-z output t ohz 0 25 0 20 0 20 ns output hold from address change t oh 10 - 10 - 15 - ns write write cycle time t wc 70 - 85 - 100 - ns chip select to end of write t cw 60 - 70 - 80 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 60 - 70 - 80 - ns write pulse width t wp 55 - 60 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 25 0 30 ns data to write time overlap t dw 30 - 35 - 40 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions ( test load and input/output reference) input pulse level : 0.4 to 2.2v input rising and falling time : 5ns input and output reference voltage :1.5v output load(see right) : c l =100pf+1ttl 1) c l =30pf+1ttl 1. km68v512al-7l family, KM68U512Al-8l family data retention characteristics 1. cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled) item symbol test condition min typ max unit vcc for data retention v dr cs 1 1) 3 vcc-0.2v 2.0 - 3.6 v data retention current i dr km68v512al-l km68v512ale-l km68v512ali-l vcc=3.0v, cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v - - - - - - 10 15 15 m a KM68U512Al-l KM68U512Ale-l KM68U512Ali-l - - - - - - 8 10 10 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 7 timing waveform of write cycle(1) (we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 8 data retention wave form cs 1 controlled v cc 3.0/2.7v 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) ( cs 1 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low : a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr(1) applied in case a write ends as cs 1 or we going high t wr(2) applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 3.0/2.7v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr . cs 2 0.2v
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 9 package dimensions 32 pin small outline package (525mil) units : millimeter(inch) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16
km68v 512a, KM68U512A family cmos sram revision 3.0 february 1998 10 32 pin thin small outline package type i (0813.4f) package dimensions 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.10 0.528 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 #32 #17 32 pin thin small outline package type i (0813.4r) 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #16 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.10 0.528 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #1 #17 #32 units : millimeter(inch)
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