pre-production process TQPED 0.5 um e/d phemt foundry service features ? e-mode, 0.35 v, vth ? d-mode, -0.8 v vp ? ingaas active layer phemt process ? 0.5 um optical lithography gates ? high density interconnects: ? 2 global ? 1 local ? high-q passives ? thin film resistors ? high value capacitors ? backside vias optional ? based on production tqpht phemt and interconnect ? nominal tom3 fet models available applications ? highly efficient, and linear power amplifiers ? low loss, high isolation, low- harmonic contnt switches ? integrated digital control logic for switches and transceivers ? converters ? integrated rf front ends? lna, sw, pa ? wireless transceivers, base sta- tions, direct broadcast satellite radars, digital radios, rf / mixed signal ics ? power detectors and couplers general description triquint?s TQPED process is based on our production-released 0.5 m tqpht process. TQPED partners an e-mode phemt device with our tqpht d-mode transistors to be the first foundry phemt process to integrate e-mode and d-mode tran- sistors on the same wafer. this process is targeted for low noise amplifiers, linear, low loss and high isolation rf switch applica- tions, converters and integrated rf front ends. the TQPED process offers a d-mode phemt with a ?0.8 v pinch off, and an e-mode phemt with a +0.35 v threshold voltage. the three metal interconnecting layers are encapsulated in a high perform- ance dielectric that allows wiring flexibility, optimized die size and plastic packaging simplicity. precision nicr resistors and high value mim capacitors are included allowing higher levels of integration, while maintaining smaller, cost ?effective die sizes. page 1 of 3; rev 1.0 12/1/2004 isolation implant pseudomorphic channel n+ metal 2 - 4um metal 1 metal 2 dielectric metal 1 - 2um dielectric dielectric metal 0 nitride isolation implant metal 1 mim metal isolation implant pseudomorphic channel n+ metal 2 - 4um metal 1 metal 2 dielectric metal 1 - 2um dielectric dielectric metal 0 nitride isolation implant metal 1 mim metal nicr e-mode / d-mode phemt nicr resistor mim capacitor semi-insulating gaas substrate 0.5 um phemt device cross-section production release: q1?2005
production process TQPED 0.5 um e/d phemt foundry service semiconductors for communications www.triquint.com triquint semiconductor 2300 ne brookwood pkwy hillsboro, oregon 97124 phone: 503-615-9000 fax: 503-615-8905 email: info@triquint.com page 2 of 5; rev 2.0 7/22/03 process details @ vds = 3.0v element parameter value units d-mode phemt vp (1ua/um) -0.8 v idss 225 ma/mm imax 550 ma/mm breakdown, vdg 15 min, 20 typ v ft @ 50% idss 25 ghz fmax @ 50% idss 90 ghz gm (50% idss) 350 ms/mm ron 1.5 ohms * mm e-mode phemt vth (1ua/um) +0.35 v idss 0.1 ua/um imax 310 ma/mm breakdown, vdg 15 min, 18 typ v ft @ 50% idss 30 ghz fmax @ 50% idss 100 ghz gm (50% idss) 625 ms/mm ron 2.5 ohms * mm common process element details gate length 0.5 m interconnect 3 metal layers mim caps value 630 pf/mm2 resistors nicr 50 ohms/sq bulk 285 ohms/sq TQPED process details maximum ratings storage temperature range -65 to +150 deg c operating temperature range -55 to +150 deg c efet/dfet transistor (vs open; idg = 1ua/um) 15 v capacitor 40 v page 2 of 3; rev 1.0 12/1/2004 pre-production process
design tool status ? complete design manual now ? device library of circuit elements: fets, diodes, thin film resistors, capacitors, inductors ? design kit for agilent?s ads design environment ? design kit planned for awr microwave office ? layout library in gsd ii format ? cadence development kit with pcells in preliminary release ? layout rule sets for design rule check for iced, ca- dence ? qualified package models for supported package styles ? noise parameters on specific device sizes available please contact your local triquint semiconductor representative/ distributor or foundry services division for additional information: e-mail: sales@triquint.com phone: (503) 615-9000 fax: (503) 615-8905 pre-production process TQPED 0.5 um e/d phemt foundry service triquint semiconductor 2300 ne brookwood pkwy hillsboro, oregon 97124 phone: 503-615-9000 fax: 503-615-8905 email: info@triquint.com semiconductors for communications www.triquint.com page 3 of 3; rev 1.0 12/1/2004 prototyping and development ? prototype development quick turn (pdq): ? shared mask set ? run monthly ? hot lot cycle time ? prototype wafer option (pwo): ? customer-specific masks; customer schedule ? 2 wafers delivered ? hot lot cycle time ? with thinning and sawing; optional backside vias process qualification status ? mature process based on tqpht 150-mm process ? process release to production scheduled for q1 2005 ? full 150mm wafer process qualification in process. to be completed early q1 2005 ? for more information on quality and reliability, contact triquint or visit: www.triquint.com/manufacturing/qr/ applications support services ? tiling of gdsii stream files including pcm ? design rule check services ? layout versus schematic check services ? packaging development engineering ? test development engineering: ? on-wafer ? packaged parts ? thermal analysis engineering ? yield enhancement engineering ? part qualification services ? failure analysis training ? gaas design classes: ? half-day introduction; upon request ? four-day technical training; fall and spring at triquint oregon facility ? for training & pdq schedules, please visit: www.triquint.com/foundry/ manufacturing services ? mask making ? production 150-mm wafer fab ? wafer thinning ? wafer sawing ? substrate vias ? dc diesort testing ? rf on-wafer testing ? plastic packaging ? rf packaged part testing
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