a a cmos 300 mhz complete-dds synthesizer product concept AD9852 adi proprietary and confidential features 300 mhz internal clock rate on-chip 12-bit dac & high-speed comparator excellent dynamic performance: 84 db sfdr @ 100 mhz ( 1 mhz) aout 4-20x pll reference clock multiplier 32-bit frequency/14-bit phase tuning words two programmable frequency/phase registers fm chirp function sin x/x correction simplified control interface: serial & parallel +3 v single supply low power: 500 mw @ 300 mhz power-down function ultra-small 44-pin tqfp packaging applications agile l.o. frequency synthesis in amateur radio tuners cellular/dcs/gsm basestation programmable clock generator fm chirp source for acousto-optic laser scanning system master reset frequency update/ data register reset 300 mhz dds mpu interface +v gnd 8-bit byte parallel 32-bit tuning word frequency/phase data registers word load clock ref clock i n control words vinp qout qout 12- bit dac analog out dac rset 4-20x pll inverse sinc filter comparator + - analog out vinn 1-bit serial serial load chirp control freq select register address phase select frequency, phase, and control data AD9852 functional block diagram general description the AD9852 digital synthesizer is a highly integrated device that uses advanced dds technology, coupled with an internal high- speed, high performance d/a converter and comparator to form a digitally-programmable synthesizer function.when referenced to an accurate clock source, the AD9852 generates a highly stable, frequency/phase-programmable output sinewave that can be used as an agile l.o. in communications, radar, and many other applications. the AD9852's innovative high-speed dds core provides a 32-bit frequency tuning word, which results in an output tuning resolution of .07 hz, for a 300 mhz internal reference clock input. the AD9852's circuit architecture allows the generation of an output sinewave at up to one-third the clock frequency, or 100 mhz, which can be digitally changed up to a rate of 25 million new frequencies per second. the device also provides 14-bits of digitally-controlled phase modulation. the on-board 12-bit dac, coupled with the innovative dds architecture, provides excellent output wideband and narrowband sfdr. the AD9852?s programmable 4-20x reference clock pll generates the 300 mhz clock internally, from an external reference clock. this saves the user the expense and difficulty of implementing a 300 mhz clock source. the ad9850 uses advanced cmos technology to provide this high level of functionality on <500 mw of power dissipation, at a maximum internal clock rate of 300 mhz. the AD9852 is available in a space-saving 44-pin tqfp surface mount package. it is specified to operate over the extended industrial temperature range of -40 to +85c. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way; p.o. box 9106; norwood, ma 02062-9106 tel: 617/329-4700 twx: 710/394-6577 west coast central atlantic 714/641-9391 214/231-5094 215/643-7790 2/17/98
2 AD9852 product concept absolute maximum ratings 1 maximum junction temp. .................................... +165c storage temperature ............................ -65c to +150c vs ............................................................ +6v operating temp. .............................. .... -40c to +85c digital inputs ................................ -0.7v to +vs lead temp. (10 sec. soldering) ........................... +300c digital output current ............................... 5ma AD9852 goal electrical specifications (vs=+3 v 5%, rset=3.9 k w w ) parameter temp test level AD9852 min typ max units clock input characteristics 2 internal clock frequency range full vi 10 300 mhz duty cycle +25c i 50 % input capacitance +25c iv 3 pf input impedance +25c iv 100 m w dac output characteristics full scale output current +25c v 10 ma gain error +25c i tbd %fs output offset +25c i tbd ua differential non-linearity +25c i .5 lsb integral non-linearity +25c i 1 lsb output slew rate +25c iv tbd v/ns output impedance +25c i 100 k w voltage compliance range +25c i 1 v wideband sfdr: 1 mhz aout +25c v 75 dbc 20 mhz aout +25c v 65 dbc 40 mhz aout +25c v 62 dbc 100 mhz aout +25c v 50 dbc narrowband sfdr 3 : 100 mhz aout ( 15 mhz) +25c v 75 dbc 100 mhz aout ( 1 mhz) +25c v 84 dbc 100 mhz aout ( 50 khz) +25c v 90 dbc comparator input characteristics input capacitance +25c v 3 pf input resistance +25c iv 500 k w input bias current +25c i 12 na input voltage range +25c iv 0 v dd v comparator output characterisitics logic "1" voltage full vi +4.95 v logic "0" voltage full vi +0.4 v propagation delay +25c iv, 7 ns clock output ac characteristics 4 clock output duty cycle full vi 50 % rise/fall time +25c iv 1 ns output jitter (rms) +25c iv 20 ps cmos logic inputs logic "1" voltage +25c i 2.7 v logic "0" voltage +25c i 0.4 v logic "1" current +25c iv 12 ua logic "0" current +25c iv 12 ua input capacitance +25c v 3 pf
3 AD9852 product concept ____________________________________________________________________________________________ AD9852 goal electrical specifications (vs=+3 v 5 %, rset=3.9 k w w ) parameter temp test level AD9852 min typ max units power supply +vs current @: 50 mhz external clock (pll enabled) +25c i 166 ma p diss@: 50 mhz external clock +25c i 500 mw p diss power-down mode +25c i 10 mw notes 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. 2 the reference clock input is configured to accept a sine wave input or a ttl-level pulse input. 3 reference clock frequency is selected to insure second harmonic is out of the bandwidth of interest. 4 reference clock input=50 mhz; output frequency=40mhz; external filter=5-pole low-pass. explanation of test levels test level i - 100% production tested. iii - sample tested only. iv - parameter is guaranteed by design and characterization testing. v - parameter is a typical value only. vi - all devices are 100% production tested at +25c. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. table i. AD9852 pin-function descriptions clkin reference clock input. this may be a sine input or continuous ttl/cmos-level pulse train. rset this is the dac's external rset connection. this resistor value sets the dac fullscale output current. agnd analog ground. these pins are the ground return for the analog circuitry (dac and comparator). vdd supply voltage pins for digital circuitry. avcc supply voltage for the analog circuitry (dac and comparator). w_clk word load clock. this clock is used to load each of the (up to) five iterations of the 8-bit fq_ud frequency u pdate. when this pin is set high, the dds will update to the frequency d0-d7 8-bit data input. this is the 8-bit data port for iteratively loading the 32-bit reset reset. this is the master reset pin; when set high it clears all registers and the dac iout the true output of the differential dac. ioutb the complementary output of the differential dac. dacbl dac baseline. this is the dac baseline reference; it should normally be left as a no connect. vinp voltage input positive. this is the comparator' s positive input pin. vinn voltage input negative. this is the comparator's negative input pin. qoutb output complement. this is the comparator's complementary output pin. qout ouput true. this is the comparator's positive output pin. fselect frequency select input. controls which frequency register, f0 or f1, is added to the phase accumulator pselect phase select input. controls which phase register, p0 or p1, is added to the phase accumulator a0-a2 address bits. these address bits are used to select the destination register for freq/phase/control input data
4 AD9852 product concept mechanical outline 44-lead thin-quad flatpack ic package (tqfp) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) seating plane 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) for further information on the AD9852 contact: jim surber analog devices, inc. 7910 triad center drive greensboro, nc 27410 p 910/605-4365 f 910/605-4347 email jim.surber@analog.com
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