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rev. 0.2 11/10 copyright ? 2010 by silicon laboratories si5350a this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5350a f actory -p rogrammable a ny -f requency cmos c lock g enerator features applications description the si5350a is a user-definable custom cl ock generator that is ideally suited for replacing crystals and crystal oscillators in cost-sensitive applications. based on a pll + high resolution fractional divider multisynth tm architecture, the si5350a can generate any frequency up to 125 mhz on each of its outputs with 0 ppm error. spread spectrum is selectable (on/off) on any of the outputs. custom pin- controlled si5350a devices can be requested using the clockbuilder web-based part number utility ( www.silabs.com/clockbuilder ). functional block diagram ? generates up to 8 non-integer frequencies from 8 khz to 125 mhz ? exact frequency synthesis at each output (0 ppm error) ? glitchless frequency changes ? low output period jitter: 100 ps pp ? configurable spread spectrum selectable at each output ? user-configurable control pins: ?? output enable (oeb_0/1/2) ?? power down (pdn) ?? frequency select (fs_0/1) ?? spread spectrum enable (ssen) ? operates from a low-cost, fixed frequency crystal: 25 or 27 mhz ? separate voltage supply pins: ?? core vdd: 2.5 v or 3.3 v ?? output vddo: 2.5 v or 3.3 v ? excellent psrr eliminates external power supply filtering ? very low power consumption (<15 ma) ? available in 3 packages types: ?? 10-msop: 3 outputs ?? 24-qsop: 8 outputs ?? 20-qfn (4x4 mm): 8 outputs ? hdtv, dvd/blu-ray, set-top box ? audio/video equipment, gaming ? printers, scanners, projectors ? residential gateways ? networking/communication ? servers, storage si5350a clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 p0 p1 p2 p3 p4 control logic multi synth 0 multi synth 1 multi synth 2 multi synth 3 multi synth 4 multi synth 5 multi synth 6 multi synth 7 20-qfn, 24-qsop osc xa xb plla pllb si5350a clk0 clk1 clk2 p0 p1 control logic multi synth 0 multi synth 1 multi synth 2 10-msop osc xa xb plla pllb ordering information: see page 18 20-qfn 24-qsop 10-msop
si5350a 2 rev. 0.2
si5350a rev. 0.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. configuring the si5350a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1. crystal inputs (xa, xb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2. output clocks (clk0?clk7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.3. programmable control pi ns (p0?p4) options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. pin descriptions (20-pin qf n, 24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. pin descriptions (10-pin msop ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. package outline (24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8. package outline (20-pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9. package outline (10-pin msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
si5350a 4 rev. 0.2 1. electrical specifications table 1. recommended operating conditions (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit ambient temperature t a ?402585c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v output buffer voltage v ddox 2.25 2.5 2.75 v 2.97 3.3 3.63 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. absolute maximum ratings parameter symbol test condition value unit dc supply voltage v dd_max ?0.5 to 3.8 v input voltage v in_p1-4 pins p1, p2, p3, p4 ?0.5 to 3.8 v v in_p0 p0 ?0.5 to (v dd +0.3) v v in_xa/b pins xa, xb ?0.5 to 1.3 v v storage temperature range t stg ?55 to 150 c operating junction temperature t jct ?55 to 150 c note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. dc characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit core supply current i dd enabled 3 outputs ? 20 26 ma enabled 8 outputs ? 25 38 ma power down (pdn = v dd )? 50 ? a output buffer supply current i ddox c l =5pf ? 2.5 4 ma input current i p1-p4 pins p1, p2, p3, p4 vin < 3.6v ??10 a i p0 pin p0 ? ? 30 a
si5350a rev. 0.2 5 table 4. ac characteristics ((v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit power-up time t rdy from v dd =v ddmin to valid out- put clock, c l =15pf, f clkn >1mhz ?110ms output enable time t oe from oeb assertion to valid clock output, c l =15pf, f clkn >1mhz ??10 s output frequency transition time t freq time to settle to within 20 ppm of specified frequency upon change in frequency plan via fs pin, f clkn >1mhz ?100? s minimum pulse width t pw_pdn power down pin (pdn) 100 ? ? ms t pw_p0-4 control pin (p0-p4) 200 ? ? ns spread spectrum frequency deviation ss dev down spread ?0.5 ? ?2.5 % spread spectrum modulation rate ss mod 30 31.5 33 khz table 5. thermal characteristics parameter symbol test cond ition package value unit thermal resistance junction to ambient ? ja still air 10-msop 131 c/w 24-qsop 80 c/w 20-qfn 51 c/w thermal resistance junction to case ? jc still air 10-msop 43 c/w 24-qsop 31 c/w 20-qfn 16 c/w table 6. input characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units crystal frequency f xtal 25 ? 27 mhz p0-p4 input low voltage v il-p0-4 ?0.1 ? 0.3 x v dd v p0-p4 input high voltage v ih_p0-4 0.7 x v dd ?3.63 v
si5350a 6 rev. 0.2 table 7. output characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units frequency range f clk 0.008 125 mhz load capacitance c l f clk < 100 mhz ? 5 15 pf duty cycle dc measured at v dd /2 45 50 55 % rise/fall time t r /t f 20%?80%, c l = 5 pf 0.6 1 1.3 ns output high voltage v oh v dd ? 0.6 ? ? v output low voltage v ol ??0.6v period jitter j per measured over 10k cycles ? 35 100 ps pk-pk cycle-to-cycle jitter j cc measured over 10k cycles ? 30 90 ps pk-pk rms phase jitter j rms 12 khz?20 mhz ? 3.5 11 ps rms table 8. 25 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?25?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l ??150w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitors in addition to external 2 pf load capacitors. 2. refer to ?an551: crystal selection guide? for more details. table 9. 27 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?27?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level spec d l ??150w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitors in addition to external 2 pf load capacitors. 2. refer to ?an551: crystal selection guide? for more details.
si5350a rev. 0.2 7 2. typical application the si5350a is a user-definable custom clock generator that is ideally suited for replacing crystals and crystal oscillators in cost-sensitive applications. an example application is shown in figure 1. figure 1. example of an si5350a in an audio/video application video processor audio processor 74.25 mhz or 74.25 1.001 mhz 24.576 mhz 27 mhz hdmi port 22.5792 mhz ethernet phy usb controller 28.322 mhz 48 mhz 125 mhz clk4 clk0 27 mhz xa xb cpu 33.3333 mhz clk1 clk3 clk7 clk6 clk2 clk5 si5350a
si5350a 8 rev. 0.2 3. functional description the si5350a?s synthesis architecture consists of two high-frequency plls in addition to one high-resolution fractional multisynth tm divider per output. a block diagram of both th e 3-output and 8-output versions are shown in figure 2. this unique architecture allows the si5350a to generate up to eight independent, non-integer-related frequencies at any of its outputs. each multisynth tm is configurable with two freq uencies (f1_x, f2_x). this allows a pin controlled glitchless frequency change at each output (clk0 to clk5). figure 2. block diagrams of 3-output and 8-output si5350a devices 10-msop multisynth 3 f1_2 f2_2 r2 fs multisynth 2 vdd gnd clk2 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddo pll a pll b osc xa xb f1_3 f2_3 r3 fs multisynth 3 f1_2 f2_2 r2 fs multisynth 2 20-qfn, 24-qsop pll a pll b vdd gnd clk2 clk3 vddob control logic p2 p3 p4 p0 p1 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddoa r6 r7 clk6 clk7 vddod f1_4 f2_4 r4 fs multisynth 4 f1_5 f2_5 r5 fs multisynth 5 clk4 clk5 vddoc f1_6 multisynth 6 f1_7 multisynth 7 osc xa xb control logic p0 p1
si5350a rev. 0.2 9 4. configuring the si5350a the si5350a is a factory-programmed custom clock genera tor that is user definable with a simple to use web- based utility ( www.silabs.com/clockbuilder ). the clockbuilder utility provides a simple graphi cal interface that allows the user to enter input and output frequencies along with other custom features as described in the following sections. all synthesis calculations are automatically performed by clockbuilder to ensure an optimum configuration. a unique part number is assigned to each custom configuration. 4.1. crystal inputs (xa, xb) the si5350a uses a fixed-frequency standard at-cut crystal as a reference to synthesize its output clocks. 4.1.1. crystal frequency the si5350a can operate using either a 27 mhz or a 25 mhz crystal. 4.1.2. internal xtal load capacitors internal load capacitors (c l ) are provided to eliminate the need for external components when connecting a xtal to the si5350a. options for internal load capacitors are 6, 8, or 10 pf, or no internal load capacitors. xtals with alternate load capacitance requirements are supported us ing external load capacitors as shown in figure 3. figure 3. external xtal with optional load capacitors 4.2. output clocks (clk0?clk7) the si5350a is orderable as a 3-output (10-msop) or 8- output (24-qsop, 20-qfn) clock generator. output clocks clk0 to clk5 can be ordered with two clock frequencies (f1_x, f2_x) which are selectable with the optional frequency select pins (fs0/1). see ?4.3.3. frequency select (fs_0, fs_1)? for more details on the operation of the frequency select pins. 4.2.1. output clock frequency outputs can be configured at any frequency from 8 khz up to 100 mhz. in addition, the device can generate any frequency up to 125 mhz on two of its outputs. 4.2.2. . spread spectrum spread spectrum can be enabled on any of the clock outputs for reducing electromagnetic interference (emi). enabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. up to ?15 db reduction in emi is possible. the si5350a supports several levels of spread spectrum allowing the designer to chose an ideal compromise between system performance and emi compliance. the amount of spread is configurable within the following parameters: ? down spread: ?0.5 to ?2 .5% modulation amplitude an optional spread spectrum enable pin (ssen) is configur able to enable or disable the spread spectrum feature. see ?4.3.1. spread spectrum enable (ssen)? for details. xa xb optional internal load capacitors 6pf, 8pf, 10pf c l c l c l optional external load capacitors c l
si5350a 10 rev. 0.2 figure 4. available spread spectrum profiles 4.2.3. invert/non-invert by default, each of the output clocks are generated in ph ase (non-inverted) with respect to each other. an option to invert any of the clock outputs is also available. 4.2.4. output state when disabled there are up to three output enable pins configurable on the si5350a as described in ?4.3.4. output enable (oeb_0, oeb_1, oeb_2)? . the output state when disabled for each of the outputs is configurable as one of the following: disable low, disable hi gh, or disable in high-impedance. 4.2.5. powering down unused outputs unused clock outputs can be completely powered down to conserve power. 4.3. programmable cont rol pins (p0?p4) options up to five programmable control pins (p0-p4) are configur able allowing direct pin cont rol of the following features: 4.3.1. spread spec trum enable (ssen) an optional control pin allows disabling the spread spec trum feature for all outputs that were configured with spread spectrum enab led. hold ssen low to disa ble spread spectrum. the ssen pin provides a convenient method of evaluating the effect of using spre ad spectrum clocks during emi compliance testing. 4.3.2. power down (pdn) an optional power down control pin allows a full shutdown of the si5350a to minimize power consumption when its output clocks are not being used. the si5350a is in normal operation when the pdn pin is held low and is in power down mode when held high. power consumption when the device is in power down mode is indicated in table 3 on page 4. 4.3.3. frequency select (fs_0, fs_1) the si5350a offers the option of configuring up to two fr equencies per clock output on clk0-clk5. this is a useful feature for applications that need to support more than on e clock rate on the same output. an example of this is shown in figure 5 where the fs pins selects which fr equency is generated from the clock output: f1_0 is generated when fs is set low, and f2_0 is generated when fs is set high. figure 5. example of generating two clock frequencies from the same clock output f c reduced amplitude and emi down spread spread amount - 0.5% to - 2.5% f c no spread spectrum center frequency amplitude video processor 27 mhz xa xb clk0 fs0 si5350a 74.25 74.25 1.001 mhz or mhz output frequency selected fs0 bit level 0 1 74.25 mhz f1_0: f2_0: 74.25 1.001 mhz
si5350a rev. 0.2 11 up to two frequency select pins are available on the si53 50a. each of the frequency select pins can be linked to any of the clock outputs as shown in figure 6. for example, fs_0 can be linked to control clock frequency selection on clk0, clk3, and clk5; fs_1 can be used to control clock frequency selection on clk1, clk2, and clk4. any other combinat ion is also possible. the si5350a uses control circuitry to ensure that frequen cy changes are glitchless. this ensures that the clock always completes its last cycle before starting a new clock cycle of a different frequency. figure 6. example configuration of a pin-controlled frequency select (fs) 4.3.4. output enable (oeb_0, oeb_1, oeb_2) up to three output enable pins (oeb_0/1/2) are available on the si5350a. similar to the fs pins, each oeb pin can be linked to any of the outpu t clocks. in the example shown in figure 7, oeb_0 is linked to control clk0, clk3, and clk5; oeb_1 is linked to contro l clk6 and clk7, and oeb_2 is linke d to control clk1, clk2, clk4, and clk5. any other combination is also po ssible. if more than one oeb pin is linked to the same clk output, the pin forcing a disable state will be do minant. clock outputs are enabled when the oeb pin is held low. the output enable control circuitry ensures glitchless operati on by starting the output clock cycle on the first leading edge after oeb is asserted (oeb = low). when oeb is rele ased (oeb = high), the clock is allowed to complete its full clock cycle before going into a disabled state. this is shown in figure 7. when disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance. figure 7. example configuration of a pin-controlled output enable clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 fs_0 fs_1 fs_0 0 1 f1_0, f1_3, f1_5 f2_0, f2_3, f2_5 output frequency fs_1 0 1 f1_1, f1_2, f1_4 output frequency clkx frequency_a frequency_b full cycle completes before changing to a new frequency frequency_a new frequency starts at its leading edge glitchless frequency changes cannot be controlled by fs pins customizable fs control f2_1, f2_2, f2_4 multisynth 0 fs multisynth 1 fs multisynth 2 fs multisynth 3 fs multisynth 4 fs multisynth 5 fs clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 oeb_0 oeb_1 oeb_0 0 1 clk enabled clk disabled output state oeb_2 oeb_1 0 1 clk enabled clk disabled output state oeb_2 0 1 clk enabled clk disabled output state clock continues until cycle is complete clkx oebx clock starts on the first leading edge glitchless output enable customizable oeb control oeb oeb oeb oeb oeb oeb oeb oeb
si5350a 12 rev. 0.2 4.4. design considerations the si5350a is a self-contained clock generator that requires very few external components. the following general guidelines are recommended to ensure optimum performance. 4.4.1. power supply decoupling/filtering the si5350a has built-in power supply f iltering circuitry to help keep the number of external components to a minimum. all that is recommended is one 0.1 f decouplin g capacitor per power supply pin. this capacitor should be mounted as close to the vdd and vddo pins as possible without using vias. 4.4.2. power supply sequencing the vdd and vddox (i.e., vddo0, v ddo1, vddo2, vddo3) power supply pins have been separated to allow flexibility in output signal le vels. it is important that po wer is applied to all supply pins (vdd, vddox) at the same time. unused vddox pins should be tied to vdd. 4.4.3. external crystal the external crystal should be mounted as close to th e pins as possible using short pcb traces. the xa and xb traces should be kept away from other high-speed signal traces. see ?an5 51: crystal selection guide? for more details. 4.4.4. external crystal load capacitors the si5350a provides the option of using internal and exte rnal crystal load capacitors. if external load capacitors are used, they should be placed as close to the xa/xb pads as possible. see ?an551: crystal selection guide? for more details. 4.4.5. unused pins unused control pins (p0?p4) should be tied to gnd. unused output pins (clk0?clk7) should be left floating.
si5350a rev. 0.2 13 5. pin descriptions (2 0-pin qfn, 24-pin qsop) pin name pin number pin type* function 20-qfn 24-qsop xa 1 6 i input pin for external xtal xb 2 7 i input pin for external xtal clk0 13 21 o output clock 0 clk1 12 20 o output clock 1 clk2 9 15 o output clock 2 clk3 8 14 o output clock 3 clk4 19 3 o output clock 4 clk5 17 1 o output clock 5 clk6 16 24 o output clock 6 clk7 15 23 o output clock 7 p0 3 9 i user configurable input pin 0. see 4.4.5. p1 4 10 i user configurable input pin 1. see 4.4.5. p2 5 11 i user configurable input pin 2. see 4.4.5. p3 6 12 i user configurable input pin 3. see 4.4.5. p4 7 13 i user configurable input pin 4. see 4.4.5. vdd 20 4 p core voltage supply pin. see 4.4.2 vddoa 11 18 p output voltage supply pin for clk0 and clk1. see 4.4.2 vddob 10 16 p output voltage supply pin for clk2 and clk3. see 4.4.2 vddoc 18 2 p output voltage supply pin for clk4 and clk5. see 4.4.2 vddod 14 22 p output voltage supply pin for clk6 and clk7. see 4.4.2 gnd center pad 5, 8, 17, 19 p ground *note: i = input, o = output, p = power 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 xa xb p0 p1 p2 p4 clk3 clk2 vddob p3 gnd pad si5350a 20-qfn (top view) clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7 2 1 4 3 6 5 8 7 10 9 12 11 23 24 21 22 19 20 17 18 15 16 13 14 si5350a 24-qsop (top view) clk7 clk6 clk0 vdd0d gnd clk1 gnd vddoa clk2 vdd0b p4 clk3 vddoc clk5 vdd clk4 xa gnd gnd xb p1 p0 p3 p2
si5350a 14 rev. 0.2 6. pin descriptio ns (10-pin msop) pin name pin number pin type* function 10-msop xa 2 i input pin for external xtal xb 3 i input pin for external xtal clk0 10 o output clock 0 clk1 9 o output clock 1 clk2 6 o output clock 2 p0 4 i user configurable input pin 0 p1 5 i user configurable input pin 1 vdd 1 p core voltage supply pin. see 4.4.2 vddo 7 p output clock voltage supply pin for clk0, clk1, and clk2. see 4.4.2 gnd 8 p ground *note: i = input, o = output, p = power xa vdd p0 xb 2 1 4 3 clk1 clk0 vddo gnd 9 10 7 8 p1 5 clk2 6 si5350a 10-msop top view
si5350a rev. 0.2 15 7. package outline (24-pin qsop) table 10. 24-qsop package dimensions dimension min nom max a??1.75 a1 0.10 ? 0.25 b 0.19 ? 0.30 c 0.15 ? 0.25 d 8.558.658.75 e 6.00 bsc e1 3.81 3.90 3.99 e 0.635 bsc l 0.40 ? 1.27 l2 0.25 bsc q0?8 aaa 0.10 bbb 0.17 ccc 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5350a 16 rev. 0.2 8. package outline (20-pin qfn) table 11. package dimensions dimension min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 4.00 bsc d2 2.65 2.70 2.75 e 0.50 bsc e 4.00 bsc e2 2.65 2.70 2.75 l 0.300.400.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components. ?
si5350a rev. 0.2 17 9. package outline (10-pin msop) table 12. 24-qsop package dimensions dimension min nom max a??1.10 a1 0.00 ? 0.15 a2 0.75 0.85 0.95 b 0.17 ? 0.33 c 0.08 ? 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.400.600.80 l2 0.25 bsc q0?8 aaa ? ? 0.20 bbb ? ? 0.25 ccc ? ? 0.10 ddd ? ? 0.08 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components. ?
si5350a 18 rev. 0.2 10. ordering information factory programmed si5350a devices c an be requested using the clockbuild er web-based utility available at: www.silabs.com/clockbuilder . a unique part number is assigned to each custom configuration as indicated in figure 8. figure 8. custom clock part numbers a development kit containing clockbuild er desktop software and hardware allows easy customization of blank si5350a devices with a user defined configuration. in ad dition to field programming, this development kit supports simplified device evaluation of any si 5350a device. the ordering part number s for the development kits and blank si5350a devices to be used for field programming are shown in figure 9 and figure 10, respectively. figure 9. development kit part numbers figure 10. blank device part numbers si5350a axxxxx xx gt - 10-msop gm - 20-qfn gu ? 24-qsop a = product revision a xxxxx = unique custom code. a five character code will be assigned for each unique custom configuration si535x evb xxxxxx evb = device and field programming kit xxxxxx = 20qfn 24qsop si5350a a xx gt - 10-msop gm - 20-qfn gu ? 24-qsop a = product revision a ? blank device
si5350a rev. 0.2 19 n otes :
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