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ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 16 features ? high performance: ? single pulsed ras interface ? fully synchronous to positive clock edge ? four banks controlled by bank selects ? programmable burst length: 1, 2, 4, 8, full-page; ? programmable cas latency: 3 ? programmable wrap: sequential or interleave ? multiple burst read with single write option ? automatic and controlled precharge command ? data mask for read/write control ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? standard power operation ? 4096 refresh cycles/64ms ? random column address every clk (1-n rule) ? single 3.3v 0.3v power supply ? lvttl compatible ? package: 54-pin 400 mil tsop-type ii 54-pin 2 high stack tsoj description the ibm0364404ct3 is a four-bank 64mb synchro- nous dram organized as 4mbit x 4 i/o x 4 bank. ibm03644b4ct3 is a stacked version of the 64mb, x 4 component. this datasheet provides timing information for the 133 mhz performance sort for this synchronous device. for the complete functional description and timing diagrams refer to the datasheet 19l3264. -75a, cl=3 units f ck clock frequency 133 mhz t ck clock cycle 7.5 ns t ac clock access time 5.4 ns t rp precharge time 20 ns t rcd ras to cas delay 20 ns t rc bank cycle time 67.5 ns discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 16 46l8543.f46205 7/99 pin assignments for planar components (top view) 54-pin plastic tsop(ii) 400 mil 4mbit x 4 i/o x 4 bank ibm0364404ct3 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc v dd nc nc nc we cas ras cs a13/bs0 a12/bs1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc v ss nc nc nc dqm clk cke nc a11 a9 23 24 25 32 31 30 a10/ap a0 a1 a2 a8 a7 a6 a5 26 27 29 28 a3 v dd a4 v ss discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 16 pin assignments for 2 high stack package (dual cs pin) (top view) 54-pin plastic tsoj(ii) 400 mil (4mbit x 4 i/o x 4 bank) x 2high ibm03644b4ct3 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 v dd nc v ddq nc dq0 v ssq v ddq nc dq1 v ssq nc v dd nc nc nc we cas ras cs0/nc a13/bs0 a12/bs1 v ss nc v ssq nc dq3 v ddq v ssq nc dq2 v ddq nc v ss nc nc nc dqm clk cke nc/ cs1 a11 a9 23 24 25 32 31 30 a10/ap a0 a1 a2 a8 a7 a6 a5 26 27 29 28 a3 v dd a4 v ss * cs0 selects the lower dram in the stack. * cs1 selects the upper dram in the stack. discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 16 46l8543.f46205 7/99 pin description clk clock input dq0-dq3 data input/output cke clock enable dqm data mask cs (2high stack: cs0, cs1) chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+3.3v) we write enable v ssq ground for dqs bs1, bs0 bank select nc no connection a0-a11 address inputs input/output functional description symbol type polarity function clk input positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input active high cke activates the clk signal when high and deactivates the clk signal when low. by deacti- vating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs, cs0, cs1 input active low cs ( cs0, cs1 for stacked devices) enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas, we input active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. bs1, bs0 input selects which bank is to be active. a0 - a11 input during a bank activate command cycle, a0-a11 defines the row address when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address when sampled at the rising clock edge. a10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. if a10 is high, auto-precharge is selected and bs0, bs1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with bs0, bs1 to control which bank(s) to precharge. if a10 is high, all banks will be precharged regardless of the state of bs. if a10 is low, then bs0 and bs1 are used to define which bank to precharge. dq0-dq3 input- output data input/output pins operate in the same manner as on conventional drams. dqm input active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. dqm low turns the output buffers on and dqm high turns them off. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. v dd , v ss supply power and ground for the input buffers and the core logic. v ddq , v ssq supply isolated power supply and ground for the output buffers to provide improved noise immunity. discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 16 ordering information - planar devices (single cs pin) part number cas latencies power supply clock cycle package org. IBM0364404CT3B-75A 3 3.3v 7.5ns 400mil type ii tsop-54 x4 ordering information - 2 high stacked devices (dual cs pin) part number cas latencies power supply clock cycle package org. ibm03644b4ct3b-75a 3 3.3v 7.5ns 400mil type ii tsoj-54 x4 discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 16 46l8543.f46205 7/99 command truth table (see note 1) function device state cke cs ras cas we dqm bank selects a10 address notes previous cycle current cycle mode register set idle h x l l l l x op code auto (cbr) refresh idle h h l l l h x x x x entry self refresh idle h l l l l h x x x x exit self refresh idle (self- refresh) lh hxxx xxxx lhhh single bank precharge see current state table hxllhlxbslx2 precharge all banks see current state table hxllhlxxhx bank activate idle h x l l h h x bs row address 2 write active h x l h l l x bs l column 2 write with auto-precharge active h x l h l l x bs h column 2 read active h x l h l h x bs l column 2 read with auto-precharge active h x l h l h x bs h column 2 burst termination active h x l h h l x x x x 3, 8 no operation any h x l h h h x x x x device deselect any h x h x x x x x x x clock suspend mode entry active h l x x x x x x x x 4 clock suspend mode exit active l h x x x x x x x x data write/output enable active h x x x x x l x x x 5 data mask/output disable active h x x x x x h x x x power down mode entry idle/active h l hxxx x x x x 6, 7 lhhh power down mode exit any (power down) lh hxxx x x x x 6, 7 lhhh 1. all of the sdram operations are defined by states of cs, we, ras, cas, and dqm at the positive rising edge of the clock.oper- ation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. refer to the current state truth table. 2. bank select (bs0, bs1): bs0, bs1 = 0,0 selects bank 0; bs0, bs1 = 0,1 selects bank 1; bs0, bs1 = 1,0 selects bank 2; bs0, bs1 = 1,1 selects bank 3. 3. during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4. during normal access mode, cke is held high and clk is enabled. when it is low, it freezes the internal clock and extends dat a read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes high at a clock tim- ing the data outputs are disabled and become high impedance after a two clock delay. dqm also provides a data mask function for write cycles. when it activates, the write operation at the clock is prohibited (zero clock latency). 6. all banks must be precharged before entering the power down mode.(if this command is issued during a burst operation, the device state will be clock suspend mode.)the power down mode does not perform any refresh operations, therefore the device cant remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. 7. a no operation or device deselect command is required on the next clock edge following cke going high. 8. device state is full page burst operation. use of this command to terminate other burst length operations is illegal. discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 16 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v 1 v ddq power supply voltage for output -0.3 to +4.6 v 1 v in input voltage -0.3 to v dd +0.3 v1 v out output voltage -0.3 to v dd +0.3 v1 t a operating temperature (ambient) 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a = 0 to 70 c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ddq supply voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v 1, 2 v il input low voltage -0.3 0.8 v 1, 3 1. all voltages referenced to v ss and v ssq . 2. v ih (max) = v dd /v ddq + 1.2v for pulse width 5ns. 3. v il (min) = v ss /v ssq - 1.2v for pulse width 5ns . capacitance (t a = 25 c, f = 1mhz, v dd = 3.3v 0.3v) symbol parameter min. typ. max. units notes c i input capacitance (a0-a11, bs0, bs1, cs, ras, cas, we, cke, dqm) 2.5 2.9 3.8 pf 1 input capacitance (clk) 2.5 3.2 3.5 c o output capacitance (dq0 - dq3) 4.0 5.4 6.5 1. multiply given planar values by 2 for 2-high stacked device except cs. discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 16 46l8543.f46205 7/99 dc electrical characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) symbol parameter min. max. units notes i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v -1 +1 m a 1 i o(l) output leakage current (d out is disabled, 0.0v v out v ddq ) -1 +1 m a 1 v oh output level (lvttl) output h level voltage ( iout = -2.0ma) 2.4 v v ol output level (lvttl) output l level voltage (i out = +2.0ma) 0.4 v 1. multiply given planar values by 2 for 2-high stacked device. operating, standby, and refresh currents (t a = 0 to +70 c, v dd = 3.3v 0.3v) parameter symbol test condition speed -75a units notes operating current i cc1 1 bank operation t rc = t rc (min), t ck = min active-precharge command cycling without burst operation 75 ma 1, 2, 3 precharge standby current in power down mode i cc2p cke v il (max), t ck = min, cs =v ih (min) 1ma1 i cc2ps cke v il (max), t ck = infinity, cs =v ih (min) 1ma1 precharge standby current in non-power down mode i cc2n cke 3 v ih (min), t ck = min, cs =v ih (min) 35 ma 1, 5 i cc2ns cke 3 v ih (min), t ck = infinity, 5 ma 1, 7 no operating current (active state: 4 bank) i cc3n cke 3 v ih (min), t ck = min, cs =v ih (min) 40 ma 1, 5 i cc3p cke v il (max), t ck = min 7 ma 1, 6 operating current (burst mode) i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data,bl=4 120 ma 1, 3, 4 auto (cbr) refresh current i cc5 t ck = min, t rc = t rc (min) cbr command cycling 145 ma 1 self refresh current i cc6 cke 0.2v 1ma1 1. currents given are valid for a single device. the total current for a stacked device depends on the operation being performed on the other deck. 2. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to three times during t rc (min). 3. the speci?ed values are obtained with the output open. 4. input signals are changed once during t ck (min). 5. input signals are changed once during three clock cycles. 6. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 7. input signals are stable. discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 16 ac characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) 1. see full specification (19l3264) for power-up requirements. 2. the transition time is measured between v ih and v il (or between v il and v ih ). 3. in addition to meeting the transition rate speci?cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.40v crossover point 5. ac measurements assume t t = 1.2ns. ac characteristics diagram clock and clock enable parameters symbol parameter -75a units notes min. max. t ck3 clock cycle time, cas latency = 3 7.5 1000 ns t ck2 clock cycle time, cas latency = 2 ns t ac3 clock access time, cas latency = 3 5.4 ns 1 t ac2 clock access time, cas latency = 2 ns 1 t ckh clock high pulse width 2.5 ns t ckl clock low pulse width 2.5 ns t ces clock enable set-up time 1.5 ns t ceh clock enable hold time 0.8 ns t sb power down mode entry time 0 7.5 ns t t transition time (rise and fall) 0.5 10 ns 1. access time is measured at 1.4v. output input clock t oh t setup t hold t ac t lz 1.4v 1.4v 1.4v t t t ckh t ckl output 50pf z o = 50 w ac output load circuit v il v ih discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 16 46l8543.f46205 7/99 common parameters symbol parameter -75a units notes min. max. t cs command setup time 1.5 ns t ch command hold time 0.8 ns t as address and bank select set-up time 1.5 ns t ah address and bank select hold time 0.8 ns t rcd ras to cas delay 20 ns 1 t rc bank cycle time 67.5 ns 1 t ras active command period 45 100k ns 1 t rp precharge time 20 ns 1 t rrd bank to bank delay time 15 ns 1 t ccd cas to cas delay time 1 clk 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). mode register set cycle symbol parameter -75a units notes min. max. t rsc mode register set cycle time 2 clk 1 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 16 read cycle symbol parameter -75a units notes min. max. t oh data out hold time 2.7 ns 1 t lz data out to low impedance time 0 ns t hz data out to high impedance time 3 5.4 ns 2 t dqz dqm data out disable latency 2 clk 1. data out hold time with no load must meet 1.8ns. 2. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle symbol parameter -75a units min. max. t ref refresh period 64 ms t rfc row refresh cycle time 75 ns t srex self refresh exit time 10 ns write cycle symbol parameter -75a units min. max. t ds data in set-up time 1.5 ns t dh data in hold time 0.8 ns t dpl data input to precharge 2 clk t dal data input to activate 5 clk t dqw dqm write mask latency 0 clk discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 16 46l8543.f46205 7/99 clock frequency and latency symbol parameter -75a units f ck clock frequency 133 mhz t ck clock cycle time 7.5 ns t aa cas latency 3 clk t rp precharge time 3 clk t rcd ras to cas delay 3 clk t rc bank cycle time 9 clk t ras minimum bank active time 6 clk t dpl data in to precharge 2 clk t dal data in to active 5 clk t rrd bank to bank delay time 2 clk t ccd cas to cas delay time 1 clk t wl write latency 0 clk t dqw dqm write mask latency 0 clk t dqz dqm data disable latency 2 clk t csl clock suspend latency 1 clk discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 16 package dimensions (400mil; 54 lead; thin small outline package) lead #1 0.80 basic 0.35 10.16 0.13 22.22 0.13 11.76 0.20 - 0.05 + 0.10 0.805ref detail a 0.10 seating plane detail a 0.5 0.1 0.05 min 1.20 max 0.25 basic gage plane discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 16 46l8543.f46205 7/99 stack package dimensions (400mil; 54 lead; 2 high stack; thin small outline j lead package) 0.75 min 3.20 max 9.90 0.40 lead #1 0.80 basic 0.30 10.15 0.05 22.22 0.28 11.4 0.25 - 0.04 + 0.10 0.10 seating plane 0.50 - 0.04 + 0.13 discontinued (8/99 - last order; 12/99 - last ship)
ibm0364404 ibm03644b4 pc133 synchronous dram - 64mb revision b 46l8543.f46205 7/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 16 revision log revision contents of modi?cation 1/14/99 initial release. 3/1/99 remove - 75d, 64mb rev c, and 256mb rev a. 3/21/99 change t rp , t rcd for -75a (22.5 to 20ns). 7/99 removed preliminary. discontinued (8/99 - last order; 12/99 - last ship)
intern ational business machines corp.1999 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (8/99 - last order; 12/99 - last ship)

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