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? semiconductor components industries, llc, 2005 december, 2005 ? rev. 6 1 publication order number: NCP1603/d NCP1603 pfc/pwm combo controller with integrated high voltage startup and standby capability the NCP1603 is a power factor correction (pfc) and pulse width modulation (pwm) combo controller. it offers extremely low no?load standby power consumption that is suitable for the low?power consumer markets. the key features of the device are listed below. pfc features ? near?unity power factor in discontinuous and critical mode (dcm and crm) ? voltage?mode operation ? low startup and shutdown current consumption ? programmable switching frequency for dcm ? synchronization capability ? overvoltage protection (107% of nominal output level) ? undervoltage protection or shutdown (8% of nominal output level) ? programmable overcurrent protection ? thermal shutdown with hysteresis (95/140 c) ? undervoltage lockout with hysteresis (9.0/10.5 v) pwm features ? integrated lossless high voltage startup current source ? 100 khz pwm current?mode operation with skipping cycle capability during standby condition ? pfc bias voltage is disabled in standby condition to achieve extremely low no?load standby power consumption ? fault protection implemented by a timer and independent of badly coupled auxiliary transformer winding ? primary overcurrent protection and latched overvoltage protection ? internal 2.5 ms soft?start ? 6.4% frequency jittering for improved emi performance ? latched thermal shutdown with hysteresis (140/165 c) ? undervoltage lockout with hysteresis (5.6/7.7/12.6 v) applications ? notebook adapters ? tv/monitors http://onsemi.com so?16 d suffix case 751b device package shipping ? ordering information NCP1603d100r2 so?16 2500 tape & reel marking diagram a = assembly location wl = wafer lot y = year ww = work week 1 16 1603d100 awlyww 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) osc v aux fb2 cs2 gnd2 gnd1 out1 v cc1 hv nc ramp cs1 fb1 v cc2 v control 13 out2 pin connections ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. 1
NCP1603 http://onsemi.com 2 ac input emi filter NCP1603 ovp outpu t voltage + ? figure 1. t ypical application circuits ac i nput emi filter NCP1603 ovp outpu t voltag e + ? not synchronized and v cc ovp latch implemented synchronized and output ovp latch implemented
NCP1603 http://onsemi.com 3 i s uvlo current mirror fb1 cs1 regulation block current mirror out1 gnd1 ramp pfc osc thermal shutdown pwm ? leb 125 ms 2.5 ms softstart cs2 fb2 oscillator 100 khz 125 ms delay hv s q r 3v ovp out2 gnd2 pwm standby or 5v 1v max 18k 55k 20k 25k fault?2 0.75v 0.75v/ 1.25v fault?2 or 300k or 5ms jittering zero current protection overcurrent protection overvoltage shutdown / uvp delay max duty r q s = 80% 200ns (9 / 10.5v) voltage regulator internal bias fb1 ref ref reg v i i 96%i (12.6 / 7.7v) (5.6 / 4v) 1 0 0~2.3v ramp 100 khz 5ms jittering r s q & & s r q 1 0 s r q & start_vaux start_vaux 3.9v max clamp & + ? + ? + ? + ? + ? + 11 9 5 16 8 2 3 4 1 6 7 12 10 14 13 10v 10v 9v 9v 18v 20v 9v 9v thermal shutdown ? + 5/ 3.5 v r q s 0 1 delay 9 v detection & 3.2ma 0 1 + ? clock disable initially error fault?1 vaux internal bias pfc modulation & v cc1 94 a 45 a (i fb1 < 8% i ref ) i fb1 (i fb1 > 107% i ref ) v cs2 v fb2 v ss (140/165 c) latchoff, reset when v cc2 < 4v disable v aux when v cc2 < 7.7v v cc2 mgmt v cc2 v aux v control i ch c 3 c 1 r 1 r 2 r 3 v ton v cc1 (i s > 203 a) (95/140 c) (i s < 14 a) v cc2 figure 2. functional block diagram latchoff, reset when v cc2 < 4v fault?1
NCP1603 http://onsemi.com 4 pin function description pin symbol function description 1 v aux auxiliary supply this pin connects to the v cc1 pin externally. it delivers a bias voltage from the v cc2 to the pfc section. the v aux is disabled when either one of the following conditions occurs: (1) v aux is initially off; (2) fault (v fb2 > 3.0 v for more than 125 ms); (3) standby (v fb2 < 0.75 v and then v fb2 is smaller than 1.25 v for more than 125 ms); (4) overvoltage protection latch activated from cs2 pin; (5) thermal shutdown latch in the pwm section; (6) insufficient supply voltage (v cc2 < 7.7 v). the transistor turns on (or v aux is enabled) when v fb2 is within the normal mode regulation window (0.75 v < v fb2 < 3.0 v). 2 fb2 pwm feedback an external optocoupler collector pulls the voltage of this pin v fb2 down to regulate the output voltage. the pwm regulation window between v fb2 = 0.75 v and v fb2 = 3.0 v. when v fb2 drops below 0.75 v, the controller enters standby operation. when no feedback signal is received from the optocoupler, v fb2 is internally pulled to be higher than 3.0 v. if this condition lasts for longer than 125 ms, the controller enters double?hiccup fault condition. 3 cs2 pwm current sense this pin cumulates three different functions: current?mode pwm regulation, primary overcurrent protection and overvoltage protection (ovp). if the voltage of this pin is above 3.0 v for ovp, the circuit is latched off until v cc2 resets. the pwm drive output is disabled. an external noise decoupling pf?order capacitor is connected to the pin to prevent the latch protection activated due to noise. 4 gnd2 pwm ground ? 5 osc pfc oscillator in oscillator mode, this pin is connected to an external capacitor to set the oscillator frequency in dcm operation. in synchronization mode, this pin is connected to an external driving signal. however, if the pfc?stage inductor current is non?zero at the end of a switching period, the pfc?stage circuit will be forced to crm and the out1 is out of synchronization to the osc pin signal. 6 gnd1 pfc ground ? 7 out1 pfc drive output this pin provides an output to an external mosfet in the pfc section. 8 v cc1 pfc supply voltage this pin is the positive supply of the pfc section. the operating range is between 9.0 v and 18 v with uvlo start threshold 10.5 v. 9 fb1 pfc feedback this pin receives a current i fb1 that represents the pfc circuit output voltage. the current is for the output regulation, pfc section overvoltage protection (ovp) and pfc section output undervoltage protection (uvp). when i fb1 goes above 107% i ref , ovp is activated and the drive output is disabled. when i fb1 goes below 14 a, the pfc section enters a low?current consumption shutdown mode. 10 v control pfc control voltage the control voltage v control directly controls the input impedance and hence the power factor of the circuit. this pin is connected to an external capacitor to limit the control voltage bandwidth typically below 20 hz to achieve power factor correction purpose. 11 cs1 pfc current sense this pin receives a current i s that is proportional to the inductor current. the current is for overcurrent protection (ocp), and zero current detection. when i s goes above 200 a, ocp is activated and the drive output (out1) is disabled. when i s goes below 14 a, it is recognized to be a zero current for feedback regulation and dcm or crm operation in the pfc oscillator section. 12 ramp pfc ramp this pin is connected to an external capacitor to set a ramp signal. the capacitor value directly affects the input impedance of the pfc circuit and its maximum input power. 13 out2 pwm drive output this pin provides an output to an external mosfet in the pwm section. 14 v cc2 pwm supply v oltage this pin is basically the positive supply of the pwm section. it is also the positive supply of the whole device because the pfc section is also supplied from this pin indirectly through v aux pin (pin 1). the operating range is between 7.7 v and 18 v. the circuit resets when v cc2 drops below 4.0 v. 15 nc no connected this pin is for high voltage clearance of the hv pin. 16 hv high v oltage this pin connects to the bulk dc voltage to deliver power to the controller in startup or fault condition. the internal startup circuit is disabled in normal and standby condition for power saving purpose. the uvlo stop and start thresholds of the startup circuit are v cc2 = 12.6 v and v cc2 = 5.6 v.
NCP1603 http://onsemi.com 5 maximum ratings rating symbol value unit v aux pin (pin 1) maximum voltage range maximum continuous current v max i max ?0.3 to +18 35 v ma fb2 and cs2 pin (pins 2?3) maximum voltage range maximum current v max i max ?0.3 to +10 100 v ma ramp, cs1, v control , fb1, and osc pins (pins 5, 9?12) maximum voltage range maximum current v max i max ?0.3 to +9.0 100 v ma out1 pin (pin 7) maximum voltage range maximum current v max i max ?0.3 to +18 ?500 to +750 v ma v cc1 and v cc2 pins (pins 8, 14) maximum voltage range maximum current v max i max ?0.3 to +18 100 v ma out2 pin (pin 13) maximum voltage range maximum current v max i max ?0.3 to +17.5 1.0 v a hv pin (pin 16) maximum voltage range maximum current v max i max ?0.3 to +500 100 v ma power dissipation and thermal characteristics maximum power dissipation (t a = 25 c) thermal resistance, junction?to?air p d r ja 770 111 mw c/w operating junction temperature range t j ?40 to +125 c maximum storage temperature range t stg ?60 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be af fected. 1. this device contains esd protection and exceeds the following tests: pin 1?14: human body model 2000 v per mil?std?883, method 3015. machine model method 200 v. pin 16 is the hv startup of the device and is rated to the maximum rating of the part, or 500 v. 2. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78.
NCP1603 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values, t j = ?40 c to +125 c, v cc2 = 13 v, hv = 30 v, v cc1 = 15 v, v control = 100 nf, ramp = 330 pf, osc = 220 pf unless otherwise specified). characteristic (pwm section) pin symbol min typ max unit pwm oscillator oscillation frequency (t j = 25 c) (note 3) oscillation frequency (t j = 0 c to +125 c) oscillation frequency (t j = ?40 c to +125 c) ? f osc2 93 90 85 100 ? ? 107 110 110 khz oscillator modulation swing, in percentage of f osc2 ? ? ? 6.4 ? % oscillator modulation swing period ? ? ? 5.0 ? ms maximum duty ratio (v cs2 = 0 v, v fb2 = 2.0 v) ? d max 75 80 85 % pwm gate drive gate drive resistor output high (v cc2 = 13 v, out2 = 300 to gnd2) output low (out2 = 1.0 v, v fb2 = 0 v) 13 r oh2 r ol2 6.0 3.0 12.3 7.5 25 18 gate drive rise time from 10% to 90% (out2 = 1.0 nf to gnd2) 13 t r2 ? 40 ? ns gate drive fall time from 90% to 10% (out2 = 1.0 nf to gnd2) 13 t f2 ? 15 ? ns pwm current sense/overvoltage protection maximum current threshold (t j = 25 c) maximum current threshold (t j = ?40 c to +125 c) 3 i limit 0.991 0.96 1.043 ? 1.095 1.106 v soft?start duration ? t ss ? 2.5 ? ms leading edge blacking duration 3 t leb 100 200 350 ns propagation delay from cs detected to turn out2 off ? t delay(cs) ? 90 180 ns overvoltage protection threshold 3 v ovp 2.7 3.0 3.3 v internal compensation ramp (peak?to?peak) (note 4) 3 v comp ? 2.3 ? v internal resistor to ramp (note 4) 3 r comp 9.0 18 36 k pwm standby thresholds/feedback standby thresholds feedback voltage v fb2 to start standby feedback voltage v fb2 to stop standby 2 v stby v stby?out 0.6 1.0 0.75 1.25 0.9 1.5 v v validation time for leaving standby 2 t stby?aux ? 125 ? ms validation time for recognize a fault 2 t fault ? 125 ? ms feedback pin sinking capability (v fb2 = 0.75 v) 2 i fb2 200 235 270 a auxiliary supply v aux mosfet resistance (v cc2 = 13 v, v fb = 2.0 v, v aux = 20 ma sinking) 1 r aux 6.0 11.7 23 pwm thermal shutdown thermal shutdown threshold (note 4) ? t sd2 150 165 ? c thermal shutdown hysteresis ? t h2 ? 25 ? c pwm startup current source high?v oltage current source startup (v cc2 = v cc2(on) ?0.2 v, v fb2 = 2.0 v, hv = 30 v) startup (v cc2 = 0 v, hv = 30 v) leakage (v cc2 = 13 v, hv = 700 v) 16 i hv1 i hv2 i hv3 1.8 1.8 10 3.2 4.4 30 4.2 5.6 80 ma ma a minimum startup voltage (v cc2 = v cc2(on) ?0.2 v, i hv = 0.5 ma) 16 v start(min) ? 20 23 v 3. consult factory for other frequency options. 4. guaranteed by design.
NCP1603 http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values, t j = ?40 c to +125 c, v cc2 = 13 v, hv = 30 v, v cc1 = 15 v, v control = 100 nf, ramp = 330 pf, osc = 220 pf unless otherwise specified). characteristic (pfc section) pin symbol min typ max unit pwm supply section supply v oltage startup threshold, v cc2 increasing minimum operating valley voltage after t urn?on undervoltage lockout threshold voltage, v cc2 decreasing logic reset level 14 v cc2(on) v cc2(off) v cc2(latch) v cc2(reset) 11.6 7.0 5.0 ? 12.6 7.7 5.6 4.0 13.6 8.4 6.2 ? v v v v supply current operating (v cc2 = 13 v, out2 = open, v fb2 = 2.0 v) operating (v cc2 = 13 v, out2 = 1.0 nf to gnd2, v fb2 = 2.0 v) latch?off phase (v cc2 = 6.5 v, v fb2 = 2.0 v) 14 i cc2(op1) i cc2(op2) i cc2(latch) 0.6 1.3 400 1.1 2.2 680 1.8 3.0 1000 ma ma a pfc oscillator oscillator frequency (osc = 220 pf to gnd) 5 f osc1 52 58 64 khz internal capacitance of the oscillator pin 5 c osc(int) ? 36 ? pf maximum oscillator switching frequency 5 f osc1(max) ? 405 ? khz oscillator discharge current (osc = 5.5 v) 5 i odch 40 49 60 a oscillator charge current (osc = 3.0 v) 5 i och 40 45 60 a comparator lower threshold (osc = 220 pf to gnd) (note 5) 5 v sync(l) 3.0 3.5 4.0 v comparator upper threshold (osc = 220 pf to gnd) 5 v sync(h) 4.5 5.0 5.5 v synchronization pulse width for detection 5 t sync(min) 500 ? ? ns synchronization propagation delay 5 t sync(d) ? 371 ? ns pfc gate drive gate drive resistor output high and draw 100 ma out of out1 pin (i source = 100 ma) output low and insert 100 ma into out1 pin (i sink = 100 ma) 7 r oh1 r ol1 5.0 2.0 11.6 7.2 20 18 gate drive rise time from 1.5 v to 13.5 v (out1 = 1.0 nf to gnd) 7 t r1 ? 53 ? ns gate drive fall time from 13.5 v to 1.5 v (out1 = 1.0 nf to gnd) 7 t f1 ? 32 ? ns pfc feedback/overvoltage protection/undervoltage protection reference current 9 i ref 192 203 208 a regulation block ratio 9 i regl /i ref 95 96 97 % vcontrol pin internal resistor 10 r control ? 300 ? k maximum control voltage (i fb1 = 100 a) 10 v control(max) 0.95 1.05 1.15 v feedback pin voltage (i fb1 = 100 a) 9 v fb1?100 ? 3.0 ? v overvoltage protection current ratio 9 i ovp /i ref 104 107 ? % overvoltage protection current threshold 9 i ovp ? 217 225 a undervoltage protection current threshold 9 i uvp /i ref 4.0 8.0 15 % 5. comparator lower threshold is also the synchronization threshold.
NCP1603 http://onsemi.com 8 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values, t j = ?40 c to +125 c, v cc2 = 13 v, hv = 30 v, v cc1 = 15 v, v control = 100 nf, ramp = 330 pf, osc = 220 pf unless otherwise specified). characteristic (pfc section) pin symbol min typ max unit pfc current sense current sense pin offset voltage (i s = 100 a) 11 v s ? 4.0 ? mv overcurrent protection level 11 i s(ocp) 190 203 210 a current sense pin offset voltage at overcurrent level 11 v s(ocp) 0 3.2 20 mv zero current detection level 11 i s(zcd) 9 14 19 a current sense pin offset voltage at zero current level 11 v s(zcd) 0 7.5 20 mv zero current sense resistor (r s(zcd) = v s(zcd) /i s(zcd) ) 11 r s(zcd) ? 0.536 1.0 k pfc ramp charging current (ramp = 0 v) 12 i ch 95 100 105 a maximum power resistance (r power = v control(max) /i ch ) 12 r power 9.5 10 11.5 k internal clamping of voltage v ton ? v ton(max) ? 3.9 ? v internal capacitance of the ramp pin 12 c ramp(int) ? 22 ? pf ramp pin sink resistance (osc = 0 v, ramp = 1.0 ma sourcing) 12 r ramp ? 71.5 ? pfc thermal shutdown thermal shutdown threshold (note 6) ? t sd1 140 170 ? c thermal shutdown hysteresis ? t h1 ? 45 ? c pfc supply section supply v oltage startup threshold (uvlo) minimum voltage for operation after t urn?on uvlo hysteresis 8 v cc1(on) v cc1(off) v h1 9.6 8.25 1.0 10.5 9.0 1.5 11.4 9.75 ? v v v supply current start?up (v cc1 = v cc1(on) ?0.2 v) operating (v cc1 = 15 v, out1 = open, osc = 220 pf) operating (v cc1 = 15 v, out1 = 1.0 nf to gnd1, osc = 220 pf) shutdown (v cc1 = 15 v, i fb = 0 a) 8 i cc1(stup) i cc1(op1) i cc1(op2) i cc1(stdn) ? ? ? ? 17 2.7 3.7 24 40 5.0 5.0 50 a ma ma a 6. guaranteed by design.
NCP1603 http://onsemi.com 9 110 108 106 104 102 100 98 96 94 92 90 ?50 ?25 0 25 50 75 100 125 pwm section oscillat or frequency (khz ) t j , junction temperature ( c) figure 3. pwm section oscillator frequency vs. temperature 10 8 6 4 2 0 ?50 ?25 0 25 50 75 100 12 5 pwm section frequency jittering (%) t j , junction temperature ( c) figure 4. pwm section oscillator frequency jittering vs. temperature 85 84 83 82 81 80 79 78 77 76 75 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) figure 5. pwm section maximum duty vs. temperature cs2 pin = 0 v fb2 pin = 2 v pwm section maximum duty (%) 18 16 14 12 10 8 6 4 2 0 ?50 ?25 0 25 50 75 100 12 5 pwm section gate drive resistance ( ) r oh2 r ol2 t j , junction temperature ( c) figure 6. pwm section gate drive resistance vs. temperature 1.1 1.05 1 0.95 0.9 ?50 ?25 0 25 50 75 100 125 pwm section current limit (v) t j , junction temperature ( c) figure 7. pwm section current limit vs. temperature pwm section soft?start period (ms) 3 2.5 2 1.5 1 0.5 0 t j , junction temperature ( c) ?50 ?25 0 25 50 75 100 12 5 figure 8. pwm section soft?start period vs. temperature 12
NCP1603 http://onsemi.com 10 140 120 100 80 60 40 20 0 ?50 ?25 0 25 50 75 100 12 5 pwm section v alida tion time for leaving standby (ms) t j , junction temperature ( c) 350 300 250 200 150 100 50 0 ?50 ?25 0 25 50 75 100 125 pwm section lead edge blanking (ns) t j , junction temperature ( c) figure 9. pwm section lead edge blanking vs. temperature 120 100 80 60 40 20 0 ?50 ?25 0 25 50 75 100 12 5 pwm section cs propagation delay (ns ) t j , junction temperature ( c) figure 10. cs2 pin propagation delay vs. temperature ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) v cs2 = 2 v v fb2 = 2 v pwm section minimum pulse (ns) 500 450 400 350 300 250 200 150 100 50 0 figure 11. pwm section minimum output pulse vs. temperature 3.15 3.1 3.05 3 2.95 2.9 ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) figure 12. cs2 pin overvoltage protection threshold vs. temperature pwm section cs pin ovp threshold (v) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ?50 ?25 0 25 50 75 100 125 pwm section standby thresholds (v) t j , junction temperature ( c) figure 13. pwm section standby thresholds vs. temperature figure 14. pwm section validation time for leaving standby vs. temperature v stby?out v stby 160
NCP1603 http://onsemi.com 11 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) v fb2 = 0.75 v pwm section fb pin sinking capability ( a ) 250 245 240 235 230 225 220 215 210 205 200 figure 15. fb2 pin sinking capability vs. temperature 140 120 100 80 60 40 20 0 ?50 ?25 0 25 50 75 100 12 5 pwm section validation time for recognize a fault (ms) t j , junction temperature ( c) figure 16. pwm section validation time for recognizing a fault vs. temperature ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) v aux = 20 ma sinking v cc2 = 13 v v aux pin mosfet resistance ( ) 20 18 16 14 12 10 8 6 4 2 0 figure 17. v aux pin internal mosfet resistance vs. temperature 6 5 4 3 2 1 0 ?50 ?25 0 25 50 75 100 12 5 startup high voltage current source (ma) t j , junction temperature ( c) figure 18. pwm section high voltage startup current source vs. temperature i hv2 (v cc2 = v cc2(on) ? 0.2 v) hv pin = 30 v i hv1 (v cc2 = 0 v) 60 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 hv pin leakage current ( a) t j , junction temperature ( c) hv pin = 700 v v cc2 = 13 v figure 19. pwm section hv pin leakage current vs. temperature ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) v cc2 = v cc2(on) ? 0.2 v i hv = 0.5 ma hv pin minimum startup voltage (v) 25 24 23 22 21 20 19 18 17 16 15 figure 20. pwm section hv pin minimum operating voltage vs. temperature 160
NCP1603 http://onsemi.com 12 14 12 10 8 6 4 2 0 ?50 ?25 0 25 50 75 100 125 pwm section supply voltage thresholds (v) t j , junction temperature ( c) figure 21. pwm section supply voltage thresholds vs. temperature v cc2(reset) v cc2(latch) v cc2(on) v cc2(off) 2.5 2 1.5 1 0.5 0 ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pwm section supply currents (ma ) i cc2(op1) (v cc2 = 13 v, 1 nf load) i cc2(op2) (v cc2 = 13 v, out2 = open) i cc2(latch) (v cc2 = 6.5 v) v fb2 = 2 v figure 22. pwm section supply currents vs. temperature ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section oscillat or frequency (khz) 60 59 58 57 56 55 54 53 52 51 50 figure 23. pfc section oscillator frequency vs. temperature 51 50 49 48 47 46 45 44 ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) i odch (osc pin = 5.5 v) pfc section osc pin charge and discharge current ( a) i och (osc pin = 3 v) figure 24. pfc section osc pin charge and discharge current vs. temperature 5.5 5 4.5 4 3.5 3 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section synchronization thresholds (v) v sync(h) c osc = 220 pf v sync(l) figure 25. pfc section synchronization thresholds vs. temperature 18 16 14 12 10 8 6 4 2 0 ?50 ?25 0 25 50 75 100 12 5 pfc section gate drive resistance ( ) r oh1 r ol1 t j , junction temperature ( c) figure 26. pfc section gate drive resistance vs. temperature
NCP1603 http://onsemi.com 13 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section reference current ( a) 210 208 206 204 202 200 198 196 194 192 190 figure 27. pfc section reference current vs. temperature 1.2 1 0.8 0.6 0.4 0.2 0 150 160 170 180 190 200 210 22 0 pfc section regulation block (v) i fb , feedback current ( a) t j = 25 c figure 28. pfc section regulation block transfer function ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section regulation block ratio (%) 100 99 98 97 96 95 94 93 92 91 90 figure 29. pfc section regulation block vs. temperature 1.1 1.08 1.06 1.04 1.02 1 ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section maximum control voltage (v) i fb = 100 a figure 30. pfc section maximum control voltage vs. temperature 6 5 4 3 2 1 0 fb1 pin offset voltage (v) 0 50 100 150 200 250 i fb , feedback current ( a) t j = 125 c figure 31. feedback pin voltage vs. feedback current ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section overvoltage protection ratio (%) 110 109.5 109 108.5 108 107.5 107 106.5 106 105.5 105 figure 32. pfc section overvoltage protection ratio vs. temperature t j = 125 c t j = ?40 c t j = 25 c t j = ?40 c
NCP1603 http://onsemi.com 14 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section overvoltage protection threshold ( a) 220 218 216 214 212 210 208 206 204 202 200 figure 33. pfc section overvoltage protection threshold vs. temperature ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section overvoltage protection ratio (%) 10 9 8 7 6 5 4 3 2 1 0 figure 34. pfc section overvoltage protection ratio vs. temperature 120 100 80 60 40 20 0 cs1 pin offset voltage (mv) 0 50 100 150 200 250 i s1 , cs1 pin current ( a) t j = 125 c figure 35. cs1 pin offset voltage vs. current ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section cs pin offset (mv) 10 9 8 7 6 5 4 3 2 1 0 figure 36. pfc section cs pin offset vs. temperature ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section overcurrent protection threshold ( a) 210 208 206 204 202 200 198 196 194 192 190 figure 37. pfc section overcurrent protection threshold vs. temperature ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section zero current threshold ( a) 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 figure 38. pfc section zero current threshold vs. temperature t j = 25 c t j = ?40 c v s(zcd) v s(ocp)
NCP1603 http://onsemi.com 15 700 600 500 400 300 200 100 0 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section zero current sense resistor ( ) figure 39. pfc section zero current sense resistance vs. temperature ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section charging current ( a) 105 104 103 102 101 100 99 98 97 96 95 figure 40. pfc section charging current vs. temperature pwm section maximum power resistance (k ) 12 11.5 11 10.5 10 9.5 9 8.5 8 t j , junction temperature ( c) ?50 ?25 0 25 50 75 100 125 figure 41. pfc section maximum power resistance vs. temperature 11 10.5 10 9.5 9 8.5 8 ?50 ?25 0 25 50 75 100 12 5 pfc section supply voltage uvlo thresholds (v) t j , junction temperature ( c) v cc1(on) v cc1(off) figure 42. pfc section supply voltage undervoltage lockout thresholds vs. temperatu re 35 30 25 20 15 10 5 0 ?50 ?25 0 25 50 75 100 125 t j , junction temperature ( c) pfc section supply startup and shutdown currents ( a) i cc1(stdn) i cc1(stup) figure 43. pfc section supply current in startup and shutdown conditions vs. temperature ?50 ?25 0 25 50 75 100 12 5 t j , junction temperature ( c) pfc section operating supply currents (ma) 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 i cc1(op2) , 1 nf load i cc1(op1) , no load v cc1 = 15 v, c osc = 220 pf figure 44. pfc section operating supply curren ts vs. temperature
NCP1603 http://onsemi.com 16 operating description figure 45. t ypical application circuit emi filter NCP1603 + ? v ac z ovp v out v in l i l d 1 c filter q 1 r s1 r cs1 c bulk c osc r fb1 i fb1 i s c control c ramp r cs2 r s2 v bulk r ff i d d 3 q 2 d 2 c out c s z ref introduction the NCP1603 is a pwm/pfc combo controller for two?stages pfc low?power application. a typical application circuit is listed in figure 45. the first?stage pfc boost circuit draws a near?unity power factor current from the input but it also steps up the rectified input voltage v in to a high bulk voltage v bulk in the bulk capacitor c bulk . then, the second?stage pwm flyback circuit converts the bulk voltage v bulk to a usable low voltage and isolated output voltage v out . the controllers of the two stages are combined to become a single pwm/pfc combo controller. the advantages of NCP1603 are the following: 1. integrated maximum 500 v lossless high voltage startup circuit that saves area and power loss. 2. low standby power consumption because of pfc shutdown and skipping cycle operation. 3. proprietary pfc methodology limits the maximum switching frequency and frequency jittering feature of the second?stage make the easier front?ended emi filter design. 4. internal ramp compensation for stability improvement in the second stage converter. 5. minimum number of external components. 6. optional synchronization capability between the pfc and pwm sections for bulk capacitor ripple current reduction. 7. safety protection features. NCP1603 is a co?package of two individual ic dies. (ncp1601 and ncp1230, 100 khz) the pfc die links up pin 5 to pin 12 that are in the lower half of figure 46. the pwm die links up the other pins that are in the upper half of figure 46. for simplicity, the pfc pins are named with suffix one that stands for the first stage and the pwm pins are named with suffix two that stands for the second stage. this dual?dies architecture allows the pfc die to be completely powered off in the standby low?power condition. it makes the power supply an excellent low?power no load standby performance. 16 15 14 12 11 10 9 hv nc ramp cs1 fb1 v cc2 v control 13 out2 1 2 3 4 5 6 7 8 osc fb2 cs2 gnd2 gnd1 out1 v cc1 v aux pwm die pfc die figure 46. internal connection biasing the controller the pwm section is the master section that always operates. the pfc section is the slave section that is powered off in standby condition for power saving. it is implemented by connecting v aux pin (pin 1) and v cc1 pin (pin 8) together externally. the v cc1 pin generally requires a small decoupling external capacitor (0.1 f) or nothing. the pwm section powers the pfc section. the v cc of the whole device refers to v cc2 (pin 14) in the pwm section (i.e., v cc = v cc2 ). figure 47. bias supply schematic NCP1603 16 14 1 468 v bulk v cc2 c vcc gnd1 = gnd2 v cc1 = v aux
NCP1603 http://onsemi.com 17 the recommended biasing schematic of the controller is in figure 47 while a typical completed application schematic can be referred to figure 45. these two dies have their own individual supply voltages at pin 8 and pin 14. the grounds of the two dies are physically connected through the package substrate but they are needed to be connected externally. the bias voltage to the NCP1603 comes from the bulk voltage v bulk through the hv pin (pin 16) during startup. after startup, a second?stage flyback transformer auxiliary winding delivers the supply voltage to v cc . lossless high v oltage startup circuit figure 48. v cc2 management qs r double hiccup 2 counter & turn off + ? uvlo 3.2 ma 16 v bulk hv 12.6/ 5.6 v + ? 7.7 v 20 v 14 v cc turn on internal bias the hv pin (pin 16) is capable of the maximum 500 v so that this pin can be directly connected to the bulk voltage v bulk and delivers startup supply voltage to the controller. figure 48 illustrates the block diagram of the startup circuit. an uvlo comparator monitors the v cc at pin 14. a startup current source is activated and deactivated whenever the voltage reaches v cc2(latch) (5.6 v typical) and v cc2(on) (12.6 v typical) thresholds respectively. therefore, the v cc never drops below v cc2(latch) after powering up unless the circuit is unplugged (i.e., v bulk disappears or smaller than its minimum required operating threshold v start(min) (20 v typical)). this feature makes the controller memorize the external latch off function implemented in pin 3. this in?chip startup circuit can minimize the number of external components and printed circuit board (pcb) area. it also minimizes the loss due to startup resistor because startup resistor always dissipates power but this startup circuit can be turned off when the v cc voltage is sufficient. actually, there is a small leakage current i hv3 (30 a typical at hv = 700 v) when the startup circuit is off. the v cc capacitor is recommended to be at least 47 f to ensure that v cc is always above the minimum operating voltage v cc2(off) (7.7 v typical) in the startup phase. for example, the pwm die consumes i cc2(op2) (2.2 ma typical), a 47 f v cc capacitor can maintain the v cc above 7.7 v for 105 ms. it is the available time to establish a v cc voltage from the flyback transformer auxiliary winding. t startup c vcc v i cc2(op2) 47 f(12.6 v?7.7 v) 2.2 ma 105 ms (eq. 1) a large enough v cc capacitor can also help to maintain v cc2 always above v cc2(off) to prevent the ic accidentally powered off during the standby condition where the low?frequency ripple of v cc2 can be very high. the pfc section does not consume any current in the startup phase since v aux is disabled initially (i.e., v aux = v cc1 = 0 v). when v cc2 falls below v cc2(off) (7.7 v typical) for whatever reason, the pwm section sleeps and it consumes i cc2(latch) (680 a typical) until v cc2 reaches v cc2(latch) (5.6 v typical). when v cc2 reaches v cc2(latch) (5.6 v typical), the startup current source activates and v cc2 rises again. figure 49. v aux enabled regions 0.75 v 3 v non? usable vaux enabled region v fb2 fault condition (v fb2 > 3 v) usable vaux enabled region standby condition (v fb2 < 0.75 v) 7.7 v v cc2 (pwm ) 18 v 12.6 v v cc1 (pfc ) 18 v 10.5 v 9 v auxiliary supply v aux the v aux pin (pin 1) connects to the v cc1 pin (pin 8) externally. internally, the v aux pin is connected to v cc2 through an internal mosfet. the mosfet on?resistance is r aux (11.7 typical). it delivers a supply voltage from the pwm section to the pfc section. the v aux is disabled when one of the following conditions occurs. 1. v aux is initially disabled because of no feedback signal (v fb2 > 3.0 v) initially. 2. fault condition (v fb2 > 3.0 v for more than 125 ms). 3. standby condition (v fb2 < v stby (0.75 v typical) and then v fb2 < v stby?out (1.25 v typical) for more than 125 ms). 4. insufficient operating supply voltage (v cc2 < v cc2(off) (7.7 v typical)). 5. overvoltage protection (ovp) latch activated from cs2 pin (pin 3) (v cs2 > v ovp (3.0 v typical)).
NCP1603 http://onsemi.com 18 6. thermal shutdown latch in the pwm section activated when the junction temperature is over typical 150 c. the uvlo start thresholds of v cc1 is v cc1(on) (10.5 v typical) and the maximum allowable limit is 18 v. on the other hand, the v aux is enabled when v cc2 is over v cc2(off) (7.7 v typical). hence, there are two possible operating regions in figure 49. in the non?usable region the v aux is not high enough to turn on the pfc section. therefore, the flyback transformer auxiliary winding must be between v cc1(on) (10.5 v typical) and 18 v . regulation in the pwm section the pwm section (or the second stage) of the NCP1603 is ncp1230 that is a current?mode fixed?frequency pwm flyback controller with internal compensation ramp. the simplified block diagram of the duty cycle regulation section is in figure 50. a 100 khz clock oscillator is modulated by adding a frequency jittering feature. this modulated 100 khz clock signal turns the out2 (pin 13) high in each switching cycle. the out2 goes low when the current?loop feedback signal intersects with the output voltage?loop feedback signal. a duty cycle is therefore generated. the maximum duty ratio is limited to d max (80% typical). v out 2 opto coupler fb2 vdd 20 k 55 k 25 k v fb2 v fb2 3 soft?start processing circuit ? + 200 ns leb soft?start period 2.5 ms v fb2 3 1 v max pwm r s q max duty = 80% v cc2 13 3 out2 v bulk flyback drain current i d cs2 r s2 r cs2 6.4% frequency jittering modulation 100 khz oscillator 2.3 v 0 v 100 khz jittering ramp 18 k figure 50. block diagram of duty cycle regulation in the pwm section the current?loop feedback circuit consists of a typical 200 ns leading edge blanking (leb) that is to prevent a premature reset of the output due to noise, a pair of sense resistors r cs2 and r s2 that sense the flyback drain current i d , and a 0?to?2.3 v jittering ramp that adds a ramp compensation for a stability improvement to the current?mode control possibly in continuous mode operation. the v fb2 is approximately divided by 3 by an internal pair of resistors (55 k and 25 k ). the soft?start processing circuit reduces the initial voltage?loop feedback signal (v fb2 / 3) for 2.5 ms. after this 2.5 ms, the soft?start disappears. as a result, the startup envelope of the peak drain current (or duty ratio) ramps up gradually for 2.5 ms. it is noted that the 2.5 ms is counted when the pwm die circuit is reset that is when v cc2 reaches v cc2(on) (12.6 v typical). this soft?start feature offers a reduced transient voltage and current stress on the power circuit during the startup. excessive output voltage causes more the optocoupler current. it pulls down the v fb2 through fb2 pin (pin 2) and generates a lower duty ratio. the output voltage reduces. insufficient output voltage reduces the optocoupler current. if the current is too small, the v fb2 is eventually pulled high than 3.0 v (3.8 v typical). the (v fb2 /3) signal is then clamped to an internal 1.0 v limit. if the ramp is ignored (i.e., r s2 = 0), the maximum possible drain current is derived as: i d(max) 1v r cs2 (eq. 2) it is noted that resistor r s2 will affect the percentage of the ramp getting compared for the modulation. hence, a large value of the r s2 increase the ramp and will reduce the possible maximum duty ratio.
NCP1603 http://onsemi.com 19 frequency jittering 93.6 khz 100 khz 106.4 khz 5 ms time pwm section oscillator frequency figure 51. frequency jittering of pwm oscillator frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the pwm section offers a typical 6.4% deviation on the nominal switching frequency (100 khz typical). a sweep sawtooth modulates the 100 khz clock up and down with a 5.0 ms period. figure 51 illustrates the 6.4% variation of the jittering oscillator frequency versus time. fault condition figure 52 illustrates the fault detection circuitry and its timing diagram. when fault (or output short circuit) happens, the output voltage collapses and the optocoupler is opened. v fb2 is internally pulled to be higher than 3.0 v (3.8 v typical). then, the controller activates an error flag when (v fb2 /3) is greater than the soft?start voltage v ss that is 1.0 v after the 2.5 ms from startup. when the circuit is powering up in the beginning, the output voltage is not yet established and fb2 pin (pin 2) is opened. therefore, there is a 125 ms timer to allow the circuit to establish an initial output voltage. then, a fault (or short circuit) condition is recognized when an error flag (v fb2 3.0 v) can last for 125 ms. when a fault is detected, out2 (pin 13) goes low. the power supply stops delivering power to the output. on the other hand, the v aux (= v cc1 ) also goes low. the v aux will restore immediately when the error flag disappears. this fault detection method offers advantage of getting rid of the auxiliary winding information that cannot truely represent the output voltage when the flyback transformer is badly coupled. ? + 2 fb2 vdd 20 k 55 k 25 k v fb2 v fb2 3 soft?start 1 v max v ss start vaux enable vaux/pfc 125 ms delay & fault disable vaux/pfc and out2 soft?start period 2.5 ms figure 52. block diagram and timing diagram of fault detection 1 v v fb2 /3 v ss v aux 125ms v aux starts when v fb2 is within regulation window (v fb2 < 3 v). (i.e., normal operation) v aux stops when v fb2 is out o f regulation window (v fb2 > 3 v ) for more than 125 ms. (i.e., fault condition) 1 v time time
NCP1603 http://onsemi.com 20 5.6 v 12.6 v 7.7 v 0a v cc2 i d startup current source charging the v cc capacitor startup circuit turns off when v cc2 is 12.6 v circuit sleeps when v cc2 is below 7.7 v maximum drain current is limited to 1 / r cs2 startup circuit turns on when v cc2 is 5.6 v switching starts when v cc2 reaches 12.6 v peak drain current follows a 2.5 ms soft?start envelope switching is missing in every two v cc hiccup cycles featuring a ?double hiccup? figure 53. timing diagram of fault condition time figure 53 illustrates the timing diagram of v cc2 and the second?stage drain current i d in fault condition. the v cc drops because output voltage collapses. when v cc drops below v cc(off) (7.7 v typical), the drive output signal disappears and the v cc continues to drop. when bias voltage v cc drops to v cc(latch) (5.6 v typical), the startup current source activates and charge up the v cc until v cc reaches v cc(on) (12.6 v typical). the internal 2.5 ms soft?start activates after v cc reaches v cc(on) (12.6 v typical). the peak drain current follows its 2.5 ms envelope. the power supply dissipates some power due to the switching signal of out2 and waits for possible auto?recovery of operation when the fault is cleared. as shown in figure 53, NCP1603 has a ?double hiccup? feature that allows the drain current in every two v cc hiccup cycle in fault condition. the ?double hiccup? feature offers fewer power dissipation during fault condition comparing to ?single hiccup?. if the fault is cleared (v fb2 < 3.0 v ss ) and v cc remains above v cc2(off) (7.7 v typical), the circuit will resume its operation. otherwise, the v cc will continue this 12.6?7.7?5.6?12.6 v hiccup mode until the fault or bulk voltage is cleared. standby condition the output voltage rises up excessively in standby condition and the v fb2 drops. a set point of 25% of the maximum of v fb2 (i.e., 3.0 v) is defined to be the standby threshold. hence, the standby threshold is v stby = 25% 3.0 v = 0.75 v. fb2 125 ms delay & leave standby ? + 2 0.75 v / 1.25 v v fb2 enable vaux / standb y disable vaux/ pfc sectio n figure 54. block diagram and timing diagram of standby detection v fb2 v aux 1.25 v 0.75 v 125 ms v aux stops when v fb2 is below 0.75 v and cannot go above 1.25 v for 125 ms v aux restores when v fb2 goes above 1.25 v time time pfc section
NCP1603 http://onsemi.com 21 figure 54 illustrates the standby detection circuitry and its timing diagram. when standby condition happens (i.e., v fb2 < 0.75 v), the controller will wait for a typical 125 ms to ensure that the output power remains low for a while. then, the v aux is disabled to shut down the pfc section for power saving. the v aux (or the pfc) restores when v fb2 goes above 1.25 v immediately because v fb2 can be possibly above the 0.75 v threshold during standby operation (referring to figure 55) and the pfc section is needed after the circuit restores from standby condition. figure 55. timing diagram in standby condition v cc2 v fb2 i d out2 goes low (no drain current) when v fb2 < 0.75 v v cc2 needs to be above 7.7 v to ensure proper operation of the controller and main output within regulation 1.25 v 0.75 v 7.7 v time figure 56. block diagram in standby operation in pwm section cs2 fb2 vcc2 out2 pwm r s ? + 2 3 13 clock 0.75 v + ? or standby q v fb2 figure 55 and 56 show the timing diagram and block diagram of the standby operation respectively. a skipping cycle behavior of the drain current is made by reset the latch whenever v fb2 is smaller than 0.75 v. when v fb2 is greater than 0.75 v, the duty ratio is modulated by the pwm block that is illustrated in figure 50. pfc in discontinuous/critical mode the pfc section of the NCP1603 is ncp1601 that is designed for low?power pfc boost circuit in dcm or crm and takes advantages on both operating modes. dcm limits the maximum switching frequency. it simplifies the front?ended emi filter design. crm limits the maximum currents of diode, mosfet and inductor. it reduces the costs and improves the reliability of the circuit. this device substantially exhibits unity power factor while operating in dcm and crm. it minimizes the number of external components. the pfc section primarily designed to operate in fixed?frequency dcm. in the most stressful conditions, crm can be an alternative option that is without power factor degradation. on the other hand, the pfc section can be viewed as a crm controller with a frequency clamp (maximum switching frequency limit) alternative option that is also without power factor degradation. in summary, the pfc section can cover both crm and dcm without power factor degradation. based on the selections of the boost inductor and the oscillator frequency, the circuit is capable of the following three applications. 1. crm only by setting the oscillator frequency higher than the crm frequency range. 2. crm and dcm by setting the oscillator frequency somewhere within the crm frequency range. 3. dcm only by setting the oscillator frequency lower than the crm frequency range. figure 57. timing diagram of the pfc stage critical mode dcm dcm time current time time time v in v ton v control inductor current, i l input current, i in
NCP1603 http://onsemi.com 22 dcm needs higher peak inductor current comparing to crm in the same averaged input current. hence, crm is generally preferred at around the sinusoidal peak for lower the maximum current stress but dcm is also preferred at the non?peak region to avoid excessive switching frequencies. because of the variable?frequency feature of the crm and constant?frequency feature of dcm, switching frequency is the maximum in the dcm region and hence the minimum switching frequency will be found at the moment of the sinusoidal peak. dcm pfc circuit a dcm/crm pfc boost converter is shown in figure 58. input voltage is a rectified 50 or 60 hz sinusoidal signal. the mosfet is switching at a high frequency (typically around 100 khz) so that the inductor current i l basically consists of high?frequency and low?frequency components. figure 58. dcm/crm pfc boost converter v in i in i l l v out c bulk c filter filter capacitor c filter is an essential and very small value capacitor in order to eliminate the high?frequency content of the dcm inductor current i l . this filter capacitor cannot be too bulky because it can pollute the power factor by distorting of the rectified sinusoidal input voltage. pfc methodology the pfc section uses a proprietary pfc methodology particularly designed for both dcm and crm operation. the pfc methodology is described in this section. figure 59. inductor current in dcm t 1 t 2 t 3 i pk t tim e inductor current as shown in figure 59, the inductor current i l of each switching cycle starts from zero in dcm. crm is a special case of dcm when t 3 = 0. when the pfc boost converter mosfet is on, the inductor current i l increases from zero to i pk for a time duration t 1 with inductance l and input voltage v in . equation 3 is formulated. v in l i pk t 1 (eq. 3) the input filter capacitor c filter and the front?ended emi filter absorb the high?frequency component of inductor current. it makes the input current i in a low?frequency signal. i in i pk (t 1 t 2 ) 2t for dcm (eq. 4) i in i pk 2 for crm (eq. 5) from equations 3, 4, and 5, the input impedance z in is formulated. z in v in i in 2tl t 1 (t 1 t 2 ) for dcm (eq. 6) z in v in i in 2l t 1 for crm (eq. 7) power factor is corrected when the input impedance z in in equations 6 and 7 are constant or slowly varying. figure 60. pfc modulation circuit and timing diagram ? + closed when output low turns off mosfet ramp 12 c ramp i ch v ton v ton ramp out1 pwm comparator the mosfet on time t 1 of pfc modulation duty is generated by a feedback signal v ton and a ramp. the pfc modulation circuit and timing diagram are shown in figure 60. a relationship in equation 8 is obtained. t 1 c ramp v ton i ch (eq. 8) the charging current i ch is constant 100 a current and the ramp capacitor c ramp is constant for a particular design. hence, according to equation 8, the mosfet on time t 1 is proportional to v ton . in order to protect the pfc modulation comparator, the maximum voltage of v ton is limited to internal clamp v ton(max) (3.9 v typical) and the ramp pin (pin 12) is with
NCP1603 http://onsemi.com 23 a 9.0 v esd zener diode. the 3.9 v maximum limit of this v ton indirectly limits the maximum on time. the v control processing circuit generates v ton from control voltage v control and time information of zero inductor current. the circuit in figure 61 makes equations 9 and 10 where the value of resistor r 1 is much higher than the value of resistor r 2 (r 1 >> r 2 ). figure 61. v control processing circuit + ? closed when zero current 10 c control v control r 1 r 2 r 3 c 1 c 3 v ton v ton tv control t 1 t 2 for dcm (eq. 9) v ton v control for crm (eq. 10) it is noted that v ton is always greater than or equal to v control (v ton v control ). in summary, the input impedance z in in equation 11 is obtained from equations 3 through 10. z in v in i in 2li ch c ramp v control (eq. 11) control voltage v control comes from the pfc boost circuit output voltage (i.e., bulk voltage v bulk ) that is a slowly varying signal. the bandwidth of v control can be additionally limited by inserting an external capacitor c control to the v control pin (pin 10) in figure 62. the internal 300 k resistor and the capacitor c control create a low?pass filter that has a bandwidth f control in equation 12. it is generally recommended to limit the bandwidth below 20 hz to achieve power factor correction. typical value of c control is 0.1 f. c control 1 2 300k f control (eq. 12) figure 62. v control low?pass filtering 300k regulation block 10 c control v control v reg i ref i ref 96% i fb1 v control processing circuit if the bandwidth of v control is much less than the 50 or 60 hz line frequency, the input impedance z in is slowly varying or roughly constant. then, the power factor correction is achieved in dcm and crm. maximum power in pfc section input and output power (p in and p out ) are derived in equations 13 and 14 when the circuit efficiency is obtained or assumed. the variable v ac stands for the rms input voltage. p in v ac 2 z in v ac 2 c ramp v control 2li ch (eq. 13) p out p in v ac 2 c ramp v control 2li ch (eq. 14) from equations 13 and 14, control voltage v control controls the amount of output power, input power, or input impedance. the maximum value of the control voltage v control is 1.05 v (i.e., v control(max) = 1.05 v). a parameter called maximum power resistor r power (10.5 k typical) is defined in equation 18 and restricted to have a maximum 10% variation (i.e., 9.5 k r power 11.5 k ) for defining the maximum power in an application. r power v control(max) i ch 1.05 v 100 a 10.5 k (eq. 15) it means that the maximum input and output power (p in(max) and p out(max) ) are limited to 10% variation. p in(max) v ac 2 c ramp r power 2l (eq. 16) p out(max) v ac 2 c ramp r power 2l (eq. 17) the maximum input current i ac(max) to deliver the maximum input power p in(max) is also derived in (eq.14). the suffix ac stands for rms value. i ac(max) p in(max) v ac v acc ramp r power 2l (eq. 18)
NCP1603 http://onsemi.com 24 feedback in pfc section the output voltage of the pfc circuit (i.e., bulk voltage v bulk ) is sensed as a feedback current i fb1 flowing into the fb1 pin (pin 9) of NCP1603. the fb1 pin voltage v fb1 is typically smaller than 5.0 v referring to figure 31. it is much lower than v bulk that is typically 400 v. therefore, v fb1 is generally neglected. i fb1 v bulk v fb1 r fb1
v bulk r fb1 (eq. 19) where r fb1 is the feedback resistor connected the fb1 pin (pin 9) and the output voltage referring to figure 45. then, the feedback current i fb1 represents the bulk voltage v bulk and will be used in the pfc section voltage regulation, undervoltage protection (uvp), and overvoltage protection (ovp). bulk voltage regulation in pfc section pfc?stage feedback current i fb1 , that presents bulk voltage v bulk or the pfc?stage output voltage, is regulated with a reference current (i ref = 203 a typical) as shown in figure 63. when i fb1 is lower than 96% of i ref , the v reg that is the output of the regulation block is as high as v control(max) (1.05 v typical) that it gives the maximum value on v ton and the maximum mosfet on time and v bulk increases. when i fb1 is higher than i ref , the v reg becomes 0 v that gives no mosfet on time and v bulk decreases. as a result, the bulk voltage v bulk is regulated around the range between 96% and 100% of the nominal value of r fb1 i ref . figure 63. regulation block v reg i ref i ref 96% i fb1 1 v based on equations 13 and 14 for a particular power level, the v control is inversely proportional to v ac 2 . hence, in high v ac condition v control is lower. it means that i fb1 or output voltage is higher based on the regulation block characteristic in figure 63. in other words, the v control in the low v ac condition is much higher than the high v ac condition. in order to not over?design the circuit in the application, the v control in the low v ac condition is usually very closed to v control(max) . it makes the output voltage be almost 96% of the nominal value of r fb1 i ref in high v ac condition. the feedback resistor r fb1 consists of two or three high precision resistors in order to set the nominal v bulk precisely and for safety purpose. the regulation block output v reg is connected to control voltage v control through an internal resistor r control (300 k typical) for the low?pass filter in figure 62. the v control and the time information of zero current are collected in the v control processing circuit to generate v ton that is then compared to a ramp signal to generate the mosfet on time t 1 for power factor correction. current sense in pfc section the pfc section senses the inductor current i l by the current sense scheme in figure 64. this scheme has the advantages of: (1) the inrush current limitation by the resistor. r cs1 . and (2) the overcurrent protection and zero current detection implemented in the same pin. figure 64. current sense in pfc section cs1 NCP1603 gnd1 + ? r cs1 r s1 i l i s i l v s inductor current i l passes through r cs1 and creates a negative voltage. this voltage is measured by a current i s flowing out of the cs1 pin (pin 11). cs1 pin has an offset voltage v s . this offset voltage is studied in the setting of zero inductor current i l(zcd) and the maximum inductor current i l(ocp) (i.e., overcurrent protection threshold). a typical variation of offset voltage v s versus sense current i s is shown in figure 35. based on figure 64, equation 20 is derived. v s r s1 i s ?r cs1 i l (eq. 20) zero current detection (zcd) in pfc section the device recognizes zero inductor current when cs1 pin (pin 11) sense current i s is smaller than i s(zcd) (14 a typical). the offset voltage of the cs1 pin in this condition is v s(zcd) (7.5 mv typical). the inductor current i l(zcd) at the zcd condition is derived in equation 21. i l(zcd) r s1 i s(zcd) v s(zcd) r cs1 (eq. 21)
NCP1603 http://onsemi.com 25 it is obvious that the i l(zcd) is not always zero. in order to make it reasonably close to zero, the setting of r s1 and r cs1 are crucial. figure 65. cs pin characteristic when i l = 0 i s(zcd) v s(zcd) r s1 > r s(zcd) r s1 = r s(zcd) v s operating zcd point ideal zcd point i s based on the cs pin (pin 4) characteristics in figure 35, figure 65 is studied here. when the inductor current is exactly zero (i.e., i l(zcd) = 0), the ideal zcd point in the figure 65 is reached where r s1 is r s(zcd) (536 typical). considering the tolerance, the actual sense resistor r s1 is needed to be higher than the ideal value of r s(zcd) to ensure that zero current signal is generated when sense current is smaller than the zcd threshold (i.e., i s < i s(zcd) ). that is, r s r s(zcd) v s(zcd) i s(zcd) (eq. 22) the higher value of r s1 makes the bigger distance between the operating and ideal zcd points in figure 65. hence, r s1 has to be as low value as possible. the best recommended value of r s1 is therefore the maximum of r s(zcd) that is 1.0 k . now that the r s1 is set at a particular value that is greater than r s(zcd) . from equation 20, the operating lines in equation 23 with different inductor currents i l of equation 20 are studied. v s r s1 i s r cs1 i l (eq. 23) these operating lines are added in figure 65 to formulate figure 66. when the inductor current i l is smaller than i l(zcd) , the sense current i s is smaller than i s(zcd) and hence the zero current signal is generated. figure 66. cs pin characteristic with different inductor current i s(zcd) v s(zcd) v s operating zcd point i s best zcd point i l = i l(zcd) i l > i l(zcd) i l = 0 it is noted in figure 66 and equation 23 that when the (r cs1 i l ) term is smaller the error or distance between the lines to the line i l = 0 is smaller. therefore, the value of the current sense resistor r cs1 is also recommended to be as small as possible to minimize the error in the zero current detection. overcurrent protection (ocp) in pfc section overcurrent protection is reached when i s is larger than i s(ocp) (200 a typical). the offset voltage of the cs pin is v s(ocp) (3.2 mv typical) in this condition. that is: i l(ocp) r s1 i s(ocp) v s(ocp) r cs1 (eq. 24) when overcurrent protection threshold is reached, the drive output of the device goes low. oscillator/synchronization block in pfc section figure 67. oscillator / synchronization block in pfc section oscillator clock s r q zero current turn on mosfet ? + 5 v/3.5 v osc delay 0 5 1 45 a 94 a &
NCP1603 http://onsemi.com 26 the pfc section is designed to operate in either dcm or crm. in order to keep the operation in dcm and crm only, the drive output cannot turn on as long as there is some inductor current flowing through the circuit. hence, the zero current signal is provided to the oscillator/ synchronization block in figure 67. an input comparator monitors the osc pin (pin 5) voltage and generates a clock signal. the negative edge of the clock signal is stored in a rs latch. when zero current is detected, the rs latch will be reset and a set signal is sent to the output drive latch that turns on the mosfet in the pfc boost circuit. figure 68 illustrates a typical timing diagram of the oscillator block. figure 68. oscillator block timing diagram time clock inductor clock latch (latch set signal) discontinuous mode critical mode (latch output) current clock edge oscillator mode in pfc section in oscillator mode, the osc pin (pin 5) is connected to an external capacitor c osc . when the voltage of this pin is above v sync(h) (5.0 v typical), the pin sinks a current i odch (94?45 = 49 a typical) and the external capacitor c osc discharges. when the voltage reaches v sync(l) (3.5 v typical), the pin sources a current i och (45 a typical) and the external capacitor c osc is charged. it is noted that there is a typical 300 ns propagation delay and the 3.5 v and 5.0 v threshold conditions are measured on 220 pf c osc capacitor. hence, the actual oscillator hysteresis is a little bit smaller. figure 69. oscillator mode timing diagram in dcm osc pin voltage osc clock clock edge drive output (dcm) 5 v 3.5 v there is an internal capacitance c osc(int) (36 pf typical) in the oscillator pin and the oscillator frequency is to f osc(max) (405 khz typical) when the osc pin is opened. hence, the oscillator switching frequency can be formulated in equation 25 and represented in figure 70. c osc 36 pf 405 khz f osc 36 pf (eq. 25) 0 100 200 300 400 500 600 700 0 50 100 150 200 f osc , oscillator frequency (khz) c osc , oscillator capacitor (pf) figure 70. osc pin frequency setting synchronization option in synchronization mode, the osc pin (pin 5) receives an external digital signal with level high defined to be higher than v sync(h) (5.0 v typical) and level low defined to be lower than v sync(l) (3.5 v typical). an internal 9.0 v esd zener diode is connected to the osc pin and hence the maximum allowable synchronization voltage is 9.0 v. the circuit recognizes a synchronization frequency by the time difference between two falling edge instants when the synchronization signal across the 3.5 v threshold point. the actual synchronization threshold point is a little bit higher than the 3.5 v threshold point. the minimum synchronization pulse width is 500 ns. there is a typical 350 ns propagation delay from synchronization threshold point to the moment of output goes high and there is also a typical 300 ns propagation delay from the synchronization threshold point to the moment of crossing 3.5 v. hence, the output goes high apparently when the sync signal turns to 3.5 v. a timing diagram of synchronization mode is summarized in figure 71. figure 71. synchronization mode timing diagram in dcm sync signal osc clock clock edge drive output (dcm) 5 v 3.5 v the pwm and pfc section can be synchronized together in order to minimize some of the ripple current in the bulk capacitor as shown in figure 72 and 73. the out2 pin (pin 13) is the external synchronization signal in figure 71 to the pfc section. when the out2 is in high state, the voltage is potentially higher than the maximum allowable voltage in osc pin (pin 5). hence, a pair of resistors divides the voltage from out2 reduces the voltage
NCP1603 http://onsemi.com 27 entering osc pin and a capacitor is added to remove some possible noise as a result, the current in figure 73 may not necessarily passes through the bulk capacitor for fewer ripple current there. figure 72. synchronization configuration osc NCP1603 out2 figure 73. synchronization timing diagram pwm drive pfc drive (dcm) current phase 1 current phase 2 output drive the output stages of the pfc section and pwm section are designed for direct drive of power mosfet. however, it is recommended to connect a current limiting resistor to the gate of the power mosfet. the pfc section output is capable of up to ?500 ma and +750 ma peak drive current and has a typical rise and fall time of 53 and 32 ns with a 1.0 nf load while the pwm section output is capable of up to 1.0 a peak drive current and has a typical rise and fall time of 40 ns and a fall time of 15 ns with a 1.0 nf capacitive load. safety features of NCP1603 (1) bulk voltage overvoltage protection (ovp) when the pfc feedback current i fb1 is higher than 107% of the reference current i ref (i.e., the bulk voltage v bulk is higher than 107% of its nominal value), the pfc drive output pin (pin 7) of the device goes low for protection and the switch of the v control processing circuit is kept off. the circuit automatically resumes operation when the output voltage is lower than 107%. the maximum ovp threshold is limited to 225 a that corresponds to 225 a 1.95 m + 5.0 v = 443.75 v when r fb1 = 1.95 m (e.g., 910 k + 910 k + 130 k ) and v fb1 = 5.0 v (for the worst case referring to figure 31). hence, it is generally recommended to use 450 v rating output capacitor to allow some design mar gin. (2) bulk voltage undervoltage protection (uvp) when the pfc feedback current i fb1 is smaller than 8% of the reference current i ref , the pfc section is shutdown and consumes less than 50 a. in normal situation of the boost converter configuration, the output bulk voltage v bulk is always higher than input voltage v in and the i fb1 is higher than 8% of the reference current. it enables the pfc section to operate. hence, uvp happens when the bulk voltage v bulk is abnormally under?voltage, the fb1 pin (pin 9) is opened, or the fb1 pin (pin 9) is manually pulled low. (3) pfc?stage overcurrent protection when the pfc sense current i s1 is higher than typically 200 a, the pfc drive output (pin 7) goes low. it represents the pfc?stage inductor current i l exceeds a user?defined value. the operation automatically resumes when the inductor current becomes lower than this user?defined value at the next clock cycle. (4) pwm?stage short?circuit protection when v fb2 remains higher than 3.0 v for 125 ms, a fault is recognized. the pfc?stage (i.e., v aux ) will be disabled and the v cc2 will operate a double hiccup shown in figure 53. the operation will be self?recovered if v cc2 is above 7.7 v and v fb2 is below 3.0 v. this fault protection is implemented by a timer and independent of badly coupled auxiliary transformer winding. (5) latched v cc overvoltage protection the normal operating voltage range of the cs2 pin (pin 3) is between 0 v and i limit (1.0 v typical). when the voltage is above 1.0 v, the out2 (pin 13) goes low. when the voltage increases above 3.0 v, the out2 goes low and stays latched off until the circuit is reset by unplugging from main supply to make v cc2 drop below v cc(reset) (4.0 v typical). this feature also offers the designer the flexibility to implement an externally pull?high latched protection or latched shutdown circuit.
NCP1603 http://onsemi.com 28 in order to prevent wrongly triggering the latch protection function, it is generaly recommended to put a pf?order decoupling ceramic capacitor across the cs2 pin to remove possible high?frequency noise there. to set the v cc overvoltage protection, the circuit is configured in figure 74. a pnp bipolar transistor is added to open the zener diode z ovp when out2 is high in order to stop any interference of the normal operation of current sense. it is because the zener diode easily pulls high the cs2 pin voltage to 1.0 v and that interferes with the normal operation of the current sense when the output is high. the ovp threshold v cc2(ovp) is expressed in equation 26. v cc2(ovp) v zovp 3v (eq. 26) figure 74. v cc latched ovp application circuit cs2 NCP1603 v cc2 r cs2 z ovp r s2 (6) latched overvoltage protection (ovp) as long as an external protection on cs2 pin (pin 3) does not affect the normal regulation operation of current sense, the protection can be implemented. an alternative is to implement the output overvoltage protection by an optocoupler in figure 75. the leakage current of the added circuit is up to the zener diode at the output voltage. when there is no overvoltage, the leakage is small and it does not affect the normal operation. a resistor paralleled to the optocoupler is added to share the potential increasing leakage current of the zener diode due to temperature variation. the zener diode at the output voltage is recommended to be a 1 ma operating current at the threshold voltage. then, this current is coupled through the optocoupler and inserts a similar order of current (depending on the current?transfer?ratio ctr of the optocoupler) into cs2 pin. the cs2 pin is capable of up to 100 ma and with an internal 9 v anti?parallel esd diode but it is recommended to put a 8.2 v zener diode there to further protect the pin. figure 75. output latched ovp application circuit NCP1603 cs2 v cc2 r cs2 z ovp r s2 v out (7) dual thermal shutdown (tsd) the NCP1603 consists of two individual dies that incorporates their individual thermal shutdown. the pfc thermal circuitry disables the pfc gate drive out1 and then keeps the power switch off when its junction temperature exceeds 170 c typically. the pfc gate drive out1 is then enabled once the temperature drops below typically 125 c (i.e., 45 c hysteresis). the pwm thermal circuitry disables the pwm gate drive out2 and then keeps the power switch off when its junction temperature exceeds 165 c typically. the pwm gate drive out2 is then enabled once the temperature drops below typically 140 c and the circuit is unplugged (to make v cc2 drops below 4.0 v).
NCP1603 http://onsemi.com 29 pfc toggling the variation of the duty ratio in the pwm stage between the pfc?on or pfc?off can be very large. when the NCP1603 circuit is operating at some conditions between pfc on and off boundary, the duty ratio variation can lead to unwanted on/off toggling in the pfc stage. a current feedforward resistor r ff is hence recommended to added between v aux and cs2 pin (pins 1 and 3) in figure 76 to prevent the toggling. the value of r ff is much larger than current sense feedback resistor r s2 and plays very little effect when v aux = 0 (or pfc is of f). when v aux is available (or pfc is on), the r ff creates a positive offset on the cs2 pin voltage and it allows the feedback voltage v fb2 to only shift slightly but provide a dramatic duty cycle reduction in figure 77. it slight movement of the feedback voltage can reduce the change to reach the pfc stage on/off threshold. hence, the current feedforward resistor can help to improve the toggling. cs2 NCP1603 r ff r s2 v bulk v aux figure 76. feedforward resistor r ff added figure 77. timing diagram of pwm stage when r ff is added high duty when pfc is off. low duty when pfc is on. out 2 v cs2 v aux v fb2 3
NCP1603 http://onsemi.com 30 package dimensions so?16 d suffix case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NCP1603/d the products described herein (NCP1603), may be covered by one or more of the following u.s. patents: 6,271,735, 6,362,067, 6,3 85,060, 6,597,221, 6,970,365. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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