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ds04-22110-4e fujitsu semiconductor data sheet assp communication control 155-mbps atm transceiver mb582a/583a n description the mb582a and MB583A are the chip set that forms a transceiver used for high-speed, point-to-point communications over optical ?ers such as in atm-lan (asynchronous transfer mode lan), sdh (synchronous digital hierarchy), and sonet (synchronous optical network). the mb582a transmitter chip generates a high-frequency clock signal from a low-frequency reference clock signal using an internal phase-locked loop (pll). with the generated clock, the mb582a multiplexes eight- channel parallel data into single-channel serial data. the MB583A receiver chip extracts and regenerates the regenerated clock signal from received serial data using an internal pll. with the regenerated clock, the MB583A demultiplexes single-channel serial data into eight- channel parallel data. n features applicable to atm, sdh, and sonet 155.52-mbps serial data transmission internal pll two reference clocks available (19.44 and 51.84 mhz) pecl serial interface plus ttl parallel interface single +5 v power supply directly connectable to atm network termination controller (mb86683 ntc) power save mode with no signal low power consumption (about 0.3 w), wide operating temperature range (?0 c to +85 c) high-speed bipolar technology n product series part number function serial data transmission rate transmission code transmission medium power consumption mb582a transmitter 155.52 mbps nrz optical, utp5 0.25 w MB583A receiver 155.52 mbps nrz optical, utp5 0.3 w
2 mb582a/583a n package 48 pin plastic lqfp (fpt-48p-m05)
3 mb582a/583a n pin assignments mb582a (transmitter) 39 37 38 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd do v cc do gnd nc nc refclk gnd v cc v cc v cc clksel gnd reset extclk pdown timer gnd pclksel piclk gnd poclk v cc d7 v cc d6 gnd d5 d4 d3 d2 gnd v cc d1 d0 tx-ready gnd v cc gnd fil2 fil1 nc refsel nc nc av cc agnd (fpt-48p-m05) (top view)
4 mb582a/583a MB583A (receiver) 39 37 38 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd d v cc d gnd tlosi losi refclk gnd v bb losi nc nc gnd v cc nc timer refsel pdown v cc gnd gnd poclk v cc do 7 v cc do 6 gnd do 5 do 4 do 3 do 2 gnd v cc do 1 do 0 rx-ready gnd v cc gnd loso extclk fil2 fil1 reset clksel av cc agnd (fpt-48p-m05) (top view)
5 mb582a/583a n pin description mb582a (transmitter) (continued) pin no. symbol pin name i/o interface (speed) function 24, 23 20 to 17, 14,13 d0 to d7 parallel data input ttl input <19.44 mbyte/s> parallel data input pins: parallel data d0 to d7 are fetched at the rising edge of the piclk pulse or by the internal parallel clock. 10 piclk parallel clock input ttl input <19.44 mhz> clock input pin for parallel data fetching: parallel data d0 to d7 are fetched at the rising edge of the piclk pulse. this pin is used for the clock synthesizer. connect a stable oscillator (such as a crystal oscillator within 20 ppm) to this pin. this pin is used when pclksel = ?? this pin can? be used when refsel = ?? 9 pclksel parallel clock selection ttl input <0 or 1> clock selection pin for parallel data fetching: the internal parallel clock and piclk are selected when this pin inputs ? and ?, respectively. also, this pin is used to select the reference clock for the clock synthesizer. refclk and piclk are selected when this pin inputs ? and ?? respectively. 46 refclk reference clock input ttl input <19.44 or 51.84 mhz> reference clock input pin: this pin is used for the pll circuit in the clock synthesizer. connect a stable oscillator (such as a crystal oscillator within 20 ppm) to this pin. one of two reference clocks can be selected. this pin is used when pclksel = ?? 32 refsel reference clock selection ttl input <0 or 1> reference clock selection pin: the 19.44- and 51.84-mhz reference clocks are selected when this pin inputs ? and ?, respectively. 4 extclk external clock input pecl input single pecl input pin: this pin inputs a high- frequency external clock signal to execute an 8-to-1 multiplexer function independent of the clock synthesizer. in this case, the operating frequency is free and may be up to 155.52 mhz. this pin is used when clksel = ??
6 mb582a/583a (continued) (continued) pin no. symbol pin name i/o interface (speed) function 3 clksel clock selection ttl input <0 or 1> clock selection pin: the clock generated by the clock synthesizer and the extclk clock are selected when this pin inputs ? and ?, respectively. 2 reset reset input asynchronous reset input pin: this pin is used to initialize the internal state. the internal circuit is reset when this pin inputs ?? upon reset, the tx-ready and poclk pins output low-level signals. also, the serial data output pins do and do output low- and high-level signals, respectively. the device must be reset when the power is turned on. for details, see ?ower-on reset,p17. 5 pdown power down ttl input <0 or 1> sleep mode pin: the circuit supply current is reduced to about 1/3 of normal level when this pin inputs ?. when it inputs ?, the circuit restores normal operation. in sleep mode, the tx-ready and do pins output low-level signals; the do and poclk pins output high-level signals. for details on sleep mode, see ?sing sleep mode, p19. 39 41 do do serial data output pecl output <155.52 mbps> serial data output pins: these pins output nrz- coded serial data converted from parallel data in the order of d7 to d0. 12 poclk parallel clock output ttl output <19.94 mhz> parallel clock output pin: this pin outputs a parallel clock synchronized with reflck. this output pin can be connected to the controller (mb86683 ntc). 25 tx-ready ready output ttl output asynchronous ready output pin: this pin indicates whether the mb582 is ready. the pin outputs the high-level signal when the device is in the ready state. the pin does not indicate the ready state when; the piclk pulse is not input while pclksel = ? (selecting piclk for the parallel clock), reset = ? (for reset operation), pdown = ? (for sleep mode), or the pll circuit in the clock synthesizer is not locked.
7 mb582a/583a (continued) pin no. symbol pin name i/o interface (speed) function 6 timer timer timer pin: this pin can be used for automatic power-on reset by connecting a 4.7 m f capacitor between this pin and the gnd pin. be sure to leave this pin open when not in use. the device must be reset when the power is turned on. the power-on reset can take place automatically only by connecting the capacitor to this pin. for details, see ?ower-on reset, p17. 30 29 fil1 fil2 external capacitor external capacitor connection pins: a 1 nf capacitor is connected between these pins. this capacitor is the ?ter capacitor for the clock synthesizer. 31, 33, 34, 43, 45 nc unused pin leave these pins open. 1, 8, 11, 15, 22, 26, 27, 37, 42, 48 gnd digital gnd digital gnd pins: connect bypass capacitors between these pins and the digital v cc pins. 7, 16, 21, 28, 38, 40, 44, 47 v cc digital v cc digital v cc pins: connect bypass capacitors between these pins and the digital gnd pins. 36 agnd analog gnd analog gnd pin: connect bypass capacitors between this pin and the av cc (analog v cc ) pin. 35 av cc analog v cc analog v cc pin: connect bypass capacitors between this pin and the agnd (analog gnd) pin.
8 mb582a/583a MB583A (receiver) (continued) pin no. symbol pin name i/o interface (speed) function 41 39 d d serial data input pecl input <155.52 mbps> serial data input pins: these pins input nrz- coded data at 155.52 mbps. 45 44 losi losi loss input pecl input <0 or 1> loss input pins: when losi = ? and losi = ?, the input serial data is regarded as being lost; the rx-ready and loso pins output low- and high- level signals, respectively. since the losi and losi pins are both connected to the reference voltage via an internal high resistor, single input is allowed with either of the pins open. these pins are used when tlosi = gnd. 43 tlosi loss input ttl input <0 or 1> loss input pin: when this pin inputs ?, the input serial data is regarded as being lost; the loso pin outputs the high-level signal. this pin is used when losi = gnd and losi = open. 46 refclk reference clock input ttl input <19.44 or 51.84 mhz> reference clock input pin: this pin is used for the pll circuit in the clock recovery unit. connect a stable oscillator (such as a crystal oscillator within 20 ppm) to this pin. one of two reference clocks can be selected. 6 refsel reference clock selection ttl input <0 or 1> reference clock selection pin: the 19.44- and 51.84-mhz reference clocks are selected when this pin inputs ? and ?, respectively. 30 extclk external clock input pecl input single pecl input pin: this pin inputs a high- frequency external clock signal to execute an 1-to-8 demultiplexer function independent of the clock recovery unit. in this case, the operating frequency is free and may be up to 155.52 mhz. this pin is used when clksel = ?? 34 clksel clock selection ttl input <0 or 1> clock selection pin: the clock generated by the clock recovery unit and the extclk clock are selected when this pin inputs ? and ?, respectively. 33 reset reset input ttl input <0 or 1> asynchronous reset input pin: this pin is used to initialize the internal state. the internal circuit is reset when this pin inputs ?? upon reset, the rx-ready, poclk, and do0 to do7 pins output low-level signals. the device must be reset when the power is turned on. for details, see ?ower-on reset,p17.
9 mb582a/583a (continued) (continued) pin no. symbol pin name i/o interface (speed) function 8 pdown power down ttl input <0 or 1> sleep mode pin: when this pin inputs ?, the MB583A enters the sleep mode. actual sleep operation is performed to reduce the circuit supply current to 1/3 of normal level after serial data input of ? or ? remains unchanged, or after a loss signal is received. when a serial data signal is received and the loss signal is cleared, the device restores normal circuit operation. note that, whenever the serial data input is variable in level without being ?ed as ? or ?? the device will assume that data is being received (the optical module connected to the serial data input may output variable level when the optical signal interrupted). when pdown = ?? the device does not enter the sleep mode regardless of the status of the serial data or loss signals. in sleep state, the rx-ready pin outputs the low- level signal; the loso, poclk, and do0 to do7 pins output high-level signals. for details on the sleep mode, see ?sing sleep mode, p19. 24, 23, 20 to 17, 14, 13 do0 to do7 parallel data output ttl output <19.44 mbyte/s> parallel data output pins: these pins output nrz- coded parallel data converted from serial data in the order of do7 to do0. 12 poclk parallel clock output ttl output <19.44 mhz> parallel clock output pin: this pin outputs a parallel clock synchronized with serial data. this output pin can be connected to the controller (mb86683 ntc). if no serial data is input when pdown = ? (sleep mode off) or a loss signal is received, this pin serves as a parallel clock output synchronized with refclk. if no serial data is input when pdown is ? (sleep mode on) or a loss signal is received, the device enters the sleep state and this pin outputs the high- level signal. note that, whenever the serial data input is variable in level without being ?ed as ? or ?, the device will assume that data is being received (the optical module connected to the serial data input may output variable level when the optical signal interrupted).
10 mb582a/583a (continued) (continued) pin no. symbol pin name i/o interface (speed) function 29 loso loss output ttl output asynchronous loss output pin: this pin outputs the high-level signal after serial data input of ? or ? remains unchanged or on reception of a loss signal. note that, whenever the serial data input is variable in level without being ?ed as ? or ?, the device will assume that data is being received (the optical module connected to the serial data input may output variable level when the optical signal interrupted). this output pin can be connected to the controller (mb86683 ntc). 25 rx-ready ready output ttl output asynchronous ready output pin: this pin indicates whether the MB583A is ready. the pin outputs the high-level signal when the device is in the ready state. the pin does not indicate the ready state when; serial data input of ? or ? remains unchanged, on reception of a loss signal, reset = ?, or the pll circuit in the clock recovery unit is not locked. 40 v bb reference voltage output reference voltage output pin: for single input of serial data, connect the vbb and d pins using a resistor. for differential input of serial data, leave this pin open. 5 timer timer timer pin: this pin can be used for automatic power-on reset by connecting a 4.7 m f capacitor between this pin and the gnd pin. be sure to leave this pin open when not in use. the device must be reset when the power is turned on. the power-on reset can take place automatically only by connecting the capacitor to this pin. for details, see ?ower-on reset, p17. 32 31 fil1 fil2 external capacitor external capacitor connection pins: a 1 nf capacitor is connected between these pins. this capacitor is the ?ter capacitor for the clock recovery. 3, 4, 7 nc unused pin leave these pins open.
11 mb582a/583a (continued) pin no. symbol pin name i/o interface (speed) function 1, 10, 11, 15, 22, 26, 27, 37, 42, 48 gnd digital gnd digital gnd pins: connect bypass capacitors between these pins and the digital v cc pins. 2, 9, 16, 21, 28, 38, 47 v cc digital gnd digital v cc pins: connect bypass capacitors between these pins and the digital gnd pins. 36 agnd analog gnd analog gnd pin: connect bypass capacitors between this pin and the av cc (analog v cc ) pin. 35 av cc analog v cc analog v cc pin: connect bypass capacitors between this pin and the agnd (analog gnd) pin.
12 mb582a/583a n block diagrams mb582a (transmitter) (ttl-in) (24) d0 (23) d1 (20) d2 (19) d3 (18) d4 (17) d5 (14) d6 (13) d7 data latch register 8 : 1 multiplexer load clk (ttl-in) (9) pclksel (10) piclk (4) extclk (3) clksel (pecl-in) (ttl-in) (46) refclk (ttl-in) (2) reset (5) pdown (6) timer (30) fil1 4.7 m f (ttl-out) poclk (12) (ttl-out) tx-ready (25) (pecl-out) do (41) do (39) output buffer pclk select timing generator output buffer output buffer refclk select (32) refsel input buffer (ttl-in) (29) fil2 clock synthesizer clk select 1 nf
13 mb582a/583a MB583A (receiver) (41) d (39) d (40) v bb 1 : 8 demuitiplexer (30) extclk (34) clksel (ttl-in) (ttl-in) (46) refclk (6) refsel (ttl-in) (33) reset (8) pdown (5) timer 4.7 m f (ttl-out) poclk (12) (ttl-out) rx-ready (25) do0 (24) output buffer output buffer intput buffer timing generator clk select clock recovery intput buffer los intput buffer do1 (23) do2 (20) do3 (19) do4 (18) do5 (17) do6 (14) do7 (13) (ttl-out) output buffer output buffer (ttl-out) loso (29) (pecl-in) (pecl-in) (43) tlosi (45) losi (44) losi (ttl-in) fil1 (32) fil2 (31) 1 nf
14 mb582a/583a n functions (1) mb582a (transmitter) reference clock function high-frequency clock function reset function parallel clock function sleep mode function ready signal function the device is not ready when; piclk is not input while pclksel = ? (selecting piclk as parallel clock input) reset = ? (reset operation) pdown = ? (sleep state) the pll circuit in the clock synthesizer is not locked (because of the refclk frequency not matched, external resistor not connected, etc.) pdown and reset functions x: 0 or 1 pclksel refsel reference clock terminal reference clock frequency 1 (open) 1 (open) refclk 19.44 mhz 0 refclk 51.84 mhz 0 1 (open) piclk 19.44 mhz 0 prohibit clksel internal clock reset reset 1 (open) clock synthesizer 1 (open) 0 extclk 0 reset pclksel parallel data input clock 1 (open) internal parallel clock (setup/hold time required between poclk and d0 to d7) 0 piclk (setup/hold time required between piclk and d0 to d7) pdown sleep mode tx-ready device state 1 sleep h ready 0 (open) wake-up l not ready pdown reset sleep mode tx-ready do do poclk 1 x sleep l l h h 0 1 not sleep h normal operation normal operation normal operation 0 llhl
15 mb582a/583a (2) MB583A (receiver) reference clock function high-frequency clock function reset function loss function loso = h when; losi or tlosi = ? input serial data of ? or ? remains unchanged.* * : note that, whenever the serial data input is variable in level without being ?ed as ? or ?, the device will assume that data is being received (the optical module connected to the serial data input may output variable level when the optical signal interrupted). refsel refclk clksel internal clock 1 (open) 19.44 mhz 1 (open) clock recovery 0 51.84 mhz 0 extclk reset reset 1 (open) 0 reset loso input serial data losi, tlosi input serial data h los detection 1 los detection l receive state 0 receive state loss signal selection setting conditions losi, losi (pecl) tlosi = gnd (open) tlosi (ttl) losi = gnd also losi = open
16 mb582a/583a sleep mode function ready signal function the sleep mode is turned on when; input serial data of ? or ? remains unchanged.* the loss signal is received. the device is not ready when; input serial data of ? or ? remains unchanged.* the loss signal is received. reset = ? (reset operation) the pll circuit in the clock recovery unit is not locked (because of the refclk frequency not matched, external resistor not connected, etc.) input serial data, pdown, reset, losi, and tlosi functions loss state: input serial data of ? or ? remains unchanged.* x: 0 or 1 * : note that, whenever the serial data input is variable in level without being ?ed as ? or ?, the device will assume that data is being received (the optical module connected to the serial data input may output variable level when the optical signal interrupted). pdown sleep mode rx-ready device state 1 (open) sleep mode on h ready 0 sleep mode off l not ready input serial data pdown reset losi, tlosi sleep mode rx-ready loso do0 to do7 poclk receive state 1 1 1 sleep l h h h 0 not sleep h l normal operation normal operation 0 1 sleep l hh h 0 not sleep l l l 0 1 1 not sleep l h undefined synchronizing with refclk 0hl normal operation normal operation 0 1 l h ll 0l loss state 1 x x sleep l h h h 0 1 x not sleep l h undefined synchronizing with refclk 0ll
17 mb582a/583a n power-on reset the mb582a and MB583A must be reset when the power is turned on. there are two methods available for resetting each device at power-on. select the best method. (1) apply a reset to the device at power-on, then cancel the reset 50 ms after the v cc and av cc have reached 5 v or input a reset pulse with a width of 50 ms after they reached 5 v. note that a stable reference clock signal (refclk or piclk) must be input before the reset is canceled. (see the diagram below.) this method eliminates the need for connecting an external capacitor to the timer pin as described in method (2). be sure to leave the timer pin open when not in use. 50 ms or more 50 ms or more (active) (inactive) (inactive) (active) v cc , av cc (= 5 v) v cc , av cc (= 0 v) select either reset reset stable reference clock stable reference clock reference clock reference clock
18 mb582a/583a (2) connect a 4.7 m f external capacitor between the timer and gnd pins. the capacitor is used for automatic power-on reset. whenever the power is recycled, ensure that it remains off for at least 500 ms. (see the diagram below.) this method allows the reset signal to be used without considering the restrictions described in method (1). the reset pin may be left open. note, however, that a stable reference clock signal (refclk or piclk) must be input within 50 ms after power- on. 500 ms or more (off) v cc , av cc (= 5 v) v cc , av cc (= 0 v) stable reference clock reference clock 50 ms or less (on)
19 mb582a/583a n using sleep mode using the mb582a sleep mode it is necessary to follow either method (1) or (2) when using the sleep mode, otherwise the device will not return to normal operating status. (1) apply a reset to the device when it enters sleep mode, then cancel the reset 50 ms after clearing the pdown signal or input a reset pulse with a width of 50 ms after clearing the pdown signal. note that a stable reference clock signal (refclk or piclk) must be input before the reset is canceled. (see the diagram below.) this method eliminates the need for connecting an external capacitor to the timer pin as described in method (2). be sure to leave the timer pin open when not in use. 50 ms or more 50 ms or more (active) (inactive) (inactive) (active) (inactive) select either reset reset (active) pdown stable reference clock reference clock stable reference clock reference clock
20 mb582a/583a (2) connect a 4.7 m f external capacitor between the timer and gnd pins. the capacitor is used for automatically resetting the sleep mode. be sure that the pdown signal has an active phase of at least 500 ms. (see the diagram below.) this method allows the reset signal to be used without considering the restrictions described in method (1). the reset pin may be left open. note, however, that a stable reference clock signal (refclk or piclk) must be input within 50 ms after the power save mode is canceled (as shown in the following illustration.) using the MB583A sleep mode it is necessary to use method (1) when using the sleep mode, otherwise the device will not return to normal operating status. (1) apply a reset to the device when the loso output goes high (the los state detected), then cancel the reset 50 ms after the loso output goes low (receive state) or input a reset pulse with a width of 50 ms after the loso output changes from high to low. note that a stable reference clock signal (refclk) must be input before the reset is canceled. (see the diagram below.) be sure to leave the timer pin open when not in use. (active) (inactive) pdown 500 ms or more within 50 ms stable reference clock reference clock 50 ms or more 50 ms or more (active) (inactive) (inactive) (active) (inactive) select either reset reset (active) loso stable reference clock reference clock stable reference clock reference clock
21 mb582a/583a n timing charts mb582a (transmitter) MB583A (receiver) poclk do d0-2 d7-2 d0-1 d7-1 d0-0 d7-0 d7 -0 d6 -0 d5 -0 d4 -0 d3 -0 d2 -0 d1 -0 d0 -0 d7 -1 d6 -1 d5 -1 d4 -1 d3 -1 d2 -1 d1 -1 d0 -1 d7 -2 d6 -2 d5 -2 d4 -2 piclk d7 d0 poclk d d0-2 d7-2 d0-1 d7-1 d0-0 d7-0 d3 -2 d2 -2 d1 -2 d0 -2 d7 -3 d6 -3 d1 -0 d0 -0 d7 -1 d6 -1 d5 -1 d4 -1 d3 -1 d2 -1 d1 -1 d0 -1 d7 -2 d6 -2 d5 -2 d4 -2 do7 do0
22 mb582a/583a n absolute maximum ratings * : the voltage is based on gnd. note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. n recommended operating conditions * : the voltage is based on gnd. connection diagram of pecl output termination resistor parameter symbol rating unit power supply voltage* v cc 0 to 6.0 v input voltage* ttl v in ?.5 to v cc +0.5 v pecl v in 2.0 to v cc v output voltage* ttl v out ?.5 to 5.5 v output current pecl i out ?0 ma storage temperature tstg ?5 to +150 c parameter symbol value unit power supply voltage* v cc 5.0 5 % v high-level output current ttl i oh ? ma low-level output current i ol 4ma do and do output termination resistors pecl? cc r t1 82 w pecl?nd r t2 130 w operating temperature ta ?0 to +85 c v cc r t1 r t2 out ic do, do pecl
23 mb582a/583a n electrical characteristics 1. dc characteristics mb582a (transmitter) (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c) *1: typical values assume that v cc = +5.0 v and ta = +25 c. *2: the output short-circuit duration must not exceed 1 second. more than one output must not be short-circuited at the same time. (continued) parameter symbol conditions value unit min. typ. *1 max. ttl input high-level input voltage v ih 2.0 v low-level input voltage v il 0.8 v input clamp voltage v ic v cc = 4.75 v, i i = ?8 ma ?.5 v high-level input current i ih v cc = 5.25 v, v i = 2.4 v 500 m a low-level input current i il v cc = 5.25 v, v i = 0.5 v ?00 m a ttl output high-level output voltage v oh v cc = 4.75 v, i oh = ? ma 2.4 v low-level output voltage v ol v cc = 4.75 v, i ol = 4 ma 0.5 v output short- circuit current *2 i os v cc = 5.25 v, v o = 0 v ?50 ma single pecl input (extclk) high-level input voltage v ih ? cc ?1.165 v cc ?0.72 v low-level input voltage v il ? cc ?1.95 v cc ?1.475 v high-level input current i ih v i = v cc ?0.72 v 200 m a low-level input current i il v i = v cc ?1.95 v ?00 m a input open-circuit voltage v io ? cc ?1.26 v cc ?1.32 v cc ?1.38 v pecl output (do, do ) high-level output voltage v oh output load: 82 w to v cc 130 w to gnd ta = ?0 cv cc ?1.15 v cc ?0.89 v ta = 0 cv cc ?1.09 v cc ?0.84 v ta = +25 cv cc ?1.05 v cc ?0.92 v cc ?0.81 v ta = +75 cv cc ?0.99 v cc ?0.735 v ta = +85 cv cc ?0.98 v cc ?0.72 v
24 mb582a/583a (continued) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ. *1 max. pecl output (do, do ) low-level output voltage v ol output load: 82 w to v cc 130 w to gnd ta = ?0 cv cc ?1.15 v cc ?1.63 v ta = 0 cv cc ?1.09 v cc ?1.63 v ta = +25 cv cc ?1.05 v cc ?0.92 v cc ?1.63 v ta = +75 cv cc ?0.99 v cc ?1.60 v ta = +85 cv cc ?0.98 v cc ?1.595 v supply current during operation i cc v cc = 5.25 v, i/o = open 50 80 ma sleep state i ccd v cc = 5.25 v, pdown = ? other i/o pins = open ?540ma pecl output current (do + do ) during operation i o1 v cc = 5.25 v output load: 82 w to v cc 130 w to gnd ?5 ?4 ma sleep state i od1 ?5 ?4 ma
25 mb582a/583a MB583A (receiver) (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c) *1: typical values assume that v cc = +5.0 v and ta = +25 c. *2: the output short-circuit duration must not exceed 1 second. more than one output must not be short-circuited at the same time. (continued) parameter symbol conditions value unit min. typ. *1 max. ttl input high-level input voltage v ih 2.0 v low-level input voltage v il 0.8 v input clamp voltage v ic v cc = 4.75 v, i i = ?8 ma ?.5 v high-level input current i ih v cc = 5.25 v, v i = 2.4 v 500 m a low-level input current i il v cc = 5.25 v, v i = 0.5 v ?00 m a ttl output high-level output voltage v oh v cc = 4.75 v, i oh = ? ma 2.4 v low-level output voltage v ol v cc = 4.75 v, i ol = 4 ma 0.5 v output short- circuit current *2 i os v cc = 5.25 v, v o = 0 v ?50 ma differential pecl input (d, d , losi, losi ) high-level input voltage v ih v cc ?0.72 v low-level input voltage v il ? cc ?1.95 v differential input voltage v dif v ih ? il 0.1 1.2 v high-level input current i ih v i = v cc ?0.72 v 200 m a low-level input current i il v i = v cc ?1.95 v ?00 m a single pecl input (extclk, losi, losi ) high-level input voltage v ih ? cc ?1.165 v cc ?0.72 v low-level input voltage v il ? cc ?1.95 v cc ?1.475 v high-level input current i ih v i = v cc ?0.72 v 200 m a low-level input current i il v i = v cc ?1.95 v ?00 m a input open-circuit voltage v io ? cc ?1.26 v cc ?1.32 v cc ?1.38 v
26 mb582a/583a (continued) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ. *1 max. v bb output reference voltage v bb ? cc ?1.26 v cc ?1.32 v cc ?1.38 v during operation i cc v cc = 5.25 v, pdown = ? other i/o pins = open 60 110 ma supply current sleep state i ccd v cc = 5.25 v, pdown = ? other i/o pins = open ?050ma
27 mb582a/583a 2. ac characteristics (1) mb582a (transmitter) parallel clock input and parallel data input timings (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) parameter symbol conditions value unit min. typ. max. piclk ? d0 to d7 setup time t su1 pclksel = ? 5.0 ns hold time t h1 5.0 ns poclk ? d0 to d7 setup time t su2 pclksel = ? 5.0 ns hold time t h2 5.0 ns d0 to d7 piclk (pclksel = 0) poclk (pclksel = 1) 51.44 ns valid data 2.0 v 0.8 v 1.5 v 1.5 v t su1 t h1 t su2 t h2
28 mb582a/583a reset input pulse width (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) pecl output waveform (v cc = +5.0 v 5.0 %,ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ. max. reset pulse width t wrst 100 ns parameter symbol conditions value unit min. typ.* max. do, do rise time t r 20 % ?0 % output load: 82 w to v cc 130 w to gnd 0.7 ns fall time t r 0.7 ns 0.8 v reset t wrst do, do 80 % 20 % t r t f
29 mb582a/583a external serial clock input timing (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ.* max. extclk ? poclk delay tphl clksel = ? 12.0 ns extclk ? poclk delay tphl clksel = ? 12.0 ns extclk ? do, do delay tpd clksel = ? 6.0 ns do, do poclk tphl tplh tpd extclk 1.5 v 1.5 v d7 -0 d6 -0 d5 -0 d4 -0 d3 -0 d2 -0 d1 -0 d0 -0 d7 -1 d6 -1 d5 -1 d4 -1 d3 -1 d2 -1
30 mb582a/583a (2) MB583A (receiver) parallel clock output and parallel data output timings (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c reset input pulse width (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) parameter symbol conditions value unit min. typ.* max. poclk ? do0 to do7 skew t skew ?.0 0 5.0 ns parameter symbol conditions value unit min. typ. max. reset pulse width t wrst 100 ns poclk do0 to do7 1.5 v 1.5 v t skew valid data reset 0.8 v t wrst
31 mb582a/583a external serial clock input timing (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ.* max. extclk ? d, d setup time t su clksel = ? 1.5 ns hold time t h 1.5 ns extclk ? poclk delay tphl1 clksel = ? 15.0 ns delay tplh2 15.0 ns extclk ? do0 to do7 delay tphl2 clksel = ? 15.0 ns delay tplh2 15.0 ns poclk d, d extclk do0 do7 t su t h tphl1 tphl2, tplh2 tplh1 d0 -0 d7 -1 d6 -1 d5 -1 d4 -1 d3 -1 d2 -1 d1 -1 d0 -1 d7 -2 d6 -2 d5 -2 d4 -2 d3 -2 d2 -2 d1 -2 d0 -2 d0-0 d0-1 d7-0 d7-1 1.5 v 1.5 v 1.5 v
32 mb582a/583a loss-state serial data timing (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ.* max. serial data loss state ? rx-ready delay t slos1 2.5 m s serial data loss state ? loso delay t slos2 2.5 m s serial data loss state ? poclk delay t slos3 10 m s serial data loss state ? do0 to do7 delay t slos4 10 m s serial data loss state ? sleep state delay t slos5 10 m s serial data rx-ready loso poclk do0 to 7 sleep state ? ? ? ? ? ? normal i cc reduced i cc t slos 1 t slos 2 t slos 3 t slos 4 t slos 5
33 mb582a/583a loss signal timing (v cc = +5.0 v 5.0 %, ta = ?0 c to +85 c ) * : typical values assume that v cc = +5.0 v and ta = +25 c. parameter symbol conditions value unit min. typ.* max. losi, tlosi ? rx-ready delay t losi1 20 ns losi, tlosi ? loso delay t losi2 20 ns losi, tlosi ? poclk delay t losi3 ? m s losi, tlosi ? do0 to do7 delay t losi4 ? m s losi, tlosi ? sleep mode delay t losi5 ? m s rx-ready loso poclk do0 to 7 sleep state ? ? normal i cc reduced i cc losi, tlosi 1.5 v 1.5 v 1.5 v t losi 2 t losi 3 t losi 4 t losi 5 t losi 1
34 mb582a/583a n application examples (1) when refclk = 19.44 mhz is used (without piclk) los trfd rdav rd0 rd7 rclk td0 td7 tclk open 19.44 mhz ? ? from optical transceiver or utp transceiver losi d d do do loso rx-ready do0 do7 poclk v cc 130 w refsel refclk 130 w 82 w v cc refsel refclk tx-ready d0 d7 poclk piclk pclksel mb86683 (ntc) MB583A (receiver) (transmitter) mb582a .... 82 w tlosi losi .... .... to optical transceiver or utp transceiver .... .... ....
35 mb582a/583a (2) when the mb582a uses piclk = 19.44 mhz (without refclk) and the MB583A uses refclk = 19.44 mhz los trfd rdav rd0 rd7 rclk td0 td7 tclk open 19.44 mhz ? ? from optical transceiver or utp transceiver losi d d do do loso rx-ready do0 do7 poclk v cc 130 w refsel refclk 130 w 82 w v cc refsel refclk tx-ready d0 d7 poclk piclk pclksel mb86683 (ntc) MB583A (receiver) (transmitter) mb582a .... 82 w tlosi losi .... .... to optical transceiver or utp transceiver .... .... .... open
36 mb582a/583a (3) when refclk = 51.84 mhz is used los trfd rdav rd0 rd7 rclk td0 td7 tclk open 51.84 mhz ? ? from optical transceiver or utp transceiver losi d d do do loso rx-ready do0 do7 poclk v cc 130 w refsel refclk 130 w 82 w v cc refsel refclk tx-ready d0 d7 poclk piclk pclksel mb86683 (ntc) MB583A (receiver) (transmitter) mb582a .... 82 w tlosi losi .... .... to optical transceiver or utp transceiver .... .... ....
37 mb582a/583a (4) when the external clock is used los trfd rdav rd0 rd7 rclk td0 td7 tclk open ? open from optical transceiver or utp transceiver losi d d do do loso rx-ready do0 do7 poclk v cc 130 w refsel refclk 130 w 82 w v cc refsel refclk tx-ready d0 d7 poclk piclk pclksel mb86683 (ntc) MB583A (receiver) (transmitter) mb582a .... 82 w tlosi losi .... .... to optical transceiver or utp transceiver .... .... .... open ? clksel extclk ? open v cc extclk 82 w 130 w clksel
38 mb582a/583a (5) when loopback is used 19.44 mhz ? ? from optical transceiver or utp transceiver losi d d do do do0 do7 poclk v cc 130 w refsel refclk 130 w 82 w v cc refsel refclk d0 d7 piclk pclksel MB583A (receiver) (transmitter) mb582a 82 w tlosi losi .... .... to optical transceiver or utp transceiver .... .... open ....
39 mb582a/583a (6) losi losi d d v cc 130 w MB583A (receiver) 82 w sd sd rd rd td td 130 w 82 w v cc (transmitter) mb582a losi losi d d v cc 130 w MB583A (receiver) 82 w sd+ sd rxout+ rxout txin+ txin 130 w 82 w v cc (transmitter) mb582a do do do do 130 w 82 w v cc d d v bb 0.1 m f 1 k w 0.1 m f 10 m f optical transceiver (example of connection for a single input from optical transceiver to MB583A) utp transceiver (example of connection with utp transceiver) optical transceiver (example of connection with optical transceiver) rd rd MB583A (receiver)
40 mb582a/583a n peripheral circuits mb582a (transmitter) *1: bypass capacitor for power supply, connected between analog gnd and analog v cc . *2: bypass capacitor for power supply, connected between digital gnd and digital v cc . *3: filter capacitor. *4: although resistance is 0 w , reserve agnd and av cc patterns. *5: capacitor for power-on reset. note: external elements should be located as closer to the relevant pins as possible. 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1234 56789101112 36 35 34 33 32 31 30 29 28 27 26 25 mb582a (top view) gnd v cc do v cc do gnd nc v cc nc refclk v cc gnd d0 d1 gnd v cc d2 d3 d4 d5 v cc gnd d6 d7 agnd av cc nc nc refsel nc fil1 fil2 v cc gnd gnd tx-ready gnd reset clksel extclk pdown timer v cc gnd pclksel piclk gnd poclk * 2 10 m f * 2 0.1 m f * 5 4.7 m f * 2 0.1 m f * 2 0.1 m f * 2 0.1 m f * 1 0.1 m f * 1 10 m f * 2 0.1 m f * 2 0.1 m f * 2 0.1 m f v cc * 4 * 4 * 3 1.0 nf * 2 0.1 m f
41 mb582a/583a MB583A (receiver) *1: bypass capacitor for power supply, connected between analog gnd and analog v cc . *2: bypass capacitor for power supply, connected between digital gnd and digital v cc . *3: filter capacitor. *4: although resistance is 0 w , reserve agnd and av cc patterns. *5: capacitor for power-on reset. note: external elements should be located as closer to the relevant pins as possible. 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 12 345 678 9101112 36 35 34 33 32 31 30 29 28 27 26 25 MB583A (top view) gnd v cc d v bb do gnd tlosi losi losi refclk v cc gnd do0 do1 gnd v cc do2 do3 do4 do5 v cc gnd do6 do7 agnd av cc clksel reset fil1 fil2 extclk loso v cc gnd gnd rx-ready gnd v cc nc nc timer refsel nc pdown v cc gnd gnd poclk * 2 10 m f * 5 4.7 m f * 2 0.1 m f * 2 0.1 m f * 1 0.1 m f * 1 10 m f * 2 0.1 m f * 2 0.1 m f * 2 0.1 m f v cc * 2 0.1 m f * 4 * 4 * 3 1.0 nf * 2 0.1 m f
42 mb582a/583a n precautions (1) for the v cc supplied to the mb582a/583a, use a stable power supply. if spike noise enters the power supply, the mb582a/583a may fail to perform stable operation. 1-1. the power supply for this lsi should be separated from the power supply for any other lsi not to receive digital noise (as shown in the following illustration). 1-2. to prevent spike noise from another lsis, add suf?ient capacitance also to another lsis (for example, 10 m f for each of the lsis). 1-3. connect a bypass capacitor of about 0.1 m f closer (as within 10 mm as possible) to the pins between each v cc and gnd. between av cc and agnd which are an analog v cc and an analog gnd, in particular, connect a bypass capacitor closer (within 10 mm) to the lsi pins. for the power source, attach a capacitor with a large value of about 10 m f to provide stable power. (2) a external ?ter capacitor between fil1 and fil2 must be placed closer (as within 15 mm as possible) to the lsi pins. this capacitor must be wired by minimum routing. the wiring should not cross any other pattern. the pins are particularly sensitive to external noise. placing this capacitor at lower-noise positions ensure their stable operations. in addition, routing gnd patterns around the pins and the capacitor greatly contributes to stable operation. (3) letting the wiring for reference clock signals supplied to the refclk and piclk cross other patterns increases jitter, leading to unstable operation. note also that input of a reference clock signal with large undershoot results in unstable operation. board v cc pin 10 m f or more 10 m f or more 4.7 m h or more 4.7 m h or more another logic lsi? v cc pattern transceiver? v cc pattern connection example 10 m f or more note: suppress the total voltage drop by the inductor to be 50 mv or less. (inductor allowable current = 0.5 a or more; inductor total dc resistance = 0.1 w or less)
43 mb582a/583a (4) serial data signals are transmitted at a high speed of 155.52 mbps. pay attention to the following points: 4-1. connect a serial data terminal resistor of 82 w to the v cc and of 130 w to the gnd. connect these terminal resistors closer to the receiving device side. (placing a terminal resistor far away from the receiving device causes signal re?ction, resulting in degradation of serial data.) 4-2. the serial data transmission line must have 50 w impedance. (inappropriate line impedance causes signal re?ction, resulting in degradation of serial data.) 4-3. do not bend the serial data transmission line with 90 . also, do not pass it through a through hole. (the through hole causes an impedance mismatch.) 4-4. the serial data transmission line should be minimum routed. (5) taking account of the above points, the board plane should be a four or more layers.
44 mb582a/583a n ordering information part number package remarks mb582apfv 48 pin plastic sqfp (fpt-48p-m05) MB583Apfv
45 mb582a/583a n package dimension c 1995 fujitsu limited f48013s-2c-5 0.10(.004) 0.500.08 (.0197.0031) 9.000.20(.354.008)sq 5.50 (.217) ref 8.00 (.315) nom .007 ?.001 +.003 ?0.03 +0.08 0.18 .005 ?.001 +.002 ?0.02 +0.05 0.127 .059 ?.004 +.008 ?0.10 +0.20 1.50 7.000.10(.276.004)sq "a" 0.500.20 (.020.008) 0.100.10 (.004.004) details of "a" part 0 10? 25 24 13 12 1 48 37 36 index lead no. (stand off) 48 pin, plastic lqfp (fpt-48p-m05) dimensions in mm(inches). (mounting height)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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