hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 1 pin assignment description the HMD1M4Z1 is a n 1 m x 4 bit s fast page mode cmos drams. fast page mode offers high speed random access of memory cells within the same row. power supply voltage (+5v ), access time ( - 5, - 6), power consumption(normal or low power), and pa ckage type ( zip) are optional features of this module . the HMD1M4Z1 have cas - before - ras refresh, ras - only refresh and hidden refresh capabilities. the HMD1M4Z1 is optimized for application to the systems, which are required high density and large capacit y such as main memory for main frames and mini computers, personal computer and high performance microprocessor systems. the HMD1M4Z1 provides common data and outputs. features w fast page mode operation w cas - before - ras refresh capability w ras - only and hidden refresh capability w fast parallel test mode capability w ttl(5v) c ompatible inputs and outputs w early write or output enable controlled write w available in 2 0 pin zip packages w single +5 v 10% power supply w 1,024 refresh cycles/16ms w performance range p in description pin symbol 1 /oe 2 /cas 3 dq2 4 dq3 5 v ss 6 dq 0 7 dq1 8 /we 9 /ras 10 a9 11 a0 12 a1 13 a2 14 a3 15 v cc 16 a4 17 a5 18 a6 19 a7 20 a8 speed t rac t cac t rc t pc HMD1M4Z1 - 5 50 15 90 35 HMD1M4Z1 - 6 60 15 1 10 40 pin function pin function a0 C a9 address inputs /we read/write enable dq0 C dq3 data input/output vcc power (+5v) /ras row address strobe vss ground /cas column address strobe nc no connection /oe data output enable 4mbit(1mx4bit) fast page mode, 1k refresh, 20pin zip, 5v design part no. hm d1m4z1
hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 2 absolute maximum rat ings * symbol parameter rating unit ta ambient temperature under bias 0 ~ 70 c tstg storage temperature (plastic) - 55 ~ 150 c vin/vout voltage on any pin relative to vss - 1.0 ~ 7.0 v vcc power supply voltage - 1.0 ~ 7.0 v io ut short circuit output current 50 ma pd power dissipation 600 mw * note: 1. stress greater than above absolute maximum ratings? may cause permanent damage to the device. recommended dc opera ting conditions (t a = 0 ~ 70c) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v * note: all voltages referenced to vcc dc and operating cha racteristics symbol parameter min max unit v oh output high l evel voltage ( i out = - 5ma) 2.4 v v ol output low level voltage ( i out = 4.2ma) 0 0.4 v - 5 85 i cc1 operating current (/ras,/cas,address cycling : t rc = t rc min) - 6 75 ma i cc2 standby current (/ras,/cas = v ih ) - 2 ma - 5 85 i cc3 /ras only refresh current ( /ras cycling, /cas = v ih ,: t rc = t rc min) - 6 75 ma - 5 65 i cc4 fast page mode current (/ras = v il , /cas, address cycling : tpc = tpc min) - 6 55 ma ma i cc5 standby current (/ras,/cas >= vcc C 0.2v) 1 ma - 5 85 i cc6 /cas before /ras refresh curre nt ( t rc = t rc min) - 6 75 ma i ccs self refresh current (/ras=/ucas=/lcas=v il , /we=/oe=a0~a9= vcc C 0.2v or 0.2v, dq0~dq31= vcc C 0.2v, 0.2v or open) - - ua i i(l) input leakage current (any input (0v<=v in <= v in + 0.5v, all other pins not under test = 0v) - 5 5 ua i o(l) output leakage current(dout is disabled, 0v<=v out <= vcc ) - 5 5 ua
hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 3 note: 1. icc depends on output load condition when the device is selected. icc (max) is specified at the output open condition. 2. address can be changed once or less while /ras = v il. 3. address can be changed once or less while /cas = v ih capacitance ( t a =25 o c, vcc = 5v +/ - 10% , f = 1m h z ) description symbol min max units note input capacitance (a0 - a 9 ) c i1 - 5 pf 1 input capacitance (/ w e, /ras , /cas0 - /cas3 ,/oe ) c i2 - 7 pf 1,2 input/output capacitance (dq0 - 31) c dq1 - 7 p f 1,2 note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. /cas = vih to disable dout. ac characterist ics ( 0 o c t a 70 o c , vcc = 5v 10%, v ih /v il = 2.4/0.8v, v o h /v ol =2.4/0.4v, see notes 1, 2) - 5 - 6 symbol parameter min max min max unit note t rc random read or write cycle time 90 110 ns t rwc read - modify - writer cycle time 132 152 ns t rac access time from /ras 50 60 ns 3,4,10 t cac access time from /cas 15 15 ns 3,4,5 t aa access time from column address 25 30 ns 3,10 t off output buffer turn - off time 0 12 0 12 ns 6 t t transition time (rise and fall) 3 50 3 50 ns 2 t rp /ras precharg e time 30 40 ns t ras /ras pulse width 50 10k 60 10k ns t rsh /ras hold time 15 15 ns t csh /cas hold time 50 60 ns t cas /cas pulse width 15 10k 15 10k ns t rcd /ras to /cas delay time 20 35 20 45 ns 4 t rad /ras to column address delay time 15 25 15 30 ns 10 t crp /cas to /ras precharge time 5 5 ns t asr row address setup time 0 0 ns t rah row address hold time 10 10 ns t asc column address setup time 0 0 ns 11 t cah column address hold time 10 10 ns 11 t ral column address to /ras lead time 25 30 ns t rcs read command setup time 0 0 ns
hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 4 t rch read command hold time to /cas 0 0 ns 8 t rrh read command hold time to /ras 0 0 ns 8 t wch write command hold time 10 10 ns t wp write command pulse width 10 10 ns t rwl write command to /ras lead time 15 15 ns t cwl write command to /cas lead time 13 15 ns t ds data - in setup time 0 0 ns 9 t dh data - in hold time 10 10 ns 9 t ref refresh period (1024 cycle) 16 16 ms t wcs write command setup time 0 0 ms 7 t cwd /ca s to /we delay time 37 37 ms 7,13 t rwd /ras to /we delay time 72 82 ns 7 t awd column address to /we delay time 47 52 ns 7 t cpwd /cas precharge to /we delay time 52 57 ns 7 t csr /cas setup time (/cas - before - /ras refresh cycle) 10 10 ns 15 t ch r /cas hold time (/cas - before - /ras refresh cycle) 10 10 ns 16 t rpc /ras precharge to /cas hold time 5 5 ns t cpa access time from /cas precharge 30 35 ns 3 t pc fast page mode cycle time 35 40 ns t cp fast page mode /ras precharge time 10 10 n s 12 t rasp fast page mode /cas pulse time 50 200k 60 200k ns t rhcp /ras hold time time from /cas precharge 30 35 ns t oea /oe access time 15 15 ns 3 t oed /oe to data delay 12 12 ns t oez output buffer turn off delay time from /oe 0 12 0 12 ns t oeh /oe command hold time 15 15 ns t rass /ras pulse width(cbr self refresh) 100 100 us t prs /ras precharge time(cbr self refresh) 90 110 ns t chs /cas hold time(cbr self refresh) - 50 - 50 ns note: 1. an initial pause of 200us is required a fter power - up followed by any 8 /ras - only refresh or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. input voltage levels are v ih / v il. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between . v ih and v il are assumed to be 5ns for all inputs. 3. measured with a load circuit equivalent to 2ttl loads and 100pf.
hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 5 4. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max ) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd <= t rcd (max). 6. this parameter defines the time at which the output achieves the o pen circuit condition and is not referenced to v oh / v ol . 7. t wcs, t rwd, t cwd, t cpwd are non restrictive operating parameter. they are included in the data sheet as electrical characteristics only. if t wcs >= t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. if t cwd >= t cwd (min), t rwd >= t rwd (min), t cpwd >= t cpwd (min), then the cycle is a read - modify - write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. either t rch or t rrh must be satisfied for a read cycles. 9. these parameters are referenced to /cas falling edge in early wr ite cycles and to /we falling edge in /oe controlled write cycle and read - modify - write cycles. 10. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater th an the specified t rad (max) limit, then access time is controlled exclusively by t aa . 11. t asc, t cah are are referenced to the earlier /cas falling edge. 12. t cp is specified from the later /cas rising edge in the previous cycle to the earlier /c as falling edge in the next cycle. 13. t cwd is referenced to the later /cas falling edge at word read - modify - write cycle. 14. t cwl is specified from /we falling edge to the earlier /cas rising edge . 15. t csr is referenced to the earlier /ca s falling edge before /ras transition low. 16. t chr is referenced to the later /cas rising edge after /ras transition low. p ackaging information
hanbit HMD1M4Z1 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0(august.2002) 6 o r dering information part number density org. package component number vcc mode speed HMD1M4Z1 - 5 4mbit 1m x 4bit 20 pin - zip 1ea 5v fp 50ns HMD1M4Z1 - 6 4mbit 1m x 4bit 20 pin - zip 1ea 5v fp 60ns 1. 8 0. 30 mm 2.5 4 mm 97. 80 0. 20 1.94 0.20 1.27 0.20 1.94 0 .20
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