pin functions a0~a18 address inputs d0~d31 data inputs/outputs cs1~4 chip select oe output enable we1~4 write enable nc no connect v cc power (+5v) gnd ground 512k x 32 sram module puma 2/77s16000/a - 020/025/35 issue 4.4 : april 2001 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 a0~a18 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram we oe description available in pga (puma 2 ) and gullwing (puma 77) footprints, the puma **s16000 is a 16 mbit sram module user configurable as 512k x 32, 1m x 16 or 2m x 8. the device is available with fast access times of 20,25 and 30ns. a low power standby and data retention mode is available. the device may be screened in accordance with mil-std-883. 16,777,216 bit cmos high speed static ram features ? 16mbit fast sram module. fast access times of 20/25/35ns. configurable as 8 / 16 / 32 bit wide output. operating power 1980 / 2640 / 3960 mw (max). standby ttl 1320mw (max). single 5v 10% power supply. ttl compatible inputs and outputs. may be screened in accordance with mil-std-883. puma 2 - 66 pin ceramic pga puma77 - 68 pin ceramic gullwing block diagram puma 77s16000 block diagram puma 2s16000 and 77s16000a, 77s16000b elm road, west chirton, north shields, tyne & wear ne29 8se, england tel. +44 (0191) 2930500 fax. +44 (0191) 2590997 we4 we3 we2 we1 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 a0~a18 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram oe
issue 4.3 : april 2001 puma 2/77s16000/a - 020/025/35 2 dc electrical characteristics (v cc =5v10%,t a =-55 c to +125 c) parameter symbol test condition min typ (1) max unit input leakage current address,oe i li1 v in = 0v to v cc -8 - 8 a we, cs i li2 v in = 0v to v cc -2 - 2 a output leakage current i lo cs (2) = v ih or oe = v ih , v i/o = 0v to v cc -8 - 8 a we (2) = v il average supply current 32 bit i cc32 cs (2) = v il , minumum cycle, i i/o = 0ma we (2) =v il or we (2) =oe=v ih , 100% duty. - - 720 ma 16 bit i cc16 as above - - 480 ma 8 bit i cc8 as above - - 360 ma standby supply current ttl levels i sb cs (2) = v ih , v cc =5.5v - - 240 ma output voltage low v ol i ol = 8.0 ma - - 0.4 v output voltage high v oh i oh = -4.0 ma 2.4 - - v notes: (1) typical values are at v cc =5.0v,t a =25 c and specified loading. (2) cs and we above are accessed through cs1~4 and we1~4 respectively. these inputs must be operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. dc operating conditions absolute maximum ratings (1) voltage on any pin relative to v ss (2) v t -0.5v to +7.0 v power dissipation p d 4w storage temperature t stg -55 to +150 c notes (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - v cc +0.5 v input low voltage v il -0.5 - 0.8 v operating temperature t a 0-70 c t ai -40 - 85 c (suffix i ) t am -55 - 125 c (suffix m , mb )
puma 2/77s16000 - 020/025/35 issue 4.3 april 2001 3 operating modes the table below shows the logic inputs required to control the operating modes of each of the srams on the device. mode cs oe we v cc current i/o pin reference cycle not selected 1 x x i sb1 ,i sb2 high z power down output disable 0 1 1 i cc high z read 0 0 1 i cc d out read cycle write 0 x 0 i cc d in write cycle note: cs above is accessed through cs1~4 and we is accessed through we1~4. for correct operation, cs1~ 4 and we1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. 1 = v ih , 0 = v il , x = don't care 166 30pf i/o pin 1.76v ? ac test conditions output load *input pulse levels: 0.0v to 3.0v *input rise and fall times: 3 ns *input and output timing reference levels: 1.5v *v cc =5v10% *puma module is tested in 32 bit mode. capacitance (v cc =5v10%,t a =25 c) note: these parameters are calculated and not measured. parameter symbol test condition typ max unit input capacitance address, oe c in1 v in =0v - 34 pf we1~4, cs1~4 c in2 v in =0v - 6 pf i/o capacitance d0~31 c i/o v i/o =0v - 42 pf (8 bit mode)
issue 4.3 : april 2001 puma 2/77s16000/a - 020/025/35 4 ac operating conditions read cycle 020 025 35 parameter symbol min max min max min max units read cycle time t rc 20 - 25 - 35 - ns address access time t aa -20-25-35ns chip select access time t acs -20-25-35ns output enable to output valid t oe -10-15-15ns output hold from address change t oh 5-5-5-ns chip selection to output in low z t clz 5-5-5-ns output enable to output in low z t olz 5-0-0-ns chip deselection to output in high z (3) t chz -10010010ns output disable to output in high z (3) t ohz 010010010ns write cycle 020 025 35 parameter symbol min max min max min max unit write cycle time t wc 20 - 25 - 35 - ns chip selection to end of write t cw 15 15 - 15 - ns address valid to end of write t aw 15 - 15 - 15 - ns address setup time t as 0-0-0-ns write pulse width t wp 15 - 15 - 15 - ns write recovery time t wr 0-0-0-ns write to output in high z t whz 010010010ns data to write time overlap t dw 10 - 10 - 10 - ns data hold from write time t dh 0-0-0-ns output active from end of write t ow 5-5-5-ns
puma 2/77s16000 - 020/025/35 issue 4.3 april 2001 5 notes: (1) during the read cycle, we is high for the module. (2) address valid prior to or coincident with cs transition low. (3) t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. read cycle timing waveform (1,2) write cycle no.1 timing waveform t as(3) t aw t cw(4) t wc a0~a18 oe cs1~4 t wp(1) t ohz(3,9) we1~4 d0~31out t t dw dh d0~31in (6) t wr (2) t ow high-z high-z t t t t rc aa oe oh address oe cs1~4 t ohz(3) t olz t acs t clz t chz(3) data valid d0~31 high-z
issue 4.3 : april 2001 puma 2/77s16000/a - 020/025/35 6 write cycle no.2 timing waveform (5) cs1~4 t wr(2) t cw (4) (6) t aw t wc a0~a18 t t t wp(1) dw t dh we1~4 d0~31out d0~31in whz(3,9) t as(3) t ow t oh (7) (8) high-z high-z ac characteristics notes (1) a write occurs during the overlap (t wp ) of a low cs and a low we. (2) t wr is measured from the earlier of cs or we going high to the end of write cycle. (3) during this period, i/o pins are in the output state. input signals out of phase must not be applied. (4) if the cs low transition occurs simultaneously with the we low transition or after the we low transition, outputs remain in a high impedance state. (5) oe is continuously low. (oe=v il ) (6) d out is in the same phase as written data of this write cycle. (7) d out is the read data of next address. (8) if cs is low during this period, i/o pins are in the output state. input signals out of phase must not be applied. (9) t whz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. low v cc data retention timing waveform t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs1~4 v dr cs1~4 vcc-0.2v
puma 2/77s16000 - 020/025/35 issue 4.3 april 2001 7 package details puma 2s16000 0.10 (0.004) 24.13 (0.950) sq. 20.57 (0.810) sq. 1.27 (0.050) 0.43 (0.017) 1.78 (0.070) 5.44 (0.214) max 25.15 (0.990) sq. 22.61 (0.890) sq. 0.76 (0.030) 24.67 (0.970) sq. 22.10 (0.870) sq. 20.10 (0.790) sq. 23.62 (0.930) sq. puma 77s16000 solder over 50 to 350 in ch nickel lead finish is 300 inch minimum 15.24 (0.60) typ 27.69 (1.090) square 4.83 (0.190) 4.32 (0.170) 1.27 (0.050) 1.52 (0.060) 27.08 (1.066) square 6.86 (0.270) max 1.27 (0.050) 1.66 (0.026) 10.67 (0.420) 10.16 (0.400) 2.54 (0.010) 3.81 (0.150) ref 2.54 (0.010) 1.02 (0.040) 0.53 (0.021) 0.38 (0.015)
pin definitions puma 77s16000 puma 77s16000a 1 12 23 view from above 2 13 24 3 14 25 4 15 26 5 16 27 6 17 28 7 18 29 8 19 30 9 20 31 10 21 32 11 22 33 34 45 56 35 46 57 36 47 58 37 48 59 38 49 60 39 50 61 40 51 62 41 52 63 42 53 64 43 54 65 44 55 66 d8 we2 d15 d9 cs2 d14 d10 gnd d13 a13 d11 d12 a14 a10 oe a15 a11 a17 a16 a12 we1 a18 vcc d7 d0 cs1 d6 d1 nc d5 d2 d3 d4 d24 vcc d31 d25 cs4 d30 d26 we4 d29 a6 d27 d28 a7 a3 a0 nc a4 a1 a8 a5 a2 a9 we3 d23 d16 cs3 d22 d17 gnd d21 d18 d19 d20 d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 nc a0 a1 a2 a3 a4 a5 gnd a6 a7 a8 a9 a10 vcc cs3 cs4 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 oe cs2 a18 gnd vcc a11 a12 a13 a14 a15 a16 cs1 nc a17 we2 we3 we4 we1 view from above d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 nc a0 a1 a2 a3 a4 a5 gnd a6 a7 a8 a9 a10 vcc cs3 cs4 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 oe cs2 a18 gnd vcc a11 a12 a13 a14 a15 a16 cs1 nc a17 nc nc nc we view from above puma 2s16000 44 nc a0 a1 a2 a3 a4 a5 cs3 gnd cs4 we1 a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 view from above vcc a11 a12 a13 a14 a15 a16 cs1 oe cs2 we3 we4 nc 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 we2 nc a18 a17 puma 77s16000b
military screening procedure multichip screening flow for high reliability product in accordance with mil-883 method 5004 shown below visual and mechanical internal visual 2017 condition b or manufacturers equivalent 100% temperature cycle 1010 condition b (10 cycles,-55 c to +125 c) 100% constant acceleration 2001 condition e (y 1 only) (10,000g) 100% burn-in pre-burn-in electrical per applicable device specifications at t a =+25 c 100% burn-in method 1015,condition d,t a =+125 c,160hrs min 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post burn-in at t a =+25 c 10% hermeticity 1014 fine condition a 100% gross condition c 100% quality conformance per applicable device specification sample external visual 2009 per vendor or customer specification 100% screen test method level mb multichip module screening flow
issue 4.3 : april 2001 puma 2/77s16000/a - 020/025/35 10 ordering information puma 2s16000amb-020 speed 020 = 20 ns 025 = 25 ns 35 = 35 ns temp. range/screeningblank = commercial temperature i = industrial temperature m = military temperature mb = processed in accordance with mil-std-883 we option blank = single we (puma 77 only) we1~4 (puma 2 only) a = we1~4(puma 77 only) b = pinout variant organisation 16000 = 512kx 32, user confiurable as 1m x 16 and 2m x 8 technology s = sram memory package puma 2 = jedec 66 pin ceramic pga package puma 77 = jedec 68 leaded gull wing ceramic surface mount package note : although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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