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dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 1 precision 8-ch/dual 4-ch low voltage analog multiplexers features benefits applications pin-for-pin compatibility with dg408/409 2.7- to 12-v single supply or 3- to 6-v dual supply operation lower on-resistance: r ds(on) - 17 typ. fast switching: t on - 38 ns, t off - 18 ns break-before-make guaranteed low leakage: i s(off) - 0.2 na max. low charge injection: 1 pc ttl, cmos, lv logic (3 v) compatible -82 db off-isolation at 1 mhz 2000-v esd protection (hbm) high accuracy single and dual power rail capacity wide operating voltage range simple logic interface data acquisition systems battery operated equipment portable test equipment sample and hold circuits communication systems sdsl, dslam audio and video signal routing description the dg408l/409l are low voltage pin -for-pin compatible companion devices to the industry standard dg408/409 with improved performance. using bicmos wafer fabrication technology allows the dg408l/409l to operate on single and dual supplies. single supply voltage ranges from 3- to 12-v while dual supply operation is recommended with 3 to 6 v. the dg408l is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). the dg409l is a dual 4-channel dif ferential analog multiplexer designed to connect one of four dif ferential inputs to a common dual output as determined by its 2-bit binary address (a 0 , a 1 ). break-before-make switching action to protect against momentary crosstalk between adjacent channels. the dg408l/409l provides lower on-resistance, faster switching time, lower leakage, less power consumption and higher off-isolation than the dg408/409. functional block diagrams and pin configurations s 3 a 0 s 6 d s 4 a 1 s 8 s 7 en dual-in- line, soic and tssop a 2 v- gnd s 1 v+ s 2 s 5 decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 a 0 d a a 1 d b en gnd v- v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg408l dg409l dual-in- line, soic and tssop
dg408l/409l vishay siliconix www.vishay.com 2 document number: 71342 s-03720?rev. d, 07-apr-03 truth tables and ordering information truth table dg408l a 2 a 1 a 0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 truth table dg409l a 1 a 0 en on switch x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 logic ?0? = v al 0.8 v logic ? 1 ? =v ah 24 v logic ?1? = v ah 2.4 v x = don?t care for low and high voltage levels for v ax and v en consult ?digital control? parameters for specific v+ operation. ordering information dg408l temp range package part number 40 to 85 c 16-pin soic dg408ldy - 40 to 85 c 16-pin tssop dg408ldq 16 pin cerdip dg408lak - 55 to 125 c 16-pin cerdip dg408lak/883 lcc-20* dg408laz/883 *block diagram and pin configuration not shown. ordering information dg409l temp range package part number 40 to 85 c 16-pin soic dg409ldy - 40 to 85 c 16-pin tssop dg409ldq 16 pin cerdip dg409lak - 55 to 125 c 16-pin cerdip dg409lak/883 lcc-20* dg409laz/883 *block diagram and pin configuration not shown. absolute maximum ratings voltage referenced to v - v+ 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v - ) - 0.3 v to (v+) +0.3 v . . . . . . . . . . . . . . . . . . . . . . current (any terminal) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . storage temperature: (a suffix) - 65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . (d suffix) - 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) b 16-pin plastic tssop c 650 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow soic c 600 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin cerdip d 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lcc-20 e 750 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. signals on s x , d x, a x , or en exceeding v+ or v - will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 7.6 mw/ c above 75 c. d. derate 12 mw/ c above 75 c. e. derate 10 mw/ c above 75 c.
dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 3 specifications (single supply 12 v) test conditions unless otherwise specified v+ 12 v 10% v 0 v a suffix - 55 to 125 c d suffix - 40 to 85 c parameter symbol v+ = 12 v, 10%, v - = 0 v v en = 0.8 v or 2.4 v f temp b typ d min c max c min c max c unit analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = 10.8 v, v d = 2 v or 9 v, i s = 10 ma sequence each switch on room full 17 29 38 29 35 r ds(on) matching between channels g r ds v d = 10.8 v, v d = 2 v or 9 v, i s = 10 ma room 1 3 3 on-resistance flatness i r flat(on) v d = 10 . 8 v , v d = 2 v or 9 v , i s = 10 ma room 3 7 7 switch off leakage current i s(off) v en = 0 v, v d = 11 v or 1 v room full -1 -15 1 15 -1 -10 1 10 switch off leakage current i d(off) v en = 0 v , v d = 11 v or 1 v v s = 1 v or 11 v room full -1 -15 1 15 -1 -10 1 10 na channel on leakage current i d(on) v s = v d = 1 v or 11 v room full -1 -15 1 15 -1 -10 1 10 digital control logic high input v oltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.8 0.8 v input current i in v ax = v en = 2.4 v or 0.8 v full - 1.5 1.5 -1 1 a dynamic characteristics transition time t trans v s1 = 8 v, v s8 = 0 v, (dg408l) v s1b = 8 v, v s4b = 0 v, (dg409l) see figure 2 room full 30 60 68 60 65 break-before-make time t open v s(all) = v da = 5 v, see figure 4 room full 11 1 1 ns enable t urn-on time t on(en) v ax = 0 v, v s1 = 5 v (dg408l) v ax = 0 v v s1b = 5 v (dg409l) room full 38 55 60 55 60 ns enable t urn-off time t off(en) v ax = 0 v, v s1b = 5 v (dg409l) see figure 3 room full 18 25 35 25 30 charge injection e q c l = 1 nf, v gen = 0 v, r gen = 0 room 1 5 5 pc off isolation e, h oirr f = 100 khz r l = 1 k room -82 db source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 7 drain off capacitance e c d(off) f = 1 mhz, v d = 2.4 v, v en = 0 v room 20 pf drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v (dg409l only) room 31 p f power supplies power supply range v+ 3 12 3 12 v power supply current i+ v en = v a = 0 v or 5 v room 0.2 0.7 0.7 ma
dg408l/409l vishay siliconix www.vishay.com 4 document number: 71342 s-03720?rev. d, 07-apr-03 specifications (dual supply v+ = 5 v, v = 5 v) test conditions unless otherwise specified v+ 5 v v 5 v 10% v 0 v a suffix - 55 to 125 c d suffix - 40 to 85 c parameter symbol v+ = 5 v, v - = - 5 v 10%, v - = 0 v v en = 0.6 v or 2.4 v f temp b typ d min c max c min c max c unit analog switch analog signal range e v analog full -5 5 -5 5 v drain-source on-resistance r ds(on) v d = 3.5 v, i s = 10 ma sequence each switch on room full 20 40 50 40 50 switch off leakage current a i s(off) v+ = 5.5 v, v - = 5.5 v room full -1 -15 1 15 -1 -10 1 10 switch off leakage current a i d(off) v+ = 5 . 5 v , v - = 5 . 5 v v en = 0 v, v d = 4.5 v, v s = 4.5 v room full -1 -15 1 15 -1 -10 1 10 na channel on leakage current a i d(on) v+ = 5.5 v, v - = 5.5 v v en = 2.4 v, v d = 4.5 v, v s = 4.5 v room full -1 -15 1 15 -1 -10 1 10 digital control logic high input v oltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.6 0.6 v input current a i in v ax = v en = 2.4 v or 0.6 v full - 1.5 1.5 -1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = - 3.5 v, (dg408l) v s1b = 3.5 v, v s4b = - 3.5 v, (dg409l) see figure 2 room full 30 60 78 60 65 break-before-make time e t open v s(all) = v da = 3.5 v, see figure 4 room full 8 1 1 ns enable t urn-on time e t on(en) v ax = 0 v, v s1 = 3.5 v (dg408l) v ax = 0 v v s1b = 3 5 v (dg409l) room full 25 55 68 55 60 ns enable t urn-off time e t off(en) v ax = 0 v, v s1b = 3.5 v (dg409l) see figure 3 room full 20 40 50 40 45 source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 6 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 15 pf drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v room 29 pf
dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 5 specifications (single supply 5 v) test conditions unless otherwise specified a suffix - 55 to 125 c d suffix - 40 to 85 c parameter symbol v+ = 5 v, 10%, v - = 0 v v en = 0.6 v or 2.4 v f temp b typ d min c max c min c max c unit analog switch analog signal range e v analog full 0 5 0 5 v drain-source on-resistance r ds(on) v+ = 4.5 v, v d or v s = 1 v or 3.5 v, i d = 5 ma room full 35 49 62 40 62 r ds(on) matching between channels g r ds v+ = 4.5 v, v d = 1 v or 3.5 v, i s = 5 ma room 1.5 3 3 on-resistance flatness i r flat(on) v+ = 4 . 5 v , v d = 1 v or 3 . 5 v , i s = 5 ma room 4 4 switch off leakage current a i s(off) v+ = 5.5 v, v s = 1 v or 4 v room full -1 -15 1 15 -1 -10 1 10 switch off leakage current a i d(off) v+ = 5 . 5 v , v s = 1 v or 4 v v d = 4 v or 1 v room full -1 -15 1 15 -1 -10 1 10 na channel on leakage current a i d(on) v+ = 5.5 v, v d = v s = 1 v or 4 v sequence each switch on room full -1 -15 1 15 -1 -10 1 10 digital control logic high input v oltage v inh v+ = 5 v full 2.4 2.4 v logic low input voltage v inl v + = 5 v full 0.6 0.6 v input current a i in v ax = v en = 2.4 v or 0.6 v full - 1.5 1.5 -1 1 a dynamic characteristics transition time e t trans v s1 = 3.5 v, v s8 = 0 v, (dg408l) v s1b = 3.5 v, v s4b = 0 v, (dg409l) see figure 2 room full 44 125 138 125 135 break-before-make time e t open v s(all) = v da = 3.5 v, see figure 4 room full 17 1 1 ns enable t urn-on time e t on(en) v ax = 0 v, v s1 = 3.5 v (dg408l) v ax = 0 v v s1b = 3 5 v (dg409l) room full 43 60 70 60 65 ns enable t urn-off time e t off(en) v ax = 0 v, v s1b = 3.5 v (dg409l) see figure 3 room full 26 45 60 45 50 charge injection e q c l = 1 nf, r gen = 0 , v gen = 0 v room 1 5 5 pc off isolation e, h oirr r l = 1 k f = 100 khz room -70 db crosstalk e x talk r l = 1 k f = 100 khz room -80 db source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 8 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 21 pf drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v (dg409l only) room 32 p f
dg408l/409l vishay siliconix www.vishay.com 6 document number: 71342 s-03720?rev. d, 07-apr-03 specifications (single supply 3 v) test conditions unless otherwise specified a suffix - 55 to 125 c d suffix - 40 to 85 c parameter symbol v+ = 3 v, 10%, v - = 0 v v en = 0.4 v or 2.0 v f temp b typ d min c max c min c max c unit analog switch analog signal range e v analog full 0 3 0 3 v drain-source on-resistance r ds(on) v+ = 2.7 v, v d = 0.5 or 2.2 v, i s = 5 ma room full 60 80 105 80 100 switch off leakage current a i s(off) v+ = 3 3 v v s = 2 or 1 v v d = 1 or 2 v room full -1 -15 1 15 -1 -10 1 10 switch off leakage current a i d(off) v+ = 3.3 v, v s = 2 or 1 v, v d = 1 or 2 v room full -1 -15 1 15 -1 -10 1 10 na channel on leakage current a i d(on) v+ = 3.3 v, v d = v s = 1 or 2 v sequence each switch on room full -1 -15 1 15 -1 -10 1 10 digital control logic high input v oltage v inh full 2 2 v logic low input voltage v inl full 0.4 0.4 v input current a i in v ax = v en = 2.4 v or 0.4 v full - 1.5 1.5 -1 1 a dynamic characteristics transition time t trans v s1 = 1.5 v, v s8 = 0 v, (dg408l) v s1b = 1.5 v, v s4b = 0 v, (dg409l) see figure 2 room full 75 150 175 150 175 break-before-make time t open v s(all) = v da = 1.5 v, see figure 4 room full 32 1 1 ns enable t urn-on time t on(en) v ax = 0 v, v s1 = 1.5 v (dg408l) v ax = 0 v v s1b = 1 5 v (dg409l) room full 70 95 115 95 105 ns enable t urn-off time t off(en) v ax = 0 v, v s1b = 1.5 v (dg409l) see figure 3 room full 55 100 115 100 105 charge injection e q c l = 1 nf, r gen = 0 , v gen = 0 v room 0.4 5 5 pc off isolation e, h oirr f = 100 khz r l = 1 k room -79 db source off capacitance e c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 8 drain off capacitance e c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 19 pf drain on capacitance e c d(on) f = 1 mhz, v d = 0 v, v en = 2 v (dg409l only) room 33 p f notes a. leakage parameters are guaranteed by worst case test condition and not subject to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r ds(on) = r ds(on) max - r ds(on) min. h. worst case isolation occurs on channel 4 do to proximity to the drain pin. i. r ds(on) flatness is measured as the difference between the minimum and maximum measured values across a defined analog signal.
dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 7 typical characteristics (25 c unless noted) 0 5 10 15 20 25 30 35 -6 -4 -2 0 2 4 6 25 c r ds(on) vs. v d and t emperature r ds9on) - drain-source on-resistnace ( ) v d - drain voltage (v) -55 c 85 c 125 c 0 10 20 30 40 50 60 70 80 024681012 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 4 6 8 10 12 14 0 5 10 15 20 25 -5 -3 -1 1 3 5 r ds(on) vs. v d and power supply input threshold vs. v+ supply v oltage v d - drain voltage (v) v+ - positive supply voltage (v) v+ = 2.7 v r ds9on) - drain-source on-resistnace ( ) v+ = 4.5 v v+ = 12 v r ds9on) - drain-source on-resistnace ( ) r ds(on) vs. v d and power supply v d - drain voltage (v) v+ = 5 v v- = - 5 v v t (v) 0 10 20 30 40 50 0123456 25 c r ds(on) vs. v d and t emperature r ds9on) - drain-source on-resistnace ( ) v d - drain voltage (v) -55 c 85 c 125 c upper threshold limit low threshold limit 0 10 20 30 40 50 60 70 0 2 4 6 8 10 12 14 switching time vs. positive supply v oltage v+ - positive supply voltage (v) switching speed (ns) t on t trans t off
dg408l/409l vishay siliconix www.vishay.com 8 document number: 71342 s-03720?rev. d, 07-apr-03 typical characteristics (25 c unless noted) 0.0 0.2 0.4 0.6 0.8 1.0 -5 0 5 10 -40 -30 -20 -10 0 10 -5 -3 -1 1 3 5 leakage current vs. analog voltage v d , v s - analog voltage (v) charge injection vs. analog v oltage leakage current (pa) q - charge injection (pc) v s - source voltage (v) i s(off) i d(on) i d(off) v+ = 5 v v- = - 5 v v+ = 5 v v- = 0 v v+ = 12 v v- = 0 v 0 5 10 15 20 25 30 35 40 3456 switching time vs. dual power supply voltage - dual power supply voltage (v) switching speed (ns) t trans t on t off c l = 1000 pf 0.1 -110 1 -30 10 -70 -50 100 1000 -90 loss (db) insertion loss, off isolation and crosstalk vs. frequency (single supply) v+ = 3 v v- = 0 v r l = 50 off isolation crosstalk insertion loss - 3 db = 280 mhz 10 -10 frequency (mhz) c d , c s - drain/source capacitance (pf) 0 5 10 15 20 25 30 35 024681012 0 5 10 15 20 25 30 35 -5 -4 -3 -2 -1 0 1 2 3 4 5 drain/source capacitance vs. analog v oltage c s(off) c d , c s - drain/source capacitance (pf) v+ = 12 v v- = 0 v c d(off) c d(on) v+ = 5 v v- = - 5 v c s(off) c d(off) c d(on) drain/source capacitance vs. analog v oltage
dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 9 schematic diagram (typical channel) figure 1. en a 0 s 1 d v+ s n v- decode/ drive level shift v- v+ a x gnd v+ test circuits figure 2. transition time a 1 a 0 a 2 a 1 a 0 v+ v- en v+ v- gnd d 35 pf v o s 1 s 2 - s 7 s 8 50 300 v s8 v s1 v+ v- en v+ v- gnd 35 pf v o s 1b s 1a - s 4a , d a s 4b 300 d b logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on (dg408l) or s 4 on (dg409l) s 1 on t trans 50% v s1 50% 90% 90% 3 v 0 v dg408l dg409l v sb4 v s1 3 v 3 v v ax 50
dg408l/409l vishay siliconix www.vishay.com 10 document number: 71342 s-03720?rev. d, 07-apr-03 test circuits figure 3. enable switching time logic input switch output v o t r <20 ns t f <20 ns 3 v 0 v 0 v t off(en) t on(en) 50% 90% 10% v o en s 1 s 2 - s 8 a 0 a 1 a 2 50 300 v o v+ gnd v- d 35 pf v- v+ s 1b s 1a - s 4a , d a s 2b - s 4b d b en a 0 a 1 50 300 v o v+ gnd v- 35 pf v- dg408l dg409l v s1 v+ v s1 figure 4. break-before-make interval 50% 80% logic input switch output v o v s t open t r <20 ns t f <20 ns 0 v 3 v 0 v en v+ gnd v- 35 pf v- 3 v a 2 d b , d all s and d a 300 v o 50 bbm.5 4/9 a 1 a 0 dg408l dg409l v s1
dg408l/409l vishay siliconix document number: 71342 s-03720?rev. d, 07-apr-03 www.vishay.com 11 test circuits figure 5. charge injection a 0 en a 1 a 2 v o v+ gnd v- d v g r g s x c l 1 nf channel select 3 v 0 v off on logic input switch output v o v o is the measured voltage due to charge transfer error q, when the channel turns off. q = c l x v o off figure 6. off isolation figure 7. crosstalk r l 1 k v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 off isolation = 20 log v out v in v in r l 1 k v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 crosstalk = 20 log v out v in v in s 1 v+ v+ v- v- v+ v- figure 8. insertion loss r l 1 k a 2 v o d r g = 50 insertion loss = 20 log v out a 1 v in a 0 v s s 1 v+ gnd v- en figure 9. source drain capacitance f = 1 mhz s 1 d en gnd v+ v- meter hp4192a impedance analyzer or equivalent s 8 a 1 a 2 a 0 channel select v- v- v+ v+

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