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part number 440sp revision 1.23 - sept 26, 2006 amcc proprietary 1 powerpc 440sp embedded processor data sheet features ?powerpc ? 440 processor core operating at up to 667mhz with 32-kb i- and d-caches (with parity checking) ? on-chip 256-kb sram configurable as l2 cache or ethernet packet/code store memory ? selectable processor:bus clock ratios (refer to the clocking chapter in the ppc440sp embedded processor user?s manual for details) ? supports up to 4 gb (2 chip selects) of 64-bit/32- bit sdram with ecc ? ddr1 266-333-400 ? ddr2 400-533-667 ? three ddr pci-x interfaces (32-bit or 64-bit) up to 133 mhz (ddr 266) with support for conventional pci ? xor accelerator with dma controller ? optional: high throughput raid 6 hardware acceleration, performs xor and galois field p & q parity computations, supports up to 255 drives ? i2o messaging unit with two dma controllers ? external peripheral bus (24-bit address, 8-bit data) for up to three devices ? one ethernet 10/100/1000 mbps half- or full- duplex interface. operational modes supported are mii and gmii. ? programmable interrupt controller supports interrupts from a variety of sources. ? programmable general purpose timers (gpt) ? three serial ports (16750 compatible uart) ? two iic interfaces ? general purpose i/o (gpio) interface available ? jtag interface for board level testing ? processor can boot from pci memory description designed specifically to address high-end embedded applications for storage, the powerpc 440sp embedded processor (ppc440sp) provides a high- performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. this chip contains a high-performance risc processor core, a ddr2 sdram controller, configurable 256kb sram to be used as l2 cache or software-controlled on-chip memory, three ddr pci-x bus interfaces, an ethernet interface, an i2o/dma controller, control for external rom and peripherals, optional raid 6 acceleration, an xor dma unit, serial ports, iic interfaces, and general purpose i/o. technology: cmos cu-11, 0.13mm package: 29mm, 783-ball, 1mm pitch, flip chip- plastic ball grid array (fc-pbga) power (estimated): less than 6w @533mhz supply voltages required: 3.3v, 2.5v, 1.8v, 1.5v
powerpc 440sp embedded processor 2 amcc proprietary revision 1.23 - sept 26, 2006 data sheet contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ppc440sp functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 powerpc 440 processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 on-chip sram/l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ddr pci-x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ddr1/ddr2 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ethernet controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 i2o/dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 optional raid 5 and raid 6 acceleration hard ware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 xor/dma2 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 29mm, 783-ball fc-pbga core package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 clock test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 clock timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ddr sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 serial bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 3 data sheet figures figure 1. order part number key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. ppc440sp functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 29mm, 783-ball fc-pbga core package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. clock timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 5. input setup and hold timing wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 6. output delay and hold timing wave form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 7. ddr sdram simulation signal termin ation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 8. ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 9. ddr sdram read data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10. ddr sdram memory data and dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11. ddr sdram read cycle timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 tables table 1. system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. dcr address map (4kb of device configuration registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 9. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 10. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 11. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 12. clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 13. peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 14. i/o specifications?all speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 15. i/o specifications?533mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 16. ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 17. ddr sdram read and write i/o timi ng?tsa and tha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 18. ddr sdram clock to write dqs timing?tds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 19. ddr sdram write data to dqs timing?tsd and thd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 20. ddr sdram i/o read timing?t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 21. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
powerpc 440sp embedded processor 4 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ordering and pvr information for information about the availability of the follo wing parts, contact your local amcc sales office. each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. see the ppc440sp embedded processor user?s manual for details about accessing these registers. note: raid-enabled versions (product feature = r) require a raid key license. figure 1. order part number key product name order part number (see notes:) package rev level pvr value jtag id ppc440sp ppc440sp-xpcfffc 29mm, 783 fc-pbga c 0x53221891 0x12056049 notes: 1. x = product feature a = raid6 not enabled r = raid6 enabled 2. p = module package type f = leaded fc-pbga n = lead free fc-pgba (rohs compliant) 3. c = chip revision level c 4. fff = processor frequency 533 = 533mhz 667 = 667mhz 5. c = case temperature range of -40c to +100c amcc part number ppc440sp-rnc667c package processor speed product feature revision level case temperature range note: the example part number above is a raid 6-enabled, lead-free package, at chip revision level c, capable of running at 667 mhz, and is shipped in tray packaging.
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 5 data sheet ppc440sp functional block diagram figure 2. ppc440sp functional block diagram the ppc440sp is a system on a chip, which uses ibm ? coreconnect bus? architecture. implemented with the crossbar option, the ibm coreconnect buses provide: ? 128-bit data, 64-bit address plb interfaces up to 16 6.66mhz, 2.6gb/s on both the read and write data paths (10.6gb/sec total) ? 32-bit opb interfaces up to 83.33mhz, 333mb/s address maps the ppc440sp incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of various proc essor accessible address regions. the second address map identifies the system device configuration registers (d crs). dcrs are accessed by software running on the ppc440sp processor through the use of mtdcr and mfdcr instructions. uart2 uart1 iic1 processor core dcr bus 32kb on-chip peripheral bus (opb) gpio accelerator bridge ddr2 sdram external bus controller controller clock, control, reset power mgmt jtag timers mmu unit opb interrupt controller universal i-cache 32kb d-cache xor/dma ppc440 ddr pci-x mal ethernet dcrs gpt l2 cache/sram 10/100/ low latency (ll) segment high bandwidth (hb) segment controller processor local bus (plb) trace arbiter plb i2o/dma host local 64 bits 64 bits local 32 bits memory pci0 pci1 pci2 1000 mii, gmii (ebc) (dma0 and dma1) (dma2) queue iic0 uart0 (emac)
powerpc 440sp embedded processor 6 amcc proprietary revision 1.23 - sept 26, 2006 data sheet table 1. system memory address map (sheet 1 of 2) function sub function start address end address size local memory (ll) 1 ddr sdram 0000 0000 0000 0000 0000 0000 ffff ffff 4gb sram 0000 0001 0000 0000 0000 0001 0003 ffff 256kb reserved 0000 0001 0004 0000 0000 0001 000f ffff internal plb interfaces (ll) i2o registers 0000 0001 0010 0000 0000 0001 0010 00ff 256b dma 0 registers 0000 0001 0010 0100 0000 0001 0010 01ff 256b dma 1 registers 0000 0001 0010 0200 0000 0001 0010 02ff 256b i20/dma buffers 0000 0001 0010 0300 0000 0001 0010 0fff 3.25kb reserved 0000 0001 0010 1000 0000 0001 001f ffff xor/dma2 0000 0001 0020 0000 0000 0001 0020 3fff 16kb reserved 0000 0001 0020 4000 0000 0001 efff ffff internal opb peripherals (ll) reserved 0000 0001 f000 0000 0000 0001 f000 01ff uart0 0000 0001 f000 0200 0000 0001 f000 0207 8b reserved 0000 0001 f000 0208 0000 0001 f000 02ff uart1 0000 0001 f000 0300 0000 0001 f000 0307 8b reserved 0000 0001 f000 0308 0000 0001 f000 03ff iic0 0000 0001 f000 0400 0000 0001 f000 041f 32b reserved 0000 0001 f000 0420 0000 0001 f000 04ff iic1 0000 0001 f000 0500 0000 0001 f000 051f 32b reserved 0000 0001 f000 0520 0000 0001 f000 05ff uart2 0000 0001 f000 0600 0000 0001 f000 0607 8b reserved 0000 0001 f000 0608 0000 0001 f000 06ff 248b gpio controller registers 0000 0001 f000 0700 0000 0001 f000 077f 128b reserved 0000 0001 f000 0780 0000 0001 f000 07ff ethernet controller registers 0000 0001 f000 0800 0000 0001 f000 08ff 256b reserved 0000 0001 f000 0900 0000 0001 f000 09ff general purpose timers 0000 0001 f000 0a00 0000 0001 f000 0b3f 320b reserved 0000 0001 f000 0b40 0000 0001 f7ff ffff ebc memory 0000 0001 f800 0000 0000 0001 ffbf ffff 124mb additional boot rom 6 0000 0001 ffc0 0000 0000 0001 ffdf ffff 2mb boot rom 2, 3 0000 0001 ffe0 0000 0000 0001 ffff ffff 2mb reserved 0000 0002 0000 0000 0000 0007 ffff ffff local memory alias (hb) aliased ddr sdram 0000 0008 0000 0000 0000 0008 ffff ffff 4gb
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 7 data sheet ddr pci-x space (hb) reserved 0000 0009 0000 0000 0000 0009 07ff ffff pcix0 i/o 0000 0009 0800 0000 0000 0009 0800 ffff 64kb pcix1 i/o 0000 0009 1800 0000 0000 0009 1800 ffff 64kb pcix2 i/o 0000 0009 2800 0000 0000 0009 2800 ffff 64kb pcix0 addressing config. regs 0000 0009 0ec0 0000 0000 0009 0ec0 0007 8b pcix1 addressing config. regs 0000 0009 1ec0 0000 0000 0009 1ec0 0007 8b pcix2 addressing config. regs 0000 0009 2ec0 0000 0000 0009 2ec0 0007 8b pcix0 core config. regs 0000 0009 0ec8 0000 0000 0009 0ec8 0fff 4kb pcix1 core config. regs 0000 0009 1ec8 0000 0000 0009 1ec8 0fff 4kb pcix2 core config. regs 0000 0009 2ec8 0000 0000 0009 2ec8 0fff 4kb pcix0 simple message passing 0000 0009 0ec8 1100 0000 0009 0ec8 11ff 256b pcix1 simple message passing 0000 0009 1ec8 1100 0000 0009 1ec8 11ff 256b pcix2 simple message passing 0000 0009 2ec8 1100 0000 0009 2ec8 11ff 256b pcix0 special cycle 0000 0009 0ed0 0000 0000 0009 0edf ffff 1mb pcix1 special cycle 0000 0009 1ed0 0000 0000 0009 1edf ffff 1mb pcix2 special cycle 0000 0009 2ed0 0000 0000 0009 2edf ffff 1mb reserved 0000 0009 2ee0 0000 0000 0009 2eff ffff pci memory 0000 0009 2f00 0000 0000 0009 ffbf ffff 3.3gb reserved 0000 0009 ffc0 0000 0000 0009 ffdf ffff pci boot rom (pci memory) 0000 0009 ffe0 0000 0000 0009 ffff ffff 2mb pci memory 0000 000a 0000 0000 0000 000f ffff ffff 24gb reserved 4 0000 0010 0000 0000 03ff ffff ffff ffff reserved 5 0400 0010 0000 0000 07ff ffff ffff ffff ddr pci-x space (hb) pci memory 0800 0000 0000 0000 ffff ffff ffff ffff 15.7eb notes: 1. ddr sdram and on-chip sram can be located anywhere in the local memory area of the memory map. 2. the boot rom and expansion rom areas of the memory map ar e intended for use by rom or fl ash-type devices. while locating volatile ddr sdram and sram in this region is supported, use of these regions for this purpose is not recommended. 3. when the optional boot from pci-x memory is selected, t he pci-x boot rom address space begins at 9 ffe0 0000 (128 kb). 4. never decoded. 5. unpredictable results on read and write operations. 6. accessed by means of ebc peripher al bank configuration registers table 1. system memory address map (sheet 2 of 2) function sub function start address end address size
powerpc 440sp embedded processor 8 amcc proprietary revision 1.23 - sept 26, 2006 data sheet table 2. dcr address map (4kb of device configuration registers) function start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b 12w clocking power on reset 00c 00d 2w system dcrs 00e 00f 2w memory controller 010 011 2w external bus controller 012 013 2w reserved 014 01f 12w sram 020 02f 16w l2 controller 030 03f 16w memory queue 040 04f 16w reserved 050 05f 16w i2o/dma 060 07f 32w plb 080 08f 16w plb to opb bridge out 090 09f 16w reserved 0a0 0af 16w reserved 0b0 0b1 2w reserved 0b2 0bf 14w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w power management 0e0 0e7 8w reserved 0e8 17f 152w ethernet mal 180 1ff 128w reserved 200 3ff 512w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a sin- gle 32-bit (word) register. one kw (1024w) equals 4kb (4096 bytes).
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 9 data sheet powerpc 440 processor core the powerpc 440 processor core is designed for high-end applications such as raid controllers, san, iscsi, routers, switches, printers, set-top bo xes, and so on. it is the first processor core to implement the book e powerpc embedded architecture and the first to use th e 128-bit version of ibm?s on-chip coreconnect bus architecture. features include: ? up to 667mhz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache ? parity on data and tag address - checking of parity with error injection ? three logical regions in d-cache: locked, transient, and normal ? d-cache full-line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? seven-stage pipeline ? three execution pipelines ? dynamic branch prediction ? memory management unit ? 64-entry, full associative, unified tlb with parity ? separate instruction and data micro-tlbs ? storage attributes for write-through, cache- inhibited, guarded, and big or little endian ? debug facilities ? multiple instruction and data range breakpoints ? data value compare ? single step, branch, and trap events ? non-invasive real-time trace interface ? 24 dsp instructions ? single cycle multiply and multiply-accumulate ? 32 x 32 integer multiply internal buses the powerpc 440sp embedded processor features thre e standard on-chip buses: the processor local bus (plb), the on-chip peripher al bus (opb), and the device control re gister bus (dcr). t he high perf ormance, high bandwidth cores such as the powerpc 440 proce ssor core, the ddr sdram me mory controller, and the ddr pci-x bridge connect to the plb. the opb hosts lower data rate peripherals. the daisy-chained dcr provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. the plb has a crossbar arbiter that supports data tran sfer between the plb master and two slave segments identified as the low latency (ll) and high bandwidth (h b) segments. the ll segment allows plb masters cpu and i2o, that are adversely affected by latency, to co mmunicate with slave devices wit h minimal latency. the hb segment allows plb masters dma, xo r, and pci to exchange large blocks of data with sdram and pci without interfering with the low latency plb masters. bus features include: ?plb ? 128-bit data implementation of the plb architecture ? separate and simultaneous read and write data paths ? 64-bit address ? simultaneous control, address, and data phases ? four levels of pipelining ? byte enable capability suppor ting unaligned transfers
powerpc 440sp embedded processor 10 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ? 32- and 64-byte burst transfers ? 166mhz, maximum 5.2gb/s (simultaneous read and write) ? processor:bus clock ratios of n:1 and n:2 ?opb ? dynamic bus sizing: 32-, 16-, and 8-bit data path ? 32-bit address ? 83.33mhz, maximum 333mb/s ? dcr ? 32-bit data path ? 10-bit address on-chip sram/l2 cache features include: ? four banks of 64kb each for a total of 256kb ? configurable as either l2 cache or sram ? memory cycles supported: ? single beat read and write, 1 to 16 bytes ? quadword read and write burst for 12-bit master ? guarded memory accesses on 4kb boundaries ? sustainable 2.6gb/s peak bandwidth at 166mhz ? use as an l2 cache improves proces sor performance and reduces the plb load ? cache coherency maintained by a hardware snoop mechanism on the low latency (ll) plb or by software ? data array and tag array parity ? unified data and instruction cache ? four-way set associative ? 36-bit addressing ? full lru replacement algorithm ? write through, look aside ? use as ethernet packet store a llows ethernet packets to be held for processing by the ethernet core ddr pci-x interface the ddr pci-x interface allows connection of pci an d pci-x devices to the powerpc processor and local memory. there are three separate interfaces supporting 32- and 64-bit pci-x buses in ddr mode. all three interfaces can be configured for ei ther host or adapter mode. pci 32/64-b it legacy mode, co mpatible with pci version 2.3, is also supported. features include: ?pci-x 2.0 ? split transactions ? frequency to 266mhz ? 32- and 64-bit address/data bus ? ecc supported for 266mhz mode 2 only ? pci 2.3 backwar d compatibility ? frequency to 66mhz ? 32- and 64-bit bus ? can be the pci host bus bridge or an adapter device pci interface ? optional pci arbitration function with pci and pci-x mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter ? support for message signaled interrupts (msi) on both in- and out-bound interrupts ? simple message passing capability ? asynchronous to the plb
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 11 data sheet ? pci power management version 1.1 ? pci arbitration function with pci-x mode 2 support (optional) ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci-x bus memory ? error tracking/status ? supports initiation of transfer to the following address spaces: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles ? pci-x initialization sequence suppor t (frequency & mode determination) ? support for unexpected split completions ? outbound transaction split discard timers ? vital product data (vpd) support ? pci-to-pci opaque bridge ddr1/ddr2 sdram memory controller the ddr2 sdram memory controller supports industry standard 184-pin dimms, so -dimms, and other discrete devices. global memory timings, address and bank sizes, and memory addressing modes are programmable. the ddr2 sdram controller interfaces to the plb through a memory queue (mq) function that includes six high- speed 1kb fifo buffers. features include: ? registered and non-registered industry standard dimms ? ddr1 266-333-400 ? ddr2 400-533-667 ? 64-and 32-bit memory interfaces with optional 8-bit ecc (sec/ded) ? 5.32gb/s peak bandwidth for the 64-bit interface ? 2.66gb/s peak bandwidth for the 32-bit interface ? two chip (bank) select signals supporting two external banks ? cas latencies of 2, 3, 4, 5, 6, and 7 supported ? page mode accesses (up to 32 open pages) with configurable paging policy ? look-ahead request queue with programmable depth of four commands. ? optional optimized command scheduling (activate/precharge non- conflicting banks while accessing the current bank) ? up to 4gb in two external banks ? programmable address mapping and timing ? hardware and software initiated self-refresh ? sync dram configuration by means of mode register and extended mode register set commands ? power management (self-refresh, suspend, sleep) ? low latency & high bandwidth plb ports ? selectable plb read response (immediate or deferred) ? programmable low latency & high bandwidth arbitration schemes ? high bandwidth port has four 1kb read buffers and two1kb write buffers ? low latency port has four 128b read buffers and two 128b write buffers external peripheral bus controller (ebc) features include: ? support 2mb boot rom ? up to three rom, eprom, sram, flash memory, and slave peripherals supported ? burst and non-burst devices ? 8-bit data bus
powerpc 440sp embedded processor 12 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ? 24-bit address, 16mb address space ? peripheral device pacing with external ?ready? ? latch data on ready, synchronous or asynchronous ? programmable access timing per device ? 256 wait states for non-burst ? 32 burst wait states for first access and up to 8 wait states for subsequent accesses ? programmable cson, csoff relative to address ? programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping ethernet controller interface the ethernet support interfaces to the physical la yer, but the phy is not included on the chip. features include: ? one 10/100/1000 interface running in full- and half-duplex modes ? one full media independent interface (mii) with 4-bit parallel data transfer ? one gigabit media independent interface (gmii) i2o/dma controller the i20/dma controller provides suppo rt for i20 messaging and two dma controllers (dma0 and dma1). i2o manages message frame address (mfa) fifos or queues in memory in response to i2o register reads and writes and transfers message frames. the dmas provide normal memory access support to ease the cpu burden. i2o features include: ? i2o pull- and push-messaging methods ? dynamic message frame size ? programmable fifo size (4096 64-bit mfas maximum) ? 64-bit and 32-bit mfa sizes ? three interrupt gathering methods ? registered mfa prefetch and posting ? 32-bit inbound and outbound doorbell registers ? four 32-bit scratch pad registers dma features include: ? programmable command pointer fifo and completion fifo size (up to 2048 dma operations queued) ? 512-byte/1kb buffering for dma0/dma1 ? simultaneous fill and drain (plb read/write pipelining) ? any source plb address to any destination address ? no memory alignment restrictio ns on source or destination ? 32-byte command descriptor block ? maximum transfer size of 16mb ? 64-bit addressing ? prefetch indicators for pci-x buffer management (dma1 only) optional raid 5 and raid 6 acceleration hardware the 440sp provides integrated acceleration hardware that implements high throughput raid 5 and raid 6 algorithms to compute the single parity p for raid 5, and dual parity p & q for raid 6. raid 5 is used to recover data in the case of a single disk drive failure, and raid 6 provides for data recovery if two disk drives fail. the 440sp offers a choice of two xor engines for computin g the p parity. the first choice is available with the xor/dma2 acceleration unit and is used for raid 5. th e second choice for xor parity computation, along with the raid 6 galois field gf(2 8 )-based polynomial computations, resides in side the memory queue functional block
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 13 data sheet of the memory controller unit. the raid 5 and raid 6 parity computations performed in the memory queue are assisted by the two-channel dma engine of the i2o/dma controller unit, designated as dma0 and dma1. the raid acceleration hardware also provides various alternatives fo r balancing load and performance, depe nding on customer-specific application firmware. the two-way crossbar bus architecture can pe rform data read and write op erations simultaneously, resulting in extremely high throughput. raid 6 capability is available only with the raid-enabled part numbers (ppc440sp-rpc fffc) as indicated in the ordering information section of this data sheet. for more information about the raid 6 implementation, description, and configur ation of the acceleration hardware, refer to the following amcc documents: ? powerpc 440sp/440spe raid support application note ? powerpc 440sp raid addendum to the user?s manual xor/dma2 controller the xor/dma2 controller performs the xor functions neede d to support raid 5 applications including parity generation and check functions used ac ross data stripes in a raid 5 system. features include: ? computes a bit-wise xor on up to 16 data str eams with result stored in designated target ? performs xor check on up to 16 data streams ? driven by a linked list command bloc k structure specifying control info rmation, source operands, target operand, status information, and link ? source and target streams may reside anywhere in plb address space. ? provides completion status per command block to be handled by software at a later time ? 96-byte and 160-byte command block formats are supported ? no memory alignment restrictions on operands or target ? internal register arrays and data buffers are parity protected ? can be used as a dma controller (dma2) with single source and target addresses serial port the serial port is compatible with the ns ? 16570 uart interface. features include: ? one 8-pin, one 4-pin, and one 2-pin interfaces are provided ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility with 16750 register set ? complete status reporting capability ? fully programmable serial-i nterface characteristics iic bus interface
powerpc 440sp embedded processor 14 amcc proprietary revision 1.23 - sept 26, 2006 data sheet features include: ? two iic interfaces provided ? support for philips ? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? supports fixed v dd iic interface ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully prog rammable configuration registers ? one programmable interrupt request signal ? full management of all iic bus protocols ? programmable error recovery ? port 0 supports serial bootstrap rom with default parameters override at initialization general purpose timers (gpt) provides a time base counter and system timers ad ditional to those defined in the processor core. ? 32-bit time base counter driven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller ? controller functions and gpio registers are progra mmed and accessed by means of memory-mapped opb bus master accesses. ? the 32 gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for ano ther purpose. ? each gpio output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 15 data sheet universal interrupt controller (uic) two cascaded universal interrupt contro llers (uic) process internal on-chip and external processor interrupts. note: processor specific interrupts (for exampl e, page faults) do not use uic resources. features include: ? 6 external interrupts ? 56 internal interrupts ? edge-triggered or level-sensitive ? positive- or negative-active ? non-critical or critical interrupt to the on-chip processor core ? programmable interrupt priority ordering ? programmable critical interrupt ve ctor for faster vector processing jtag features include: ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl)
powerpc 440sp embedded processor 16 amcc proprietary revision 1.23 - sept 26, 2006 data sheet figure 3. 29mm, 783-ball fc-pbga core package top view bottom view note: all dimensions are in mm. 01 03 05 07 09 11 13 15 17 19 02 04 06 08 10 12 14 16 18 21 23 20 22 24 a b c d e f g h j k l m aa n p r t u v w y ab ac ad 29.0 0.2 1.00 typ 29.0 0.2 3.27 max 0.4 min 0.6 0.1 solderball x 783 25 26 27 28 af ae ag ah a1 corner 24 ad a 1 ppc440sp xpcfffc part number aaaaaaaa lot number ?
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 17 data sheet signal lists this section contains two tables that list external signals. table 3 lists all the external signals in alphabetical or der and shows the ball (pin) number on which the signal appears. multiplexed signals are shown wi th the default signal (following reset) not in brackets and the alternate signal or signals in brackets. multiplexed signals appear alphabetically multiple times in the list?once for each signal name on the ball. the page number listed gives the page in ?signal functional description? on page 56 where the signals in the indicated interface group begin. table 4 on page 47 lists all the external signals in order by ball (pin) number. signal list?alphabetic order table 3. signals listed alpha betically (sheet 1 of 30) signal name ball interface group page a1gnd b01 power 62 a2gnd ag28 a1v dd c01 a2v dd af28 ap0gnd ag01 ap0v dd af01 ap1gnd b28 ap1v dd c28 ap2gnd t01 ap2v dd r01 ba0 ad21 ddr sdram 58 ba1 ae20 ba2 ae25 banksel0 t23 banksel1 p22 cas ah25 clken0 ae23 clken1 ae24
powerpc 440sp embedded processor 18 amcc proprietary revision 1.23 - sept 26, 2006 data sheet dm0 ae26 ddr sdram 58 dm1 aa26 dm2 v25 dm3 p26 dm4 k27 dm5 m21 dm6 r21 dm7 u19 dm8 aa24 dqs0 ad26 dqs0 ad25 dqs1 aa28 dqs1 aa27 dqs2 u26 dqs2 u25 dqs3 n27 dqs3 n28 dqs4 k25 dqs4 k26 dqs5 l25 dqs5 l26 dqs6 r26 dqs6 r25 dqs7 w27 dqs7 w26 dqs8 ab26 dqs8 ab25 table 3. signals listed alpha betically (sheet 2 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 19 data sheet ecc0 ac24 ddr sdram 58 ecc1 y23 ecc2 y21 ecc3 ac23 ecc4 ad23 ecc5 aa23 ecc6 w19 ecc7 af20 table 3. signals listed alpha betically (sheet 3 of 30) signal name ball interface group page
powerpc 440sp embedded processor 20 amcc proprietary revision 1.23 - sept 26, 2006 data sheet emccd d02 ethernet 59 emccrs e03 emcmdclk d01 emcmdio e04 emcrefclk d12 emcrxclk d03 emcrxd0 f04 emcrxd1 g04 emcrxd2 f03 emcrxd3 g01 emcrxd4 h03 emcrxd5 h02 emcrxd6 f05 emcrxd7 f06 emcrxdv f07 emcrxerr j01 emctxclk e01 emcgtxclk b08 emctxd0 f02 emctxd1 f01 emctxd2 h01 emctxd3 g03 emctxd4 h04 emctxd5 k04 emctxd6 k03 emctxd7 a02 emctxen c04 emctxerr a03 extreset h11 external slave peripheral 59 table 3. signals listed alpha betically (sheet 4 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 21 data sheet gnd b02 power 62 gnd b05 gnd b09 gnd b20 gnd b24 gnd b27 gnd c13 gnd c16 gnd e02 gnd e07 gnd e11 gnd e18 gnd e22 gnd e27 gnd f14 gnd f15 gnd g05 gnd g09 gnd g13 gnd g16 gnd g20 gnd g24 gnd j02 gnd j07 gnd j11 gnd j18 gnd j22 gnd j27 gnd l05 gnd l09 gnd l13 gnd l16 table 3. signals listed alpha betically (sheet 5 of 30) signal name ball interface group page
powerpc 440sp embedded processor 22 amcc proprietary revision 1.23 - sept 26, 2006 data sheet gnd l20 power 62 gnd l24 gnd n03 gnd n07 gnd n11 gnd n14 gnd n15 gnd n18 gnd n22 gnd n26 gnd p06 gnd p13 gnd p16 gnd p23 gnd r06 gnd r13 gnd r16 gnd r23 gnd t03 gnd t07 gnd t11 gnd t14 gnd t15 gnd t18 gnd t22 gnd t26 gnd v05 gnd v09 gnd v13 gnd v16 gnd v20 gnd v24 gnd y02 gnd y07 table 3. signals listed alpha betically (sheet 6 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 23 data sheet gnd y11 power 62 gnd y18 gnd y22 gnd y27 gnd ab05 gnd ab09 gnd ab13 gnd ab16 gnd ab20 gnd ab24 gnd ac14 gnd ac15 gnd ad02 gnd ad07 gnd ad11 gnd ad18 gnd ad22 gnd ad27 gnd af13 gnd af16 gnd ag02 gnd ag05 gnd ag09 gnd ag20 gnd ag24 gnd ag27 table 3. signals listed alpha betically (sheet 7 of 30) signal name ball interface group page
powerpc 440sp embedded processor 24 amcc proprietary revision 1.23 - sept 26, 2006 data sheet [gpio00] [trcclk] pcix0req2 aa12 system 61 [gpio01] [trcbs0] pcix0req3 y12 [gpio02] [trcbs1] pcix0gnt2 ac13 [gpio03] [trcbs2] pcix0gnt3 af11 [gpio04] [trces0] pcix1req2 c23 [gpio05] [trces1] pcix1req3 e23 [gpio06] [trces2] pcix1gnt2 d21 [gpio07] [trces3] pcix1gnt3 d23 [gpio08] [trces4] perready g12 [gpio09] percs1 [trcts0] e12 [gpio10] percs2 [trcts1] h10 [gpio11] irq0 [trcts2] c07 [gpio12] irq1 [trcts3] c06 [gpio13] irq2 [trcts4] a05 [gpio14] irq3 [trcts5] c05 [gpio15] irq4 [trcts6] d06 [gpio16] irq5 [uart2_rx] d05 [gpio17] perbe0 [uart2_tx] r09 [gpio18] pcix0gnt0 af14 [gpio19] pcix0gnt1 ag13 [gpio20] pcix0req0 ah11 [gpio21] pcix0req1 ag12 [gpio22] pcix1gnt0 b19 [gpio23] pcix1gnt1 c19 [gpio24] pcix1req0 c20 [gpio25] pcix1req1 c22 [gpio26] pcix2gnt0 p01 [gpio27] pcix2gnt1 p03 [gpio28] pcix2req0 u05 [gpio29] pcix2req1 n04 [gpio30] uart1_rx a07 [gpio31] uart1_tx a06 halt k18 hisrrst b06 table 3. signals listed alpha betically (sheet 8 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 25 data sheet iic0sclk d09 iic peripheral 60 iic0sda e08 iic1sclk f08 iic1sda e10 irq0 [gpio11] [trcts2] c07 interrupts 60 irq1 [gpio12] [trcts3] c06 irq2 [gpio13] [trcts4] a05 irq3 [gpio14] [trcts5] c05 irq4 [gpio15] [trcts6] d06 irq5 [gpio16] [uart2_rx] d05 memaddr00 af23 ddr sdram 58 memaddr01 ae21 memaddr02 ad19 memaddr03 ae19 memaddr04 ah22 memaddr05 ah23 memaddr06 ae22 memaddr07 af21 memaddr08 af22 memaddr09 ag23 memaddr10 ag21 memaddr11 af19 memaddr12 ah20 memaddr13 ah21 memaddr14 af24 memclkout0 ag26 memclkout0 ag25 memclkout1 ah26 memclkout1 ah27 table 3. signals listed alpha betically (sheet 9 of 30) signal name ball interface group page
powerpc 440sp embedded processor 26 amcc proprietary revision 1.23 - sept 26, 2006 data sheet memdata00 ad28 ddr sdram 58 memdata01 ae27 memdata02 af27 memdata03 ac26 memdata04 ac27 memdata05 ae28 memdata06 af25 memdata07 ac25 memdata08 y26 memdata09 ab28 memdata10 ac28 memdata11 y28 memdata12 y25 memdata13 aa25 memdata14 ab23 memdata15 w25 memdata16 u27 memdata17 v28 memdata18 w28 memdata19 t25 memdata20 t27 memdata21 v26 memdata22 w23 memdata23 t28 memdata24 n25 memdata25 p28 memdata26 r28 memdata27 m27 memdata28 m26 memdata29 p25 memdata30 u24 memdata31 m25 table 3. signals listed alpha betically (sheet 10 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 27 data sheet memdata32 j26 ddr sdram 58 memdata33 k28 memdata34 l28 memdata35 h28 memdata36 h27 memdata37 j28 memdata38 p21 memdata39 h26 memdata40 p20 memdata41 m23 memdata42 m22 memdata43 n23 memdata44 n21 memdata45 k24 memdata46 m24 memdata47 n19 memdata48 u23 memdata49 r22 memdata50 r24 memdata51 u22 memdata52 t19 memdata53 r20 memdata54 p24 memdata55 t21 memdata56 w22 memdata57 u20 memdata58 u21 memdata59 w24 memdata60 w21 memdata61 v23 memdata62 v21 memdata63 w20 memdcfdbkd ab21 memdcfdbkr ac21 table 3. signals listed alphabetically (sheet 11 of 30) signal name ball interface group page
powerpc 440sp embedded processor 28 amcc proprietary revision 1.23 - sept 26, 2006 data sheet memodt0 aa22 ddr sdram 58 memodt1 ac22 memvref0 aa20 memvref1 aa21 no ball a01 a physical ball does no t exist at this coordinate na ov dd b07 power 62 ov dd b11 ov dd b14 ov dd b15 ov dd c03 ov dd g02 ov dd g07 ov dd g11 ov dd k14 ov dd k15 ov dd l02 ov dd l07 ov dd l11 ov dd p10 ov dd p14 table 3. signals listed alpha betically (sheet 12 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 29 data sheet p0v dd r14 power 62 p0v dd w14 p0v dd w15 p0v dd ab07 p0v dd ab11 p0v dd ab18 p0v dd ab22 p0v dd ag07 p0v dd ag11 p0v dd ag14 p0v dd ag15 p0v dd ag18 p0v dd ag22 p1v dd b18 p1v dd b22 p1v dd c26 p1v dd g18 p1v dd g22 p1v dd g27 p1v dd l18 p1v dd l22 p1v dd l27 p1v dd p15 p2v dd p02 p2v dd r02 p2v dd r10 p2v dd v02 p2v dd v07 p2v dd v11 p2v dd ab02 p2v dd af03 table 3. signals listed alpha betically (sheet 13 of 30) signal name ball interface group page
powerpc 440sp embedded processor 30 amcc proprietary revision 1.23 - sept 26, 2006 data sheet pcix0ack64 [pcix0ecc1] ah06 pci-x0 56 pcix0ad00 ae12 pcix0ad01 ae11 pcix0ad02 ae10 pcix0ad03 ae09 pcix0ad04 af10 pcix0ad05 ah08 pcix0ad06 ah09 pcix0ad07 aa11 pcix0ad08 ac09 pcix0ad09 aa09 pcix0ad10 ac08 pcix0ad11 ad08 pcix0ad12 ad10 pcix0ad13 aa10 pcix0ad14 ab10 pcix0ad15 ah07 pcix0ad16 af06 pcix0ad17 af07 pcix0ad18 ae08 pcix0ad19 af05 pcix0ad20 af04 pcix0ad21 ad06 pcix0ad22 ag04 pcix0ad23 af08 pcix0ad24 ah02 pcix0ad25 ah03 pcix0ad26 af02 pcix0ad27 ae03 pcix0ad28 ad04 pcix0ad29 ae05 pcix0ad30 ae01 pcix0ad31 ae02 table 3. signals listed alpha betically (sheet 14 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 31 data sheet pcix0ad32 ae18 pci-x0 56 pcix0ad33 af18 pcix0ad34 ah19 pcix0ad35 ag19 pcix0ad36 ad17 pcix0ad37 aa18 pcix0ad38 w18 pcix0ad39 ac20 pcix0ad40 ae17 pcix0ad41 y17 pcix0ad42 w17 pcix0ad43 aa17 pcix0ad44 ac19 pcix0ad45 ab17 pcix0ad46 ac17 pcix0ad47 ab19 pcix0ad48 ac18 pcix0ad49 ah18 pcix0ad50 ag16 pcix0ad51 af17 pcix0ad52 af15 pcix0ad53 ah15 pcix0ad54 ae15 pcix0ad55 ad15 pcix0ad56 ab14 pcix0ad57 ab15 pcix0ad58 aa14 pcix0ad59 y15 pcix0ad60 w16 pcix0ad61 aa16 pcix0ad62 ac16 pcix0ad63 aa15 table 3. signals listed alpha betically (sheet 15 of 30) signal name ball interface group page
powerpc 440sp embedded processor 32 amcc proprietary revision 1.23 - sept 26, 2006 data sheet pcix0be0 af09 pci-x0 56 pcix0be1 ag10 pcix0be2 ae07 pcix0be3 ae06 pcix0be4 ah16 pcix0be5 ag17 pcix0be6 ae16 pcix0be7 ae14 pcix0calg0 aa08 pcix0calg1 y19 pcix0calr0 ab08 pcix0calr1 aa19 pcix0cap aa13 pcix0clk af12 pcix0devsel y10 [pcix0ecc0] pcix0par ag06 [pcix0ecc1] pcix0ack64 ah06 pcix0ecc2 ag03 pcix0ecc3 ah04 pcix0ecc4 ah05 pcix0ecc5 ad03 [pcix0ecc6] pcix0req64 ag08 [pcix0ecc7] pcix0par64 ah14 pcix0frame ac12 pcix0gnt0 [gpio18] af14 pcix0gnt1 [gpio19] ag13 pcix0gnt2 [gpio02] [trcbs1] ac13 pcix0gnt3 [gpio03] [trcbs2] af11 pcix0idsel y14 pcix0inta ab12 pcix0irdy w13 table 3. signals listed alpha betically (sheet 16 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 33 data sheet pcix0m66en ad14 pci-x0 56 pcix0par [pcix0ecc0] ag06 pcix0par64 [pcix0ecc7] ah14 pcix0perr w11 pcix0req0 [gpio20] ah11 pcix0req1 [gpio21] ag12 pcix0req2 [gpio00] [trcclk] aa12 pcix0req3 [gpio01] [trcbs0] y12 pcix0req64 [pcix0ecc6] ag08 pcix0reset ah13 pcix0serr ad12 pcix0stop ae13 pcix0trdy w12 pcix0vc ah10 pcix0vref0 ac11 pcix0vref1 ac10 table 3. signals listed alpha betically (sheet 17 of 30) signal name ball interface group page
powerpc 440sp embedded processor 34 amcc proprietary revision 1.23 - sept 26, 2006 data sheet pcix1ack64 [pcix1ecc1] k23 pci-x1 56 pcix1ad00 d18 pcix1ad01 c18 pcix1ad02 f18 pcix1ad03 a19 pcix1ad04 f16 pcix1ad05 h20 pcix1ad06 f20 pcix1ad07 f21 pcix1ad08 c17 pcix1ad09 d16 pcix1ad10 b17 pcix1ad11 b16 pcix1ad12 e17 pcix1ad13 h19 pcix1ad14 f19 pcix1ad15 g19 pcix1ad16 a15 pcix1ad17 c14 pcix1ad18 c15 pcix1ad19 a16 pcix1ad20 d15 pcix1ad21 h17 pcix1ad22 g17 pcix1ad23 h18 pcix1ad24 d13 pcix1ad25 b13 pcix1ad26 b12 pcix1ad27 c12 pcix1ad28 e15 pcix1ad29 k16 pcix1ad30 h16 pcix1ad31 j15 table 3. signals listed alpha betically (sheet 18 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 35 data sheet pcix1ad32 e28 pci-x1 56 pcix1ad33 f28 pcix1ad34 f27 pcix1ad35 d28 pcix1ad36 g28 pcix1ad37 m20 pcix1ad38 m19 pcix1ad39 l23 pcix1ad40 a27 pcix1ad41 g26 pcix1ad42 c27 pcix1ad43 d27 pcix1ad44 f26 pcix1ad45 k22 pcix1ad46 k21 pcix1ad47 k20 pcix1ad48 h25 pcix1ad49 j25 pcix1ad50 e25 pcix1ad51 b26 pcix1ad52 e26 pcix1ad53 j23 pcix1ad54 j21 pcix1ad55 h23 pcix1ad56 b25 pcix1ad57 c24 pcix1ad58 d24 pcix1ad59 c25 pcix1ad60 a26 pcix1ad61 a25 pcix1ad62 d25 pcix1ad63 f24 table 3. signals listed alpha betically (sheet 19 of 30) signal name ball interface group page
powerpc 440sp embedded processor 36 amcc proprietary revision 1.23 - sept 26, 2006 data sheet pcix1be0 f17 pci-x1 56 pcix1be1 d17 pcix1be2 d14 pcix1be3 e14 pcix1be4 d26 pcix1be5 f25 pcix1be6 g25 pcix1be7 f22 pcix1calg0 l19 pcix1calg1 g14 pcix1calr0 l21 pcix1calr1 h14 pcix1cap g21 pcix1clk e21 pcix1devsel d19 [pcix1ecc0] pcix1par k19 [pcix1ecc1] pcix1ack64 k23 pcix1ecc2 h21 pcix1ecc3 h22 pcix1ecc4 h15 pcix1ecc5 f23 [pcix1ecc6] pcix1req64 h24 [pcix1ecc7] pcix1par64 a24 pcix1frame b21 pcix1gnt0 [gpio22] b19 pcix1gnt1 [gpio23] c19 pcix1gnt2 [gpio06] [trces2] d21 pcix1gnt3 [gpio07] [trces3] d23 pcix1idsel b23 pcix1inta a22 pcix1irdy d22 pcix1m66en g23 table 3. signals listed alpha betically (sheet 20 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 37 data sheet pcix1par [pcix1ecc0] k19 pci-x1 56 pcix1par64 [pcix1ecc7] a24 pcix1perr d20 pcix1req0 [gpio24] c20 pcix1req1 [gpio25] c22 pcix1req2 [gpio04] [trces0] c23 pcix1req3 [gpio05] [trces1] e23 pcix1req64 [pcix1ecc6] h24 pcix1reset a20 pcix1serr a23 pcix1stop c21 pcix1trdy e19 pcix1vc a21 pcix1vref0 j17 pcix1vref1 k17 table 3. signals listed alpha betically (sheet 21 of 30) signal name ball interface group page
powerpc 440sp embedded processor 38 amcc proprietary revision 1.23 - sept 26, 2006 data sheet pcix2ad00 ac03 pci-x2 56 pcix2ad01 ac04 pcix2ad02 ac05 pcix2ad03 ad01 pcix2ad04 ab01 pcix2ad05 ab04 pcix2ad06 ac01 pcix2ad07 ac02 pcix2ad08 y04 pcix2ad09 aa01 pcix2ad10 y03 pcix2ad11 y01 pcix2ad12 aa03 pcix2ad13 aa04 pcix2ad14 ab06 pcix2ad15 ac06 pcix2ad16 w02 pcix2ad17 w01 pcix2ad18 w03 pcix2ad19 w04 pcix2ad20 v04 pcix2ad21 y06 pcix2ad22 y08 pcix2ad23 aa05 pcix2ad24 v01 pcix2ad25 u03 pcix2ad26 t04 pcix2ad27 t02 pcix2ad28 u04 pcix2ad29 w07 pcix2ad30 w06 pcix2ad31 w05 pcix2be0 ab03 pcix2be1 aa02 table 3. signals listed alpha betically (sheet 22 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 39 data sheet pcix2be2 v03 pci-x2 56 pcix2be3 u02 pcix2calg0 w08 pcix2calr0 w09 pcix2cap t08 pcix2clk r03 pcix2devsel m03 [pcix2ecc0] pcix2par ac07 pcix2ecc1 w10 pcix2ecc2 aa07 pcix2ecc3 u09 pcix2ecc4 n01 pcix2ecc5 aa06 pcix2ecc6 ae04 pcix2frame u08 pcix2gnt0 [gpio26] p01 pcix2gnt1 [gpio27] p03 pcix2idsel t10 pcix2inta u07 pcix2irdy p04 pcix2m66en t06 pcix2par [pcix2ecc0] ac07 pcix2perr u06 pcix2req0 [gpio28] u05 pcix2req1 [gpio29] n04 pcix2reset v06 pcix2serr v08 pcix2stop m02 pcix2trdy n02 pcix2vc v10 pcix2vref0 r04 pcix2vref1 u10 table 3. signals listed alpha betically (sheet 23 of 30) signal name ball interface group page
powerpc 440sp embedded processor 40 amcc proprietary revision 1.23 - sept 26, 2006 data sheet peraddr00 j04 external slave peripheral 59 peraddr01 k06 peraddr02 k05 peraddr03 m08 peraddr04 l06 peraddr05 m07 peraddr06 l08 peraddr07 k07 peraddr08 k08 peraddr09 m05 peraddr10 n08 peraddr11 n06 peraddr12 p08 peraddr13 p05 peraddr14 p07 peraddr15 l03 peraddr16 l04 peraddr17 l01 peraddr18 m04 peraddr19 k01 peraddr20 k02 peraddr21 r07 peraddr22 r05 peraddr23 r08 perbe0 [gpio17] [uart2_tx] r09 perblast b04 perclk a04 percs0 m06 percs1 [gpio09] [trcts0] e12 percs2 [gpio10] [trcts1] h10 table 3. signals listed alpha betically (sheet 24 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 41 data sheet perdata0 h05 external slave peripheral 59 perdata1 j08 perdata2 h07 perdata3 d04 perdata4 g08 perdata5 e06 perdata6 g06 perdata7 j06 pererr b03 peroe f12 perpar0 c02 perready [gpio08] [trces4] g12 perr/w h06 perwe k10 psro m12 psro 62 psro m17 psro u12 psro u17 ras ah24 ddr sdram 58 table 3. signals listed alpha betically (sheet 25 of 30) signal name ball interface group page
powerpc 440sp embedded processor 42 amcc proprietary revision 1.23 - sept 26, 2006 data sheet reserved d07 reserved 62 reserved f09 reserved f13 reserved h08 reserved h09 reserved h13 reserved j10 reserved j12 reserved j14 reserved k09 reserved k11 reserved k12 reserved k13 reserved l10 reserved l12 reserved l14 reserved l15 reserved l17 reserved m09 reserved m10 reserved m11 reserved m13 reserved m14 reserved m15 reserved m16 reserved m18 reserved n10 reserved n12 reserved n17 reserved p09 reserved p11 reserved p12 reserved p17 table 3. signals listed alpha betically (sheet 26 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 43 data sheet reserved p18 reserved 62 reserved r11 reserved r12 reserved r17 reserved r18 reserved t12 reserved t17 reserved u11 reserved u13 reserved u14 reserved u15 reserved u16 reserved u18 reserved v12 reserved v14 reserved v15 reserved v17 sv dd p19 power 62 sv dd p27 sv dd r15 sv dd r19 sv dd r27 sv dd v18 sv dd v22 sv dd v27 sv dd ab27 sv dd af26 sysclk j03 system 61 syserr j19 syspartsel a14 sysreset g15 table 3. signals listed alpha betically (sheet 27 of 30) signal name ball interface group page
powerpc 440sp embedded processor 44 amcc proprietary revision 1.23 - sept 26, 2006 data sheet tck d10 jtag 61 tdi a10 tdo d11 testen a18 system 61 tmrclk d08 tms c10 jtag 61 [trcclk] [gpio00] pcix0req2 aa12 trace 61 [trcbs0] [gpio01] pcix0req3 y12 [trcbs1] [gpio02] pcix0gnt2 ac13 [trcbs2] [gpio03] pcix0gnt3 af11 [trces0] [gpio04] pcix1req2 c23 [trces1] [gpio05] pcix1req3 e23 [trces2] [gpio06] pcix1gnt2 d21 [trces3] [gpio07] pcix1gnt3 d23 [trces4] [gpio08] perready g12 [trcts0] percs1 [gpio09] e12 [trcts1] percs2 [gpio10] h10 [trcts2] [gpio11] irq0 c07 [trcts3] [gpio12] irq1 c06 [trcts4] [gpio13] irq2 a05 [trcts5] [gpio14] irq3 c05 [trcts6] [gpio15] irq4 d06 trst b10 jtag 61 uart0_cts c09 uart peripheral 60 uart0_dcd a08 uart0_dsr c11 uart0_dtr a11 uart0_ri a13 uart0_rts f11 uart0_rx h12 uart0_tx c08 table 3. signals listed alpha betically (sheet 28 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 45 data sheet uart1_dsr /cts f10 uart peripheral 60 uart1_rts/dtr g10 uart1_rx [gpio30] a07 uart1_tx [gpio31] a06 [uart2_rx] [gpio16] irq5 d05 [uart2_tx] [gpio17] perbe0 r09 uartserclk a09 v dd a12 power 62 v dd a17 v dd a28 v dd e05 v dd e09 v dd e13 v dd e16 v dd e20 v dd e24 v dd j05 v dd j09 v dd j13 v dd j16 v dd j20 v dd j24 v dd m01 v dd m28 v dd n05 v dd n09 v dd n13 v dd n16 v dd n20 v dd n24 v dd t05 v dd t09 table 3. signals listed alpha betically (sheet 29 of 30) signal name ball interface group page
powerpc 440sp embedded processor 46 amcc proprietary revision 1.23 - sept 26, 2006 data sheet v dd t13 power 62 v dd t16 v dd t20 v dd t24 v dd u01 v dd u28 v dd y05 v dd y09 v dd y13 v dd y16 v dd y20 v dd y24 v dd ad05 v dd ad09 v dd ad13 v dd ad16 v dd ad20 v dd ad24 v dd ah01 v dd ah12 v dd ah17 v dd ah28 we v19 ddr sdram 58 table 3. signals listed alpha betically (sheet 30 of 30) signal name ball interface group page
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 47 data sheet signal list?ball assignment order in the following table, only the primary (default) signal name is shown for each pin. multiplexed pins are marked with an asterisk (*). to determine the other signals that sh are a pin, look up the primary signal name in table 3 on page 17. table 4. signals listed by ba ll assignment (sheet 1 of 7) ball signal name ball signal name ball signal name ball signal name a01 no ball b01 a1gnd c01 a1v dd d01 emcmdclk a02 emctxd7 b02 gnd c02 perpar0 d02 emccd a03 emctxerr b03 pererr c03 ov dd d03 emcrxclk a04 perclk b04 perblast c04 emctxen d04 perdata3 a05 irq2 * b05 gnd c05 irq3 * d05 irq5 * a06 uart1_tx * b06 hisrrst c06 irq1 * d06 irq4 * a07 uart1_rx * b07 ov dd c07 irq0 * d07 reserved a08 uart0_dcd b08 emcgtxclk c08 uart0_tx d08 tmrclk a09 uartserclk b09 gnd c09 uart0_cts d09 iic0sclk a10 tdi b10 trst c10 tms d10 tck a11 uart0_dtr b11 ov dd c11 uart0_dsr d11 tdo a12 v dd b12 pcix1ad26 c12 pcix1ad27 d12 emcrefclk a13 uart0_ri b13 pcix1ad25 c13 gnd d13 pcix1ad24 a14 syspartsel b14 ov dd c14 pcix1ad17 d14 pcix1be2 a15 pcix1ad16 b15 ov dd c15 pcix1ad18 d15 pcix1ad20 a16 pcix1ad19 b16 pcix1ad11 c16 gnd d16 pcix1ad09 a17 v dd b17 pcix1ad10 c17 pcix1ad08 d17 pcix1be1 a18 testen b18 p1v dd c18 pcix1ad01 d18 pcix1ad00 a19 pcix1ad03 b19 pcix1gnt0 * c19 pcix1gnt1 * d19 pcix1devsel a20 pcix1reset b20 gnd c20 pcix1req0 * d20 pcix1perr a21 pcix1vc b21 pcix1frame c21 pcix1stop d21 pcix1gnt2 * a22 pcix1inta b22 p1v dd c22 pcix1req1 * d22 pcix1irdy a23 pcix1serr b23 pcix1idsel c23 pcix1req2 * d23 pcix1gnt3 * a24 pcix1par64 * b24 gnd c24 pcix1ad57 d24 pcix1ad58 a25 pcix1ad61 b25 pcix1ad56 c25 pcix1ad59 d25 pcix1ad62 a26 pcix1ad60 b26 pcix1ad51 c26 p1v dd d26 pcix1be4 a27 pcix1ad40 b27 gnd c27 pcix1ad42 d27 pcix1ad43 a28 v dd b28 ap1gnd c28 ap1v dd d28 pcix1ad35
powerpc 440sp embedded processor 48 amcc proprietary revision 1.23 - sept 26, 2006 data sheet e01 emctxclk f01 emctxd1 g01 emcrxd3 h01 emctxd2 e02 gnd f02 emctxd0 g02 ov dd h02 emcrxd5 e03 emccrs f03 emcrxd2 g03 emctxd3 h03 emcrxd4 e04 emcmdio f04 emcrxd0 g04 emcrxd1 h04 emctxd4 e05 v dd f05 emcrxd6 g05 gnd h05 perdata0 e06 perdata5 f06 emcrxd7 g06 perdata6 h06 perr/w e07 gnd f07 emcrxdv g07 ov dd h07 perdata2 e08 iic0sda f08 iic1sclk g08 perdata4 h08 reserved e09 v dd f09 reserved g09 gnd h09 reserved e10 iic1sda f10 uart1_dsr /cts g10 uart1_rts/dtr h10 percs2 * e11 gnd f11 uart0_rts g11 ov dd h11 extreset e12 percs1 * f12 peroe g12 perready * h12 uart0_rx e13 v dd f13 reserved g13 gnd h13 reserved e14 pcix1be3 f14 gnd g14 pcix1calg1 h14 pcix1calr1 e15 pcix1ad28 f15 gnd g15 sysreset h15 pcix1ecc4 e16 v dd f16 pcix1ad04 g16 gnd h16 pcix1ad30 e17 pcix1ad12 f17 pcix1be0 g17 pcix1ad22 h17 pcix1ad21 e18 gnd f18 pcix1ad02 g18 p1v dd h18 pcix1ad23 e19 pcix1trdy f19 pcix1ad14 g19 pcix1ad15 h19 pcix1ad13 e20 v dd f20 pcix1ad06 g20 gnd h20 pcix1ad05 e21 pcix1clk f21 pcix1ad07 g21 pcix1cap h21 pcix1ecc2 e22 gnd f22 pcix1be7 g22 p1v dd h22 pcix1ecc3 e23 pcix1req3 * f23 pcix1ecc5 g23 pcix1m66en h23 pcix1ad55 e24 v dd f24 pcix1ad63 g24 gnd h24 pcix1req64 * e25 pcix1ad50 f25 pcix1be5 g25 pcix1be6 h25 pcix1ad48 e26 pcix1ad52 f26 pcix1ad44 g26 pcix1ad41 h26 memdata39 e27 gnd f27 pcix1ad34 g27 p1v dd h27 memdata36 e28 pcix1ad32 f28 pcix1ad33 g28 pcix1ad36 h28 memdata35 table 4. signals listed by ba ll assignment (sheet 2 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 49 data sheet j01 emcrxerr k01 peraddr19 l01 peraddr17 m01 v dd j02 gnd k02 peraddr20 l02 ov dd m02 pcix2stop j03 sysclk k03 emctxd6 l03 peraddr15 m03 pcix2devsel j04 peraddr00 k04 emctxd5 l04 peraddr16 m04 peraddr18 j05 v dd k05 peraddr02 l05 gnd m05 peraddr09 j06 perdata7 k06 peraddr01 l06 peraddr04 m06 percs0 j07 gnd k07 peraddr07 l07 ov dd m07 peraddr05 j08 perdata1 k08 peraddr08 l08 peraddr06 m08 peraddr03 j09 v dd k09 reserved l09 gnd m09 reserved j10 reserved k10 perwe l10 reserved m10 reserved j11 gnd k11 reserved l11 ov dd m11 reserved j12 reserved k12 reserved l12 reserved m12 psro j13 v dd k13 reserved l13 gnd m13 reserved j14 reserved k14 ov dd l14 reserved m14 reserved j15 pcix1ad31 k15 ov dd l15 reserved m15 reserved j16 v dd k16 pcix1ad29 l16 gnd m16 reserved j17 pcix1vref0 k17 pcix1vref1 l17 reserved m17 psro j18 gnd k18 halt l18 p1v dd m18 reserved j19 syserr k19 pcix1par * l19 pcix1calg0 m19 pcix1ad38 j20 v dd k20 pcix1ad47 l20 gnd m20 pcix1ad37 j21 pcix1ad54 k21 pcix1ad46 l21 pcix1calr0 m21 dm5 j22 gnd k22 pcix1ad45 l22 p1v dd m22 memdata42 j23 pcix1ad53 k23 pcix1ack64 * l23 pcix1ad39 m23 memdata41 j24 v dd k24 memdata45 l24 gnd m24 memdata46 j25 pcix1ad49 k25 dqs4 l25 dqs5 m25 memdata31 j26 memdata32 k26 dqs4 l26 dqs5 m26 memdata28 j27 gnd k27 dm4 l27 p1v dd m27 memdata27 j28 memdata37 k28 memdata33 l28 memdata34 m28 v dd table 4. signals listed by ba ll assignment (sheet 3 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor 50 amcc proprietary revision 1.23 - sept 26, 2006 data sheet n01 pcix2ecc4 p01 pcix2gnt0 * r01 ap2v dd t01 ap2gnd n02 pcix2trdy p02 p2v dd r02 p2v dd t02 pcix2ad27 n03 gnd p03 pcix2gnt1 * r03 pcix2clk t03 gnd n04 pcix2req1 * p04 pcix2irdy r04 pcix2vref0 t04 pcix2ad26 n05 v dd p05 peraddr13 r05 peraddr22 t05 v dd n06 peraddr11 p06 gnd r06 gnd t06 pcix2m66en n07 gnd p07 peraddr14 r07 peraddr21 t07 gnd n08 peraddr10 p08 peraddr12 r08 peraddr23 t08 pcix2cap n09 v dd p09 reserved r09 perbe0 * t09 v dd n10 reserved p10 ov dd r10 p2v dd t10 pcix2idsel n11 gnd p11 reserved r11 reserved t11 gnd n12 reserved p12 reserved r12 reserved t12 reserved n13 v dd p13 gnd r13 gnd t13 v dd n14 gnd p14 ov dd r14 p0v dd t14 gnd n15 gnd p15 p1v dd r15 sv dd t15 gnd n16 v dd p16 gnd r16 gnd t16 v dd n17 reserved p17 reserved r17 reserved t17 reserved n18 gnd p18 reserved r18 reserved t18 gnd n19 memdata47 p19 sv dd r19 sv dd t19 memdata52 n20 v dd p20 memdata40 r20 memdata53 t20 v dd n21 memdata44 p21 memdata38 r21 dm6 t21 memdata55 n22 gnd p22 banksel1 r22 memdata49 t22 gnd n23 memdata43 p23 gnd r23 gnd t23 banksel0 n24 v dd p24 memdata54 r24 memdata50 t24 v dd n25 memdata24 p25 memdata29 r25 dqs6 t25 memdata19 n26 gnd p26 dm3 r26 dqs6 t26 gnd n27 dqs3 p27 sv dd r27 sv dd t27 memdata20 n28 dqs3 p28 memdata25 r28 memdata26 t28 memdata23 table 4. signals listed by ba ll assignment (sheet 4 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 51 data sheet u01 v dd v01 pcix2ad24 w01 pcix2ad17 y01 pcix2ad11 u02 pcix2be3 v02 p2v dd w02 pcix2ad16 y02 gnd u03 pcix2ad25 v03 pcix2be2 w03 pcix2ad18 y03 pcix2ad10 u04 pcix2ad28 v04 pcix2ad20 w04 pcix2ad19 y04 pcix2ad08 u05 pcix2req0 * v05 gnd w05 pcix2ad31 y05 v dd u06 pcix2perr v06 pcix2reset w06 pcix2ad30 y06 pcix2ad21 u07 pcix2inta v07 p2v dd w07 pcix2ad29 y07 gnd u08 pcix2frame v08 pcix2serr w08 pcix2calg0 y08 pcix2ad22 u09 pcix2ecc3 v09 gnd w09 pcix2calr0 y09 v dd u10 pcix2vref1 v10 pcix2vc w10 pcix2ecc1 y10 pcix0devsel u11 reserved v11 p2v dd w11 pcix0perr y11 gnd u12 psro v12 reserved w12 pcix0trdy y12 pcix0req3 * u13 reserved v13 gnd w13 pcix0irdy y13 v dd u14 reserved v14 reserved w14 p0v dd y14 pcix0idsel u15 reserved v15 reserved w15 p0v dd y15 pcix0ad59 u16 reserved v16 gnd w16 pcix0ad60 y16 v dd u17 psro v17 reserved w17 pcix0ad42 y17 pcix0ad41 u18 reserved v18 sv dd w18 pcix0ad38 y18 gnd u19 dm7 v19 we w19 ecc6 y19 pcix0calg1 u20 memdata57 v20 gnd w20 memdata63 y20 v dd u21 memdata58 v21 memdata62 w21 memdata60 y21 ecc2 u22 memdata51 v22 sv dd w22 memdata56 y22 gnd u23 memdata48 v23 memdata61 w23 memdata22 y23 ecc1 u24 memdata30 v24 gnd w24 memdata59 y24 v dd u25 dqs2 v25 dm2 w25 memdata15 y25 memdata12 u26 dqs2 v26 memdata21 w26 dqs7 y26 memdata08 u27 memdata16 v27 sv dd w27 dqs7 y27 gnd u28 v dd v28 memdata17 w28 memdata18 y28 memdata11 table 4. signals listed by ba ll assignment (sheet 5 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor 52 amcc proprietary revision 1.23 - sept 26, 2006 data sheet aa01 pcix2ad09 ab01 pcix2ad04 ac01 pcix2ad06 ad01 pcix2ad03 aa02 pcix2be1 ab02 p2v dd ac02 pcix2ad07 ad02 gnd aa03 pcix2ad12 ab03 pcix2be0 ac03 pcix2ad00 ad03 pcix0ecc5 aa04 pcix2ad13 ab04 pcix2ad05 ac04 pcix2ad01 ad04 pcix0ad28 aa05 pcix2ad23 ab05 gnd ac05 pcix2ad02 ad05 v dd aa06 pcix2ecc5 ab06 pcix2ad14 ac06 pcix2ad15 ad06 pcix0ad21 aa07 pcix2ecc2 ab07 p0v dd ac07 pcix2par * ad07 gnd aa08 pcix0calg0 ab08 pcix0calr0 ac08 pcix0ad10 ad08 pcix0ad11 aa09 pcix0ad09 ab09 gnd ac09 pcix0ad08 ad09 v dd aa10 pcix0ad13 ab10 pcix0ad14 ac10 pcix0vref1 ad10 pcix0ad12 aa11 pcix0ad07 ab11 p0v dd ac11 pcix0vref0 ad11 gnd aa12 pcix0req2 * ab12 pcix0inta ac12 pcix0frame ad12 pcix0serr aa13 pcix0cap ab13 gnd ac13 pcix0gnt2 * ad13 v dd aa14 pcix0ad58 ab14 pcix0ad56 ac14 gnd ad14 pcix0m66en aa15 pcix0ad63 ab15 pcix0ad57 ac15 gnd ad15 pcix0ad55 aa16 pcix0ad61 ab16 gnd ac16 pcix0ad62 ad16 v dd aa17 pcix0ad43 ab17 pcix0ad45 ac17 pcix0ad46 ad17 pcix0ad36 aa18 pcix0ad37 ab18 p0v dd ac18 pcix0ad48 ad18 gnd aa19 pcix0calr1 ab19 pcix0ad47 ac19 pcix0ad44 ad19 memaddr02 aa20 memvref0 ab20 gnd ac20 pcix0ad39 ad20 v dd aa21 memvref1 ab21 memdcfdbkd ac21 memdcfdbkr ad21 ba0 aa22 memodt0 ab22 p0v dd ac22 memodt1 ad22 gnd aa23 ecc5 ab23 memdata14 ac23 ecc3 ad23 ecc4 aa24 dm8 ab24 gnd ac24 ecc0 ad24 v dd aa25 memdata13 ab25 dqs8 ac25 memdata07 ad25 dqs0 aa26 dm1 ab26 dqs8 ac26 memdata03 ad26 dqs0 aa27 dqs1 ab27 sv dd ac27 memdata04 ad27 gnd aa28 dqs1 ab28 memdata09 ac28 memdata10 ad28 memdata00 table 4. signals listed by ba ll assignment (sheet 6 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 53 data sheet ae01 pcix0ad30 af01 ap0v dd ag01 ap0gnd ah01 v dd ae02 pcix0ad31 af02 pcix0ad26 ag02 gnd ah02 pcix0ad24 ae03 pcix0ad27 af03 p2v dd ag03 pcix0ecc2 ah03 pcix0ad25 ae04 pcix2ecc6 af04 pcix0ad20 ag04 pcix0ad22 ah04 pcix0ecc3 ae05 pcix0ad29 af05 pcix0ad19 ag05 gnd ah05 pcix0ecc4 ae06 pcix0be3 af06 pcix0ad16 ag06 pcix0par * ah06 pcix0ack64 * ae07 pcix0be2 af07 pcix0ad17 ag07 p0v dd ah07 pcix0ad15 ae08 pcix0ad18 af08 pcix0ad23 ag08 pcix0req64 * ah08 pcix0ad05 ae09 pcix0ad03 af09 pcix0be0 ag09 gnd ah09 pcix0ad06 ae10 pcix0ad02 af10 pcix0ad04 ag10 pcix0be1 ah10 pcix0vc ae11 pcix0ad01 af11 pcix0gnt3 * ag11 p0v dd ah11 pcix0req0 * ae12 pcix0ad00 af12 pcix0clk ag12 pcix0req1 * ah12 v dd ae13 pcix0stop af13 gnd ag13 pcix0gnt1 * ah13 pcix0reset ae14 pcix0be7 af14 pcix0gnt0 * ag14 p0v dd ah14 pcix0par64 * ae15 pcix0ad54 af15 pcix0ad52 ag15 p0v dd ah15 pcix0ad53 ae16 pcix0be6 af16 gnd ag16 pcix0ad50 ah16 pcix0be4 ae17 pcix0ad40 af17 pcix0ad51 ag17 pcix0be5 ah17 v dd ae18 pcix0ad32 af18 pcix0ad33 ag18 p0v dd ah18 pcix0ad49 ae19 memaddr03 af19 memaddr11 ag19 pcix0ad35 ah19 pcix0ad34 ae20 ba1 af20 ecc7 ag20 gnd ah20 memaddr12 ae21 memaddr01 af21 memaddr07 ag21 memaddr10 ah21 memaddr13 ae22 memaddr06 af22 memaddr08 ag22 p0v dd ah22 memaddr04 ae23 clken0 af23 memaddr00 ag23 memaddr09 ah23 memaddr05 ae24 clken1 af24 memaddr14 ag24 gnd ah24 ras ae25 ba2 af25 memdata06 ag25 memclkout0 ah25 cas ae26 dm0 af26 sv dd ag26 memclkout0 ah26 memclkout1 ae27 memdata01 af27 memdata02 ag27 gnd ah27 memclkout1 ae28 memdata05 af28 a2v dd ag28 a2gnd ah28 v dd table 4. signals listed by ba ll assignment (sheet 7 of 7) ball signal name ball signal name ball signal name ball signal name
powerpc 440sp embedded processor 54 amcc proprietary revision 1.23 - sept 26, 2006 data sheet signal description the ppc440sp embedded controller is packaged in a 783-ba ll flip-chip plastic ball grid array (fc-pbga). the following table describes the package level pinout. in the table ?signal functional description? on page 56, each i/o signal is listed along with a short description of its function. active-low signals (for example, ras ) are marked with an overline. please see ?signals listed alphabetically? on page 17 for the pin (ball) number to which each signal is assigned. table 5. pin summary group no. of pins signal pins, non-multiplexed 496 signal pins, multiplexed 32 total signal pins 528 axv dd 2 apxv dd 3 axgnd 5 ov dd (3.3v i/os) 15 pxv dd (3.3v-1.5v pci) 31 sv dd g(2.5-1.8v sdram) 10 v dd (1.5v logic) 47 gnd 92 total power pins 205 reserved 50 total pins 783
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 55 data sheet multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. the signal names shown in signal functional description are not accompan ied by signal names that might be multiplexed on the same pin. if you need to know what, if any, signals are multiplexed with a pa rticular signal, look up the name in ?signals listed alphabetica lly? on page 17. it is expected that in any single application a particular pin will always be programmed to serve the same functi on. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. strapping pins one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during no rmal operation (see ?strapping? on page 83). note that these are not multiplexed pins since the function of the pins is not programmable. multipurpose signals in addition to multiplexing, some pins are also multi- purpose. for example, the pcix 0ack can function instead as pcix0ecc1 depending on the pci interface mode of operation.
powerpc 440sp embedded processor 56 amcc proprietary revision 1.23 - sept 26, 2006 data sheet table 6. signal functional description (sheet 1 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci-x0:2 interfaces pcix0:1ack64 /pcix0:1ecc1 ack64 or ecc1. normally used as ack64 indicating that the target can transfer data using 64 bits. or used as ecc1 for pci-x mode 2. i/o 3.3v pci or 1.5v pci for mode 2 4 pcix0:1ad63:00 pcix2ad31:00 address/data bus (bidirectional) for pci-x0 and pci-x1. address/data bus (bidirectional) for pci-x 2. i/o 3.3v pci or 1.5v pci for mode 2 pcix0:1be7:0 pcix2be3:0 pci-x byte enables for pci-x0 and pci-x1 . pci-x byte enables for pci-x2 . i/o 3.3v pci or 1.5v pci for mode 2 pcix0:1calg0:1 pcix2calg0 external calibration resistor pads (g) for pci-x0:2 (one pad for each 32-bit bus group). ina pcix0:1calr0:1 pcix2calr0 external calibration resist or pads (r) for pcix0:2 (one pad for each 32-bit bus group). ina pcix0:2cap capable of pci-x operation. this analog input is sampled to configure pci and determine the state of the pcix0:2vc output signal: 0.00v dd (0.0v) = conventional pci & pcix0:2vc = 0 0.49v dd (1.6v) = pci-x ddr 266 mode 2 & pcix0:2vc = 1 0.75v dd (2.5v) = pci-x 66 & pcix0:2vc = 0 1.00v dd (3.3v) = pci-x 133 & pcix0:2vc = 0 ina pcix0:2clk provides timing to the pci in terface for pci transactions. note: if the pci-x interface is no t being used, drive this pin with a 3.3v clock signal at a frequency between 1 and 66mhz i 3.3v pci pcix0:2devsel indicates the driving device has decoded its address as the target of the current access. i/o 3.3v pci 4 pcix0:2ecc5:2 pcix2ecc1 pcix2ecc6 ecc check bits 5?2. all ecc bi ts are valid only for pcix ddr mode 2. note: see pcix0:2par for ecc0. see pcix0:1ack64 for ecc1. see pcix0:1req64 for ecc6. see pcix0:1par64 for ecc7. i/o 3.3v pci or 1.5v pci for mode 2 pcix0:2frame driven by the current master to indicate beginning and duration of an access. i/o 3.3v pci 4 pcix0:2gnt0:1 pcix0:1gnt2:3 indicates that the specified agent is granted access to the bus. when using an external pci/pci-x arbiter, connect the external arbiter's grant line to this signal. i/o 3.3v pci 4 pcix0:2idsel used as a chip select during configuration read and write transactions. i 3.3v pci 5 pcix0:2inta level sensitive pci interrupt. o 3.3v pci pcix0:2irdy indicates initiating agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 57 data sheet pcix0m66en capable of 66mhz operation. i 3.3v pci or 1.5v pci for mode 2 pcix1:2m66en capable of 66mhz operation. i 3.3v pci or 1.5v pci for mode 2 5 pcix0:2par/pcix0:2ecc0 even parity indicator or ecc0. normally used to indicate even parity across pciad31:00 and be3:0. used as ecc0 for pcix0:2 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 pcix0:1par64/pcix0:1ecc7 even parity indicator or ecc7. normally used to indicate even parity across pciad63:32 and be7:4 for pci0 and pci1. or used as ecc7 for pcix0:1 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 pcix0:2perr reports data parity errors during all pci transactions except a special cycle. i/o 3.3v pci 4 pcix0:2req0:1 pcix0:1req2:3 an indication to the pci-x arbiter that the specified agent wishes to use the bus . when using an external pci/pci-x arbiter, connect the external arbiter's request line to this signal. i/o 3.3v pci 4 pcix0:1req64 /pcix0:1ecc6 request 64-bit transfer or ecc6. normally used by the current bus master to indicate a 64-bit transfer. or used as ecc6 for pcix2 mode 2. i/o 3.3v pci or 1.5v pci for mode 2 4 pcix0:2reset sets pci device registers and logic to a consistent state. o 3.3v pci pcix0:2serr reports address parity errors, data parity errors on the special cycle command, or other catastrophic system errors. i/o 3.3v pci 4 pcix0:2stop indicates the current target is requesting the master to stop the current transaction. i/o 3.3v pci 4 pcix0:2trdy i ndicates the target agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pcix0:2vc voltage control output. used to control the voltage regulator supplying the pci i/o voltage. see pci-xcap signal. 0 = 3.3v (pci i/o) 1 =1.5v (pci-x ddr) o 3.3(1.5)v pci pcix0:2vref0:1 voltage reference input for pci-x mode 2/ddr (1.5v) i/o. not used for pci or pci-x mode 1. ivpcixddr 5 table 6. signal functional description (sheet 2 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor 58 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ddr sdram interface ba0:2 bank address supporting up to eight internal banks. o 2.5(1.8)v ddr sdram banksel0:1 selects up to two external ddr sdram banks. o 2.5(1.8)v ddr sdram cas column address strobe. o 2.5(1.8)v ddr sdram clken0:1 clock enable. o ne for each external bank. o 2.5(1.8)v ddr sdram dm0:8 memory write data byte lane masks. memdm8 is the byte lane mask for the ecc byte lane. o 2.5(1.8)v ddr sdram dqs0:8 dqs0:8 byte lane data strobe. dqs8 is the data strobe for the ecc byte lane. these signal s are differential pairs. i/o 2.5(1.8)v ddr sdram diff ecc0:7 ecc check bits 0:7. i/o 2.5(1.8)v ddr sdram memaddr14:00 memory address bus. note: memaddr14 is the most significant bit (msb). o 2.5(1.8)v ddr sdram memclkout0:1 memclkout0:1 subsystem clocks. these si gnals are differential pairs. o 2.5(1.8)v ddr sdram diff memdata63:00 memory data bus. note: memdata63 is the most significant bit (msb). i/o 2.5(1.8)v ddr sdram memdcfdbkd feedback driver, for i/o timing measurements. o 2.5(1.8)v ddr sdram memdcfdbkr feedback receiver. connect externally to memdcfdbkd. i 2.5(1.8)v ddr sdram memodt0:1 memory on-die termination control. o 2.5(1.8)v ddr sdram memvref0 memory reference voltage (sv ref ) input. i 2.5(1.8)v ddr sdram volt ref rcv memvref1 memory reference voltage (sv ref ) supplemental input. i 2.5(1.8)v ddr sdram volt ref sup ras row address strobe. o 2.5(1.8)v ddr sdram we write enable. o 2.5(1.8)v ddr sdram table 6. signal functional description (sheet 3 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 59 data sheet ethernet interface emccd collision detection. i 3.3v lvttl emccrs carrier sense. i 3.3v lvttl emcmdclk management data clock. o 3.3v lvttl emcmdio transfer command and status information between mii and phy. i/o 3.3v lvttl emcrxd0:7 receive data. i 3.3v lvttl emcrxdv receive data valid. i 3.3v lvttl emcrxerr receive error. i 3.3v lvttl emcrxclk receive clock. i 3.3v lvttl emcrefclk reference clock. i 3.3v lvttl emctxclk transmit clock. i 3.3v lvttl emcgtxclk ethernet gigabit transmit clock. o 3.3v lvttl emctxd0:7 transmit data. o 3.3v lvttl emctxen transmit data enabled. o 3.3v lvttl emctxerr, transmit error. o 3.3v lvttl external slave peripheral interface peraddr00:23 peripheral address bus. note: peraddr00 is the most significant bit (msb). o3.3v lvttl 1 perbe0 external peripheral data bus byte enable. o 3.3v lvttl 1 perblast used by the peripheral controller to indicates the last transfer of a memory access. o3.3v lvttl percs0:2 external peripheral device select. o 3.3v lvttl perdata0:7 peripheral data bus. note: perdata0 is the most significant bit (msb). i/o 3.3v lvttl 1 peroe used by peripheral controll er or dma controller depending upon the type of transfer involved. when the ppc440sp is the bus master, it enables the selected device to drive the bus. o3.3v lvttl perpar0 external peripheral data bus byte parity. i/o 3.3v lvttl 1 perready used by a peripheral slave to indicate it is ready to transfer data. i3.3v lvttl perr/w used as output by the peripheral controller. high indicates a read from memory, low indicates a write to memory. o3.3v lvttl 1 perwe write enable. o 3.3v lvttl perclk peripheral clock used by synchr onous peripheral slaves. o 3.3v lvttl pererr external error used as an input to record external slave peripheral errors. i 3.3v lvttl 1, 5 table 6. signal functional description (sheet 4 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor 60 amcc proprietary revision 1.23 - sept 26, 2006 data sheet uart peripheral interface uartserclk serial clock input that prov ides an alternative to the internally generated serial clock. used in cases where the allowable internally generated clock rates are not satisfactory. i 3.3v lvttl 1, 4 uart0_rx uart0 receive data. i 3.3v lvttl 1, 4 uart0_tx uart0 transmit data. o 3.3v lvttl 4 uart0_dcd uart0 data carrier detect. i 3.3v lvttl 6 uart0_dsr uart0 data set ready. i 3.3v lvttl 6 uart0_cts uart0 clear to send. i 3.3v lvttl 1, 4 uart0_dtr uart0 data terminal ready. o 3.3v lvttl 4 uart0_rts uart0 request to send. o 3.3v lvttl 4 uart0_ri uart0 ring indicator. i 3.3v lvttl w/pull-up 1, 4 uart1_rx uart1 receive data. i 3.3v lvttl 1, 4 uart1_tx uart1 transmit data. o 3.3v lvttl 1, 4 uart1_dsr /cts uart1 data set ready or clear to send. the choice is determined by a dcr register bit setting. i 3.3v lvttl 1, 4 uart1_dtr/rts uart1 request to send or data terminal ready. the choice is determined by a dcr register bit setting. o 3.3v lvttl 1, 4 uart2_rx uart2 receive data. i 3.3v lvttl 1, 4 uart2_tx uart2 transmit data. o 3.3v lvttl 1, 4 iic peripheral interface iic0sclk iic0 serial clock. i/o 3.3v iic 1, 2 iic0sda iic0 serial data. i/o 3.3v iic 1, 2 iic1sclk iic1 serial clock. i/o 3.3v iic 1, 2 iic1sda iic1 serial data. i/o 3.3v iic 1, 2 interrupts interface irq0:5 external interrupt requests 0 through 5. i 3.3v lvttl 1, 5 table 6. signal functional description (sheet 5 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 61 data sheet system interface halt halt from external debugger. i 3.3v lvttl 1, 4 gpio00:17 general purpose i/o 0 through 17. to access these functions, software must set dcr register bits. i/o 3.3v lvttl gpio18:29 general purpose i/o 18 through 29. to access these functions, software must set dcr register bits. i/o 3.3v pci gpio30:31 general purpose i/o 30 through 31. to access these functions, software must set dcr register bits. i/o 3.3v lvttl sysclk main system clock input. i 3.3v lvttl syserr set to 1 when a machine check is generated. o 3.3v lvttl syspartsel not used. i na 3 sysreset main system reset. external logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by software. i 3.3v lvttl 1, 2 hisrrst hardware initiated self-refresh and system reset. i 3.3v lvttl 1, 2 extreset external reset. during the ppc440sp?s reset phase, this signal is at down level. o3.3v lvttl testen test enable. i 3.3v lvttl 3 tmrclk processor timer external input clock. i 3.3v lvttl jtag interface tck test clock. i 3.3v lvttl 1 tdi test data in. i 3.3v lvttl w/pull-down 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl with pull-up 1 trst test reset. during chip power-up, this signal must be low from the start of vdd ramp-up until at least 16 sysclk cycles after vdd is stable in order to initialize the jtag controller. i 3.3v lvttl with pull-up 5 trace interface trcclk trace data capture clock, r uns at 1/4 the frequency of the processor. o3.3v lvttl trcbs0:2 trace branch execution status. o 3.3v lvttl trces0:4 trace execution status is presented every fourth processor clock cycle. o3.3v lvttl trcts0:6 additional information on trace execution and branch status. o3.3v lvttl table 6. signal functional description (sheet 6 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor 62 amcc proprietary revision 1.23 - sept 26, 2006 data sheet power axgnd analog ground. na na apxv dd analog voltage?1.5v. filtered voltages input for pci plls (analog circuits). note: a separate filter for all analog voltages is recommended. na na axv dd analog voltage?1.5v. filtered voltages input for s ystem plls (analog circuits). note: a separate filter for all analog voltages is recommended. na na gnd logic and i/o ground. na na ov dd i/o supply (except ddr sdram and pci-x)? 3.3v. na na pxv dd pci-x i/o voltage supply. note: pci-x operates at 3.3v. pci-x 266 ddr operates at 1.5v na na sv dd ddr sdram i/o voltage supply. note: ddr sdram operates at 2.5v ddr2 sdram operates as 1.8v na na v dd logic voltage supply?1.5v. na na psro psro performance screen ring oscillator. note: all psro signals should be connected to logic ground (gnd). na na reserved reserved do not connect voltage, ground, or any signals to these pins. na na table 6. signal functional description (sheet 7 of 7) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to 3.3v) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to 3.3v) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 63 data sheet device characteristics table 7. absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or be yond these maximum ratings can cause permanent damage to the device. none of the performance specifications contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes 1.5v supply voltage (internal logic) v dd 0 to +1.6 v 3.3v supply voltage (i/o interface, except ddr sdram) ov dd 0 to +3.6 v 3.3v supply voltage (pci-x i/o) pxv dd 0 to +3.6 v 1.5v supply voltage (pci-x ddr i/o) pxv dd 0 to +1.6 v 1.5v supply voltages (system plls) axv dd 0 to +1.6 v 1 1.5v supply voltages (pci-x plls) apxv dd 0 to +1.6 v 1 2.5v supply voltage (ddr sdram logic) sv dd 0 to +2.7 v 1.8v supply voltage (ddr2 sdram logic) sv dd 0 to +1.95 v 3.3v lvttl receivers input voltage v in 0 to +3.6 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c2 notes: 1. the analog voltages used for the on-chip p lls can be derived from the logic voltage, but must be filtered before entering the ppc440sp. a separate filter, as shown below, is recommended for each voltage: 2. this value is not a specificatio n of the operational temperature range, it is a stress rating only. v dd c axv dd , apxv dd l l ? smt ferrite bead chip, murata blm31a700s c ? 0.1 f ceramic
powerpc 440sp embedded processor 64 amcc proprietary revision 1.23 - sept 26, 2006 data sheet table 8. package thermal specifications thermal resistance values for the ppc440sp packa ge in a convection environment are as follows: parameter symbol airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) junction-to-case thermal resistance jc 0.6 0.6 0.6 c/w 1 case-to-ambient thermal resistance (w/o heat sink) ca 15.5 13.1 11.9 c/w 2 range minimum maximum junction-to-ball (typical) jb 6.5 6.5 c/w 3 notes: 1. case temperature, t c , is measured at top center of case surface with dev ice soldered to circuit board. for this part the junction temperature and the case temperature are essentially identical. 2. the case-to-ambient thermal resistance is measured in a jedec jesd51-6 standard environment; and may not accurately predict thermal performance in production equipment environments. the operational case temperature must be maintained. 3. 6.5 c/w is the theoretical jb using an infinite heat sink. the larger number applies to the module mounted on a 1.8mm thick, 2p card using 1oz. copper power planes, with an effective heat transfer area of 75mm 2 . table 9. recommended dc operat ing conditions (sheet 1 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage 533 mhz v dd +1.4 +1.5 +1.6 v 4 logic supply voltage 667 mhz v dd +1.425 +1.5 +1.575 v 4 i/o supply voltage ov dd +3.0 +3.3 +3.6 v 4 pci-x i/o supply voltage pci-x ddr pxv dd +3.0 1.425 +3.3 1.5 +3.6 1.575 v4 voltage reference input for pci-x ddr mode 2 pcix0vref0:1 +1.425 +1.5 +1.575 v 4 ddr1 sdram supply voltage ddr2 sdram sv dd +2.3 1.7 +2.5 (2.6) 1.8 +2.7 1.9 v4 system pll supply voltages axv dd +1.4 +1.5 +1.6 v 3 pci-x pll supply voltages apxv dd +1.4 +1.5 +1.6 v 3 ddr1 sdram reference voltage sv ref +1.15 +1.25 +1.35 v 3 ddr2 sdram reference voltage sv ref 0.49 x sv dd 0.50 x sv dd 0.51 x sv dd v
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 65 data sheet input logic high (2.5v ddr sdram) v ih sv ref +0.18 sv dd +0.3 v2 input logic high (1.8v ddr2 sdram) sv ref +0.125 sv dd +0.3 v input logic high (2.5v cmos, 3.3v tolerant receiver) 1.7 v input logic high (3.3v pci-x) 0.5ov dd ov dd +0.5 v1 input logic high (1.5v pci-x ddr) v ref +0.10 v i/o +0.50 v1 input logic high (3.3v lvttl) +2.0 +3.6 v input logic low (2.5v ddr sdram) v il -0.3 sv ref -0.18 v input logic low (1.8v ddr2 sdram) -0.3 sv ref -0.125 v input logic low (2.5v cmos, 3.3v tolerant receiver) 0.7 v input logic low (3.3v pci-x) -0.5 0.35ov dd v1 input logic low (1.5v pci-x ddr) -0.5 v ref -0.10v v1 input logic low (3.3v lvttl) 0 +0.8 v output logic high (2.5v ddr sdram) v oh +1.95 sv dd v output logic high (1.8v ddr2 sdram) sv dd -0.45 sv dd v output logic high (2.5v cmos, 3.3v tolerant receiver) 2.0 v output logic high (3.3v pci-x) 0.9ov dd ov dd v1 output logic high (1.5v pci-x ddr) v1 output logic high (3.3v lvttl) +2.4 ov dd v output logic low (2.5v ddr sdram) v ol 00.45v output logic low (1.8v ddr2 sdram) 0 0.45 v output logic low (2.5v cmos, 3.3v tolerant receiver) 0.4 v output logic low (3.3v pci-x) 0.1ov dd v1 output logic low (1.5v pci-x ddr) v1 output logic low (3.3v lvttl) 0 +0.4 v input leakage current (with no internal pull-up or pull-down) i il1 01 a input leakage current (with internal pull-down) i il2 0 (lpdl) 200 (mpul) ? 5 input leakage current (with internal pull-up) i il3 -150 (lpdl) 0 (mpul) a5 table 9. recommended dc operat ing conditions (sheet 2 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
powerpc 440sp embedded processor 66 amcc proprietary revision 1.23 - sept 26, 2006 data sheet input max allowable overshoot (3.3v lvttl) v imao +3.9 v input max allowable undershoot (3.3v lvttl) v imau -0.6 v output max allowable overshoot (3.3v lvttl) v omao +3.9 v output max allowable undershoot (3.3v lvttl) v omau3 -0.6 v case temperature t c -40 +100 c6 notes: 1. pci-x drivers meet pci-x specifications. 2. sv ref = sv dd /2 3. the analog voltages used for the on-chip plls can be derived fr om the logic voltage, but must be filtered before entering the ppc440sp. see ?absolute maximum ratings? on page 63. 4. power supply sequencing: it is recommended that the 1.5v vdd of the core reach its nominal value before applying power to the i/os. voltage applied to i/os from an external source must not be allowed to exceed the 0vdd ramp. a power down cycle must complete (0vdd and vdd are below 0.4v) before a new power up cycle is started. 5. lpdl is least positive down level; mpul is most positive up level. 6. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. table 10. input capacitance parameter symbol maximum unit notes group 1 (2.5v sstl i/o) c in1 5.2 pf group 2 (3.3v lvttl i/o) c in2 7.1 pf group 3 (pci-x i/o) c in3 5.7 pf group 4 (receivers) c in4 6.9 pf group 5 (3.3v tolerant cmos i/o) c in5 3.4 pf table 9. recommended dc operat ing conditions (sheet 3 of 3) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 67 data sheet clock test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in the table ?recommended dc operating conditions.? ac specifications are characterized with v dd = 1.5v, t c = +85 c and a 10pf test load as shown in the figure to the right. table 11. dc power supply loads parameter symbol minimum typical maximum unit notes v dd (1.5v) active operating current i dd 3000 ma 2 ov dd (3.3v) active operating current i odd 40 ma 2 pxv dd (3.3v) active operating current i pdd 730 ma 2 pxv dd (1.5v) active operating current i pdd 1600 ma sv dd (2.5v) active operating current i sdd 1100 ma 2 sv dd (1.8v) active operating current i sdd 750 ma 2 axv dd (1.5v) input current i add 33 ma 1, 2 apxv dd (1.5v) input current i apdd 33 ma 1, 2 notes: 1. see ?absolute maximum ratings? on page 63 for filter recommendations. 2. valid only for cpu/plb/opb = 533.33/133.33/66.66 mhz. output pin 10pf c
powerpc 440sp embedded processor 68 amcc proprietary revision 1.23 - sept 26, 2006 data sheet figure 4. clock timing waveform table 12. clocking specifications symbol parameter min max units sysclk input f c frequency 33.33 83.33 mhz t c period 12 30 ns t cs edge stability (cycle-t o-cycle jitter) ? 0.15 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns pll vco f c frequency 600 1333.33 mhz t c period 0.75 1.66 ns processor clock (cpu clock) f c frequency 400 666.66 mhz t c period 1.5 2.5 ns memclkout f c frequency 200 333.33 mhz t c period 3 5 ns t ch high time 45% of nominal period 55% of nominal period ns opb clock and perclk f c frequency ? 83.33 mhz t c period 12 ? ns mal clock f c frequency 45 83.33 mhz t c period 12 22.2 ns t cl t ch t c
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 69 data sheet spread spectrum clocking care must be taken when using a spread spectrum cloc k generator (sscg) with the ppc440sp. this controller uses a pll for clock generation inside the chip. the accura cy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc440sp the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc440sp with one or more internal clocks at their maximum supported fr equency, the sscg can only lower the frequency. ? the maximum frequency deviation c annot exceed -1%, and the modulation frequency cannot exceed 40 khz. in some cases, on-board ppc440sp peripherals impose more stringent requirements. ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout sinc e it also tracks the modulation. ? for pci-x and pci 66 the maximum spread spectrum is -1% modulated between 30khz and 33khz. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is runni ng at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure that any sscg used with the ppc440sp meets the above requirements and does not adversely affect other aspects of the system.
powerpc 440sp embedded processor 70 amcc proprietary revision 1.23 - sept 26, 2006 data sheet i/o specifications table 13. peripheral interface clock timings parameter min max units notes pcixxclk input frequency (asynchronous mode) ? 133.33 mhz 2 pcixxclk period (asynchronous mode) 7.5 ? ns pcixxclk input high time 40% of nominal period 60% of nominal period ns pcixxclk input low time 40% of nominal period 60% of nominal period ns emcmdclk output frequency ? 2.5 mhz emcmdclk period 400 ? ns emcmdclk output high time 160 ? ns emcmdclk output low time 160 ? ns emctxclk input frequency 2.5 25 mhz emctxclk period 40 400 ns emctxclk input high time 35% of nominal period ? ns emctxclk input low time 35% of nominal period ? ns emcrxclk input frequency 2.5 25 mhz emcrxclk period 40 400 ns emcrxclk input high time 35% of nominal period ? ns emcrxclk input low time 35% of nominal period ? ns perclk output frequency (for sync. slaves) ? 83.33 mhz perclk period 12 ? ns perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency ? 1000/(2t opb +2ns) mhz 1 uartserclk period 2t opb +2 ?ns1 uartserclk input high time t opb +1 ?ns1 uartserclk input low time t opb +1 ?ns1 tmrclk input frequency ? 100 mhz tmrclk period 10 ? ns tmrclk input high time 40% of nomin al period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at an integral divisor ratio of the frequency of the plb clock. the maximum opb clock frequency is 83.33 mhz. refer to the clocking chapter of the ppc440sp embedded processor user?s manual for details. 2. when the pci-x interface is used to support a legacy pci interface, the maximum pcixclk frequency is 66.66mhz.
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 71 data sheet input/output timing these timing diagrams illustra te the relationship of the timing parameters defined in the i/o specific ation tables that follow. figure 5. input setup and hold timing waveform figure 6. output delay and hold timing waveform clock t is t ih min min inputs valid valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float ( high-z ) high ( drive ) low (drive)
powerpc 440sp embedded processor 72 amcc proprietary revision 1.23 - sept 26, 2006 data sheet table 14. i/o specifications?all speeds (sheet 1 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133.33mhz. pci-x input setup time requir ement is 1.2ns for 133.33mhz and 1.7ns for 66.66mhz. pci timings (in parentheses) are for a synchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 3. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci-x interfaces pcix0:2ack64 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:1ad63:00 pcix2ad31:00 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:1be7:0 pcix2be3:0 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2calg0:1 note 2 (2) 0.5(0) na na na na pcix0:2clk 2 pcix0:1calr0:1 dc dc na na na na async pcix0:2cap note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2clk note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2devsel note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2ecc5:2 na na 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2frame na na 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2gnt0 na na 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2gnt1 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:1gnt2:3 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2idsel note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2inta note 2 (2) 0.5(0) na na na na pcix0:2clk 2 pcix0:2irdy note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:1m66en note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2par note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:1par64 note 2 (2) 0.5(0) na na na na pcix0:2clk 2 pcix0:2perr note 2 (2) 0.5(0) na na na na pcix0:2clk 2 pcix0:1req0 note 2 (2) 0.5(0) na na na na pcix0:2clk 2 pcix0:1req1:3 pcix2req1 na na na na na na pcix0:2clk 2 pcix0:2req64 note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2reset note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2serr note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2stop note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2trdy note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2 pcix0:2vc note 2 (2) 0.5(0) 3.5(6) 0.7 (note 2) 0.5 1.5 pcix0:2clk 2
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 73 data sheet ethernet interface emccd na na 19.1 8.7 1, async emccrs na na 19.1 8.7 1, async emcmdclk na na na na 19.1 8.7 1, async emcmdio 19.1 8.7 emcmdclk emcrxd0:7 4 1 na na 19.1 8.7 emcrxclk emcrxdv 4 1 na na 19.1 8.7 emcrxclk emcrxerr na na 19.1 8.7 emcrxclk emcrxclk na na 19.1 8.7 1, async emcrefclk na na 19.1 8.7 emctxclk na na na na 19.1 8.7 1, async emcgtxclk na na na na 19.1 8.7 1, async emctxd0:7 na na 15 2 19.1 8.7 emctxclk emctxen na na 15 2 19.1 8.7 emctxclk emctxerr, na na 15 2 19.1 8.7 emctxclk internal peripheral interface iic0sclk na na na na 15.3 10.2 iic0sda 15.3 10.2 iic0sclk iic1sclk na na na na 15.3 10.2 iic1sda 15.3 10.2 iic0sclk uartserclk na na na na 19.1 8.7 uart0_rx na na uartserclk uart0_tx na na 19.1 8.7 uartserclk uart0_dcd na na 19.1 8.7 async uart0_dsr na na 19.1 8.7 async uart0_cts na na 19.1 8.7 async uart0_dtr na na 19.1 8.7 async uart0_ri na na async uart0_rts na na 19.1 8.7 async uart1_rx na na 19.1 8.7 uartserclk uart1_tx na na 19.1 8.7 uartserclk uart1_dsr/cts na na 19.1 8.7 async uart1_rts/dtr na na 19.1 8.7 async uart2_rx na na 19.1 8.7 uartserclk uart2_tx na na 19.1 8.7 uartserclk interrupts interface irq0:5 na na async jtag interface tdi n/a n/a n/a n/a async tms n/a n/a n/a n/a async tdo n/a n/a 19.1 8.7 async tck n/a n/a n/a n/a async trst n/a n/a n/a n/a async table 14. i/o specifications?all speeds (sheet 2 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133.33mhz. pci-x input setup time requir ement is 1.2ns for 133.33mhz and 1.7ns for 66.66mhz. pci timings (in parentheses) are for a synchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 3. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
powerpc 440sp embedded processor 74 amcc proprietary revision 1.23 - sept 26, 2006 data sheet system interface halt n/a n/a n/a n/a async gpio00:31 19.1 8.7 async sysclk n/a n/a n/a n/a n/a syserr n/a n/a 19.1 8.7 async syspartsel n/a n/a n/a n/a async sysreset n/a n/a async hisrrst 19.1 8.7 async testen n/a n/a n/a n/a async tmrclk n/a n/a n/a n/a n/a trace interface trcclk n/a n/a 19.1 8.7 trcbs0:2 19.1 8.7 trces0:4 19.1 8.7 trcts0:6 19.1 8.7 table 14. i/o specifications?all speeds (sheet 3 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133.33mhz. pci-x input setup time requir ement is 1.2ns for 133.33mhz and 1.7ns for 66.66mhz. pci timings (in parentheses) are for a synchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 3. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 75 data sheet table 15. i/o specifications?533mhz notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface peraddr00:23 n/a 1 6.2 0 19.1 8.7 perclk perbe0 27.7 12.8 perclk perblast n/a 1 5.7 n/a 19.1 8.7 perclk percs0:2 n/a n/a 5.9 0 19.1 8.7 perclk perdata0:7 1.2 1 6 0 19.1 8.7 perclk peroe n/a n/a 5.8 0 19.1 8.7 perclk perpar0 1.7 1 5.7 n/a 19.1 8.7 perclk perready 3.6 1 n/a n/a 19.1 8.7 perclk perr/w n/a 1 5.7 n/a 19.1 8.7 perclk perwe n/a n/a 5.7 0 19.1 8.7 n/a extreset n/a n/a n/a n/a 19.1 8.7 perclk perclk n/a n/a n/a n/a 19.1 8.7 plb clk pererr 1.2 n/a n/a 19.1 8.7 perclk
powerpc 440sp embedded processor 76 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ddr sdram i/o specifications the ddr sdram controller times its oper ation with internal plb clock signals and generates memclkout0 from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout0 is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout0 can be advanced with respect to the plb clock by means of the sdram0_clktr programming register. in a typical system, users advance memclkout by 90. this depends on the specific application and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the ppc440sp embedded processor user?s manual ). in the following sections, the label me mclkout0(0) refers to memclkout0 when it has not been phase-shifted, and memclkout0(90) refers to memclkout0 when it has been phase-advanced 90 . advancing memclkout0 by 90 creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to memclkout0(90). the rising edge of memclkout0(90) a ligns with the first rising edge of the dqs signal. the following ddr data is generated by means of simulation and includes logic, driver, package rlc, and lengths. it is not to be used as a circuit design recommendation. valu es are calculated over best case and worst case processes with speed, temperature, and voltage as follows: best case = fast process, -40c, +1.6v worst case = slow process, +85c, +1.4v note: in all the following ddr tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions. the signals are terminated as indicated in the figure be low for the ddr timing data in the following sections. figure 7. ddr sdram simulati on signal termination model 10pf 10pf memclkout0 memclkout0 120w 50w 30pf addr/ctrl/data/dqs v tt = sv dd /2 ppc440sp note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design will depend on many factors, including the type of memory used and the board layout.
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 77 data sheet table 16. ddr sdram output driver specifications signal path output current (ma) i/o h (maximum) i/o l (minimum) write data memdata00:07 15.2 15.2 memdata08:15 15.2 15.2 memdata16:23 15.2 15.2 memdata24:31 15.2 15.2 memdata32:39 15.2 15.2 memdata40:47 15.2 15.2 memdata48:55 15.2 15.2 memdata56:63 15.2 15.2 ecc0:7 15.2 15.2 dm0:8 15.2 15.2 memclkout0 15.2 15.2 memaddr00:12 15.2 15.2 ba0:1 15.2 15.2 ras 15.2 15.2 cas 15.2 15.2 we 15.2 15.2 banksel0:3 15.2 15.2 clken0:3 15.2 15.2 dqs0:8 15.2 15.2
powerpc 440sp embedded processor 78 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ddr sdram write operation the following timing chart shows the relationship between the signals involved in a ddr write operation. figure 8. ddr sdram write cycle timing ddr sdram read and write i/o timing?t sa and t ha note 1: clock speed is 333 mhz. t sa and t ha are referenced to memclkout. note 2: memory clock signal is shifted by 90 from the internal clock. table 17. ddr sdram read and write i/o timing?t sa and t ha signal name t sa (ns) t ha (ns) minimum minimum memaddr00:12 1.32 1.2 ba0:1 1.15 1.49 banksel0:3 1.12 1.52 clken0:3 1.29 1.45 cas 1.24 1.14 ras 1.29 1.48 we 1.35 1.43 dqs memdata plb clk memclkout addr/cmd t sa t ha t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout t ha = hold time for address and command signals from memclkout t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq)
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 79 data sheet ddr sdram clock to write dqs timing?t ds note 1: all of the dqs signals are referenced to memclkout. note 2: clock speed is 333 mhz. note 3: the tds values in the table include 1.5 3ns cycle at 333 mhz (3 ns 1.5 = 4.5 ns). note 4: to obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table and add 1.5 of the cycle time for the lower clock frequency (t ds - 4.5 + 1.5 t cyc ). ddr sdram write data to dqs timing?t sd and t hd note 1: t sd and t hd are measured under worst-case conditions. note 2: clock speed for the values in the following table is 333 mhz. table 18. ddr sdram clock to write dqs timing?t ds signal name t ds (ns) minimum maximum dqs0 4.76 5.07 dqs1 4.78 5.09 dqs2 4.78 5.10 dqs3 4.76 5.07 dqs4 4.79 5.11 dqs5 4.80 5.13 dqs6 4.81 5.11 dqs7 4.79 5.11 dqs8 4.77 5.07 table 19. ddr sdram write data to dqs timing?t sd and t hd signal name reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 0.58 0.64 memdata08:15, dm1 dqs1 0.62 0.55 memdata16:23, dm2 dqs2 0.62 0.60 memdata24:31, dm3 dqs3 0.63 0.57 memdata32:39, dm4 dqs4 0.68 0.54 memdata40:47, dm5 dqs5 0.67 0.52 memdata48:55, dm6 dqs6 0.62 0.61 memdata56:63, dm7 dqs7 0.65 0.55 ecc0:7, dm8 dqs8 0.63 0.61
powerpc 440sp embedded processor 80 amcc proprietary revision 1.23 - sept 26, 2006 data sheet ddr sdram read operation the read of the incoming data from the sdram is done on the rising and falling edges of the differential dqs signal. the data must be centered on these edges for correct operation. the ppc440sp can delay in very small increments the dqs by means of the programming of the mcif0_rodc[rqfd] register field. ddr sdram memclkout0 and read clock delay to accommodate timing variations intr oduced by the system designs using this chip, the three-stage data path shown in figure 9, below, is used to eliminate metastability and allow data sampling to be adjusted for minimum latency. the data is stored in the eight flip flops of stage 1, so that it can be transferred later, within an 8x period. figure 9. ddr sdram read data path. plb bus dq mcif0_rqdc[rqfd] programmed delay package mux read dqs c d ff: flip-flop q2 dqs (diff) ddr 1x clock mux data (x64) (x64) read fifo plb 1x clock stage 2 stage 1 stage 3 ff plb bus [0:63] [64:127] dqs rising dqs falling q3 0 6 4 2 (x64) coarse delay cycles driver rec memdcfdbkd memdcfdbkr ext feedback read start feedback data capture window ddr 1x clock mcif0_rdcc[rdss] mcif0_rfdc[rffd] mcif0_rfdc[rfos] stage 2 store oversampling dqs aligned cas lat delay feedback signal gen fine delay t1 t2 t3 t4 fine delay ff ff 7 5 3 1 1 0 7 edge sync edge sync upper lower signals pins ff q2_ovs ff fbk signal delay +1 compare ddr 1x clock oversampling clock read latency adjust circuit c d ff ff adjust
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 81 data sheet figure 10 shows the data strobe (dqs) and the data to be coincident. there is actually a slight skew as specified by the sdram specifications, and there can be additio nal skew due to loading and signal routing. it is recommended that the signal length for all of the eight dqs signals be matched. figure 10. ddr sdram memory data and dqs table 20. ddr sdram i/o read timing?t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 333.33mhz. 3. the time values in the table include 1/ 4 of a cycle at 166mhz (3ns x 0.25 = 0.75 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 0. 75 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., t sd - 0.75 + 0.25t cyc ). signal names reference signal read data vs dqs setup t sd (ns) read data vs dqs hold t hd (ns) memdata00:07 dqs0 0.00 1.00 memdata08:15 dqs1 0.00 1.00 memdata16:23 dqs2 0.00 1.00 memdata24:31 dqs3 0.00 1.00 memdata32:39 dqs4 0.00 1.00 memdata40:47 dqs5 0.00 1.00 memdata48:55 dqs6 0.00 1.00 memdata56:63 dqs7 0.00 1.00 ecc0:7 dqs8 0.00 1.00 dqs memdata tsd thd
powerpc 440sp embedded processor 82 amcc proprietary revision 1.23 - sept 26, 2006 data sheet the following figure shows the timing relationship between sdram ddr data at the input pin and the store of the data in stage 1. figure 11. ddr sdram read cycle timing example dqs at plb 1x clock data at pin d0 d2 high low feedback d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 data out stage 2 d1 d3 ddr 1x clock ddr 2x clock memclk (diff.) data out stage 1 (0) delayed dqs data out stage 1 (2) data out stage 1 (1) output 1x ddr clk cycle memcntl pin oversampling guard band valid store 1st data in stage 2 t1 t2 t3 t4
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 83 data sheet initialization the ppc440sp provides an option for setting initial parameters based on default values or by reading them from a serial ?bootstrap? rom attach ed to the iic0 bus. these options are defined by strapping on three external pins (see ?strapping? below). strapping while the sysreset input pin is low (system reset), the state of cert ain i/o pins is read to enable certain default initial conditions prior to ppc440sp start-up. the actual capture instant is the nearest sysclk edge before the deassertion of reset. these pins must be strapped usin g external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. they are used for strap functions only during reset. following reset they are used for normal functions. figure 21 lists the strapping pins along with their functions and strapping options: serial bootstrap rom during reset, if the serial device is enabled, initial conditions can be read fr om a rom connected to the iic0 port. in this case, at the de-assertion of sysreset, the ppc440sp se quentially reads up to 32 bytes from the rom device on the iic0 port and sets the sdr0_sds tp0 - sdr0_sdstp7 registers accordingly. the initialization settings a nd their default values are described in detail in the ppc440sp embedded processor user?s manual . table 21. strapping pin assignments function option pin strapping bit 0 a08 (uart0_dcd ) bit 1 c11 (uart0_dsr ) bit2 c09 (uart0_cts ) serial bootstrap rom is disabled (bit 0 off). refer to the iic bootstrap controller chapter in the ppc440sp embedded processor user?s manual for details. boot from ebc 0 0 boot from pci 0 1 serial bootstrap rom is enabled (bit 0 on). the options being selected are the iic0 slave address that responds with strapping data and reading 128 bits from the bootstrap rom. 0x54 1 0 0 0x50 1 1 0 serial bootstrap rom is enabled (bit 0 on). the options being selected are the iic0 slave address that responds with strapping data and reading 256 bits from the bootstrap rom. 0x54 1 0 1 0x50 1 1 1
powerpc 440sp embedded processor 84 amcc proprietary revision 1.23 - sept 26, 2006 data sheet document revision history revision date description 1.23 sept 26, 2006 corrected package thermal specifications table w here the letter q appeared instead of the symbol for theta. 1.22 sept 22, 2006 updated recommended dc operating conditions table. 1.21 sept 12, 2006 updated processor clock va lues in clocking specifications table. 1.20 june 27, 2006 updated recommended dc op conditions and signal functional description tables for pci-x ddr mode 2. 1.19 june 14, 2006 updated signal lists. 1.18 may 23, 2006 fixed doc issue for peroe signal in signal functional description table. updated clocking specifications table and serial bootstrap rom paragraph. 1.17 may 1, 2006 updated core package graphic in figure 3. a dded raid acceleration section to features, description, and functional details sections. 1.16 march 8, 2006 updated ordering and pvr information, part number list, and package diagram. gjg 1.15 march 7, 2006 removed dma statement from serial port featur e statement. removed reference to notes from perblast entry in signal functional description table. gjg 1.14 march 6, 2006 updated description of on-chip sram/l2 cache in introduction. gjg 1.13 february 9, 2006 updated signal function description table per jb, updated mailing address and copyright date in disclaimer. gjg 1.12 nov 15, 2005 clarified information about ddr sdram i/o spec ifications, updated note in system memory address map table per gb, updated ordering and pvr information, part number list, and package diagram, deleted preliminary from running head. gjg 1.11 july 12, 2005 updated leakage current info, case te mp range, ddr sdram signal termination graphic. gjg 1.10 may 23, 2005 changed pvr numbers for pass 2. corrected f unctional block diagram. updated write timing diagrams. gjg 1.09 mar 8, 2005 changed part numbers in ordering and pvr information section to reflect pass 2. removed text for unsupported cola component. gjg 1.08 feb 16, 2005 added table to document muxed usage of gpio signals. removed additional references to unsupported cola serial interface. reformatte d lof and lot to comply with amcc style. updated description information on first page, sections on dc power supply loads and recommended dc operating conditions. gjg 1.07 jan 19, 2005 remove references to unsupported cola serial interface. gjg 1.06 dec 21, 2004 update max case temp in recommended dc op conditions table to match ordering and pvr information table. gjg 1.05 dec 14, 2004 update order part number key information, ddr sdram read data path block diagram, and ddr sdram read cycle timing example diagram per gb. gjg 1.04 dec 01, 2004 update ordering and pvr information. gjg 1.03 oct 19, 2004 update table in recommended dc operating conditi ons section per docs issue database id #12. gjg 1.02 oct 12, 2004 update functional block diagram and text, signal functional description table, and recommended dc operating conditions secti on with gb?s comments. gjg 1.01 sept 08, 2004 first official draft. gjg 1.00 dec 31, 2003 create initial data sheet.
powerpc 440sp embedded processor revision 1.23 - sept 26, 2006 amcc proprietary 85 data sheet applied micro circuits corporation 215 moffett park dr., sunnyvale, ca 94089 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2006 applied micro circuits corporation.

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