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1 ? fn7344.1 EL5177 550mhz differential twisted-pair driver the EL5177 is a high bandwidth amplifier with an out put in differential form. it is primarily targeted for applications such as driving twisted-pair lines or any application where common mode injection is likely to occur. the input signal can be in either single-ended or differential form but the output is always in differential form. on the EL5177, two feedback inputs provide the user with the ability to set the device gain (stable at minimum gain of one.) the output common mode level is set by the reference pin (ref), which has a -3db bandwidth of 110mhz. generally, this pin is grounded but it can be tied to any voltage reference. both outputs (out+, out-) are short circuit protected to withstand temporary overload condition. the EL5177 is available in the 10-pin msop package and is specified for operation over the full -40c to +85c temperature range. see also el5174 (EL5177 in 8-pin msop.) features ? fully differential inputs, outputs, and feedback ? differential input range 2.3v ? 550mhz 3db bandwidth ? 1100v/s slew rate ? low distortion at 20mhz ? single 5v or dual 5v supplies ? 40ma maximum output current ? low power - 12.5ma typical supply current applications ? twisted-pair drivers ? differential line drivers ? vga over twisted-pair ? adsl/hdsl drivers ? single ended to differential amplification ? transmission of analog signals in a noisy environment pinout EL5177 (10-pin msop) top view ordering information part number package tape & reel pkg. dwg. # EL5177iy 10-pin msop - mdp0043 EL5177iy-t7 10-pin msop 7? mdp0043 EL5177iy-t13 10-pin msop 13? mdp0043 1 2 3 4 10 9 8 7 fbp in+ ref in- out+ vs- vs+ en 5 6 fbn out- - + data sheet september 23, 2003 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners.
2 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = 25c) supply voltage (v s + to v s -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v maximum output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c recommended operating temperature . . . . . . . . . .-40c to +85c v in , v inb , v ref . . . . . . . . . . v s - + 0.8v (min) to v s + - 0.8v (max) v in - v inb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s + = +5v, v s - = -5v, t a = 25c, v in = 0v, r ld = 1k ? , r f = 0, r g = open, c ld = 2.7pf, unless otherwise specified parameter description conditions min typ max unit ac performance bw -3db bandwidth a v = 1, c ld = 2.7pf 550 mhz a v = 2, r f = 500, c ld = 2.7pf 130 mhz a v = 10, r f = 500, c ld = 2.7pf 20 mhz bw 0.1db bandwidth a v = 1, c ld = 2.7pf 120 mhz sr slew rate v out = 3v p-p , 20% to 80% 800 1100 v/s t stl settling time to 0.1% v out = 2v p-p 10 ns t ovr output overdrive recovery time 20 ns gbwp gain bandwidth product 200 mhz v ref bw (-3db) v ref -3db bandwidth a v =1, c ld = 2.7pf 110 mhz v ref sr+ v ref slew rate - rise v out = 2v p-p , 20% to 80% 134 v/s v ref sr- v ref slew rate - fall v out = 2v p-p , 20% to 80% 70 v/s v n input voltage noise at 10khz 21 nv/ hz i n input current noise at 10khz 2.7 pa/ hz hd2 second harmonic distortion v out = 2v p-p , 5mhz -95 dbc v out = 2v p-p , 20mhz -94 dbc hd3 third harmonic distortion v out = 2v p-p , 5mhz -88 dbc v out = 2v p-p , 20mhz -87 dbc dg differential gain at 3.58mhz r ld = 300 ? , a v =2 0.06 % d differential phase at 3.58mhz r ld = 300 ? , a v =2 0.13 input characteristics v os input referred offset voltage 1.4 25 mv i in input bias current (v in +, v in -) -20 -14 -7 a i ref input bias current (v ref )0.52.34a r in differential input resistance 150 k ? c in differential input capacitance 1pf dmir differential mode input range 2.1 2.3 2.5 v cmir+ common mode positive input range at v in +, v in -3.4v cmir- common mode negative input range at v in +, v in --4.3v v refin + positive reference input voltage range v in + = v in - = 0v 3.4 3.7 v v refin - negative reference input voltage range v in + = v in - = 0v -3.3 -3 v EL5177
3 v refos output offset relative to v ref 50 100 mv cmrr input common mode rejection ratio v in = 2.5v 65 78 db gain gain accuracy v in = 1v 0.980 0.995 1.010 v output characteristics v out output voltage swing r l = 500 ? to gnd 3.6 3.8 v i out +(max) maximum source output current r l = 10 ?, v in + = 1.1v, v in - = -1.1v, v ref = 0 35 50 ma i out -(max) maximum sink output current -40 -30 ma r out output impedance 130 m ? supply v supply supply operating range v s + to v s -4.7511v i s(on) power supply current - per channel 10 12.5 14 ma i s(off) + positive power supply current - disabled en pin tied to 4.8v 76 120 a i s(off) - negative power supply current - disabled -200 -120 a psrr power supply rejection ratio v s from 4.5v to 5.5v 60 75 db enable t en enable time 130 ns t ds disable time 1.2 s v ih en pin voltage for power-up v s + - 1.5 v v il en pin voltage for shut-down v s + - 0.5 v i ih-en en pin input current high at v en = 5v 40 50 a i il-en en pin input current low at v en = 0v -6 -2.5 a electrical specifications v s + = +5v, v s - = -5v, t a = 25c, v in = 0v, r ld = 1k ? , r f = 0, r g = open, c ld = 2.7pf, unless otherwise specified (continued) parameter description conditions min typ max unit pin descriptions pin number pin name pin description 1 fbp non-inverting feedback input; resistor r f1 must be connected from this pin to v out 2 in+ non-inverting input 3 ref output common-mode control; the common-mode voltage of v out will follow the voltage on this pin 4 in- inverting input 5 fbn inverting feedback input; resistor r f2 must be connected from this pin to v out 6 out- inverting output 7en enabled when this pin is floating or the applied voltage v s + -1.5 8 vs+ positive supply 9 vs- negative supply 10 out+ non-inverting output EL5177
4 connection diagram 1 2 3 4 10 9 8 7 fbp in+ ref in- out+ vs- vs+ en 5 6 fbn out- 0 ? r f2 0 ? r f1 50 ? r s3 50 ? r s1 50 ? r s2 open r g inn- inp 1k ? -5v +5v out+ out- en vref r ld typical performance curves figure 1. frequency response figure 2. frequency response for various gain figure 3. frequency response vs c ld figure 4. frequency response vs r ld 4 3 1 0 -2 -3 -5 -6 10m 100m 1g magnitude (db) frequency (hz) -4 -1 2 1m a v = 1, r ld = 1k ? , c ld = 2.7pf v op-p = 200mv v op-p = 1v 4 3 1 0 -2 -3 -5 -6 10m 100m 1g frequency (hz) -4 -1 2 1m normalized magnitude (db) a v = 2 a v = 5 a v = 10 a v = 1 r ld = 1k ? , c ld = 2.7pf 10 8 4 2 -2 -4 -8 -10 10m 100m 1g frequency (hz) -6 0 6 1m magnitude (db) a v = 1, r ld = 1k ? c ld = 50pf c ld = 34pf c ld = 23pf c ld = 2.7pf c ld = 9pf 4 3 1 0 -2 -3 -5 -6 10m 100m 1g magnitude (db) frequency (hz) -4 -1 2 1m r ld = 500 ? r ld = 200 ? r ld = 1k ? a v = 1, c ld = 2.7pf EL5177
5 figure 5. frequency response fi gure 6. frequency response vs r ld figure 7. frequency response - v ref figure 8. psrr vs frequency figure 9. cmrr vs frequency figure 10. voltage and current noise vs frequency typical performance curves (continued) 10 9 7 6 4 3 1 0 10m 100m 400m frequency (hz) 2 5 8 1m magnitude (db) r f = 200 ? r f = 500 ? r f = 1k ? a v = 2, r ld = 1k ? , c ld = 2.7pf 10 9 7 6 4 3 1 0 10m 100m 400m frequency (hz) 2 5 8 1m magnitude (db) a v = 2, c ld = 2.7pf, r f = 750 ? r ld = 200 ? r ld = 1k ? r ld = 500 ? 5 4 2 1 -1 -2 -4 -5 1m 10m magnitude (db) frequency (hz) -3 0 3 100k 100m 0 -10 -30 -50 -60 -80 -90 100k 100m psrr (db) frequency (hz) -70 -40 -20 10k 1m 10m psrr+ psrr- 100 60 20 -20 cmrr (db) frequency (hz) 80 40 0 100k 100m 1k 1m 1g 10k 10m 1k 100 10 1 voltage noise (nv/ hz), 100 100k 10m frequency (hz) 10 10k 1m 1k e n i n current noise (pa/ hz) EL5177
6 figure 11. output impedance vs frequency figure 12. harmonic distortion vs differential output voltage figure 13. harmonic distortion vs differential output voltage figure 14. harmonic distortion vs r ld figure 15. harmonic distortion vs r ld figure 16. harmonic distortion vs frequency typical performance curves (continued) 100 10 1 0.1 100k 1m 100m impedence ( ? ) frequency (hz) 10k 10m distortion (db) v op-p, dm (v) -100 -90 -80 -70 -60 -50 -40 1 1.5 2 2.5 3 3.5 4 4.5 5 hd2 (f = 5mhz) hd3 (f = 5mhz) hd3 (f = 20mhz) hd2 (f = 20mhz) v s = 5v , a v = 1, r ld = 1k ? -40 -50 -60 -70 -80 -90 distortion (db) 27 169 410 -100 35 8 h d 2 ( f = 2 0 m h z ) hd3 (f = 20mhz) h d 3 ( f = 5 m h z ) v op-p, dm (v) v s = 5v , a v = 2, r ld = 1k ? hd2 (f = 5mhz) -50 -55 -60 -70 -90 distortion (db) -80 200 600 r ld ( ? ) 100 800 400 1000 -100 300 500 700 h d 3 ( f = 2 0 m h z ) h d 2 ( f = 2 0 m h z ) h d 2 ( f = 5 m h z ) -65 -75 -85 -95 900 v s = 5v , a v = 1, v op-p, dm = 1v h d 3 ( f = 5 m h z ) -50 -55 -60 -70 -90 distortion (db) -80 300 700 r ld ( ? ) 200 800 500 1000 -100 400 600 hd3 (f = 20mhz) h d 2 ( f = 2 0 m h z ) hd2 (f = 5mhz) -65 -75 -85 -95 900 v s = 5v , a v = 2, v op-p, dm = 2v h d 3 ( f = 5 m h z ) distortion (db) frequency (mhz) -100 -90 -80 -70 -60 -50 -40 0102030405060 hd3 (a v = 2) h d 2 ( a v = 2 ) h d 3 ( a v = 1 ) h d 2 ( a v = 1 ) v s = 5v , r ld = 1k ? , v op-p, dm = 1v for a v = 1, v op-p, dm = 2v for a v = 2 EL5177
7 figure 17. small signal transient response f igure 18. large signal transient response figure 19. enabled response figure 20. disabled response figure 21. package power dissipation vs ambient temperature figure 22. package power dissipation vs ambient temperature typical performance curves (continued) 10ns/div 50mv/div 10ns/div 0.5v/div ch1 ch2 400ns/div m = 400ns, ch1 = 500mv/div, ch2 = 5v/div ch1 ch2 400ns/div m = 400ns, ch1 = 200mv/div, ch2 = 5v/div jedec jesd51-3 low effective thermal conductivity test board 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 486mw ja =206c/w msop8/10 0.5 jedec jesd51-7 high effective thermal conductivity test board 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) 85 870mw ja =115c/w msop8/10 0.8 0.5 0.7 EL5177
8 simplified schematic description of operat ion and application information product description the EL5177 is a wide bandwidth, low power and single/differential ended to differential output amplifier. it can be used as single/differential ended to differential converter. the EL5177 is internally compensated for closed loop gain of +1 of greater. connected in gain of 1 and driving a 1k ? differential load, the EL5177 has a -3db bandwidth of 550mhz. driving a 200 ? differential load at gain of 2, the bandwidth is about 130mhz. the EL5177 is available with a power down feature to reduce the power while the amplifier is disabled. input, output, and supply voltage range the EL5177 has been designed to operate with a single supply voltage of 5v to 10v or a split supplies with its total voltage from 5v to 10v. the amplifiers have an input common mode voltage range from -4.3v to 3.4v for 5v supply. the differential mode input range (dmir) between the two inputs is from -2.3v to +2.3v. the input voltage range at the ref pin is from -3.3v to 3.7v. if the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. the output of the EL5177 can swing from -3.8v to +3.8v at 1k ? differential load at 5v supply. as the load resistance becomes lower, the output swing is reduced. differential and common mode gain settings the voltage applied at ref pin can set the output common mode voltage and the gain is one. the differential gain is set by the r f and r g network. the gain setting for EL5177 is: where: ?r f1 = r f2 = r f figure 23. choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resistor is required. just short the out+ pin to fbp pin and out- pin to fbn pin. for gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier's phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be ref r 10 r 9 r cd r cd out+ out- c c r 6 r 5 c c r 4 r 3 r 7 r 8 r 2 r 1 v b1 fbn fbp in- in+ v b2 v s + v s - v odm v in ( +v in - ) 1 r f1 r f2 + r g ---------------------------- + ?? ?? ?? ? = v odm v in ( +v in - ) 1 2r f r g ----------- + ?? ?? ?? ? = v ocm v ref = v o + fbp r g r f2 i n + i n - ref fbn v in + v in - v ref r f1 v o - EL5177
9 exceeded for optimum performance. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the expense of reducing the bandwidth. the bandwidth of the EL5177 depends on the load and the feedback network. r f and r g appear in parallel with the load for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum bandwidth performance. for gain of +1, r f = 0 is optimum. for the gains other than +1, opt imum response is obtained with r f between 500 ? to 1k ? . the EL5177 has a gain bandwidth product of 200mhz for r ld = 1k ? . for gains 5, its bandwidth can be predicted by the following equation: driving capacitive loads and cables the EL5177 can drive 23pf differential capacitor in parallel with 1k ? differential load with less than 5db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (usually between 5 ? to 50 ? ) can be placed in series with each output to eliminate most peaking. however, this will reduce the gain slightly. if the gain setting is greater than 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-termination series resistor at the amplifier's output will isolate t he amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the EL5177 can be disabled and placed its outputs in a high impedance state. the turn off time is about 1.2s and the turn on time is about 130ns. when disabled, the amplifier's supply current is reduced to 1.7a for i s + and 120a for i s - typically, thereby effectively eliminating the power consumption. the amplifier's power down can be controlled by standard cmos signal levels at the en pin. the applied logic signal is relative to v s + pin. letting the en pin float or applying a signal that is less than 1.5v below v s + will enable the amplifier. the amplifier will be disabled when the signal at en pin is above v s + - 0.5v. output drive capability the EL5177 has internal short circuit protection. its typical short circuit current is 40ma. if the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceeds 40ma. this limit is set by the design of the internal metal interconnect. power dissipation with the high output drive capability of the EL5177. it is possible to exceed the 135c absolute maximum junction temperature under certain load current conditions. therefore, it is im portant to calculate the maximum junction temperature for the applicatio n to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: where: ?v s = total supply voltage ?i smax = maximum quiescent supply current per channel ? ? v o = maximum differential output voltage of the application ?r ld = differential load resistance ?i load = load current by setting the two pd max equations equal to each other, we can solve the output current and r ld to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as sort as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0. 1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, the v s - pin becomes the negative supply rail. gain bw 200mhz = pd max t jmax t amax ? ja -------------------------------------------- - = pd v s i smax v s ? v o r ld ----------- - + = EL5177
10 for good ac performance, parasitic capacitance should be kept to minimum. use of wire wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performance. minimizing parasitic capacitance at the amplifier's inverting in put pin is very important. the feedback resistor should be placed very close to the inverting input pin. strip line design techniques are recommended for the signal traces. typical applications figure 24. twisted pair cable receiver as the signal is transmitted through a cable, the high frequency signal will be attenuated. one way to compensate this loss is to boost the high frequency gain at the receiver side. figure 25. transmit equalizer fbp r g r f in+ in- ref fbn r f r fr r gr in+ in- ref el5175 EL5177 v o 50 50 r t twisted pair z o = 100 ? v o + fbp r f i n + i n - ref fbn r f v o - r g r t r gc c l 75 f l f h frequency gain (db) f h 1 2 r gc c c ---------------------------- - ? f l 1 2 r g c c ------------------------ - ? dc gain 1 2r f r g ----------- + = hf () gain 1 2r f r g r gc || -------------------------- + = EL5177
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com msop package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp EL5177

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