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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 ad9879 mixed-signal front end set-top box, cable modem features low cost 3.3 v mxfe for docsis euro docsis dvb davic compliant set-top box and cable modem applications 232 mhz quadrature digital upconverter 12-bit direct if dac (txdac+ ) up to 65 mhz carrier frequency dds programmable sampling clock rates 16 upsampling interpolation lpf single-tone frequency synthesis analog tx output level adjust direct cable amp interface 12-bit, 33 msps direct if adc with optional video clamping input 10-bit, 33 msps direct if adc dual 7-bit, 16.5 msps sampling i/q adc 12-bit sigma-delta auxiliary dac applications cable modem and satellite systems set-top boxes power line modem pc multimedia digital communications data and video modems qam, ofdm, fsk modulation functional block diagram tx data i q 12 dac caport mclk rxi rx10 rx12 video sport rxiq[3:0] rxif[11:0] tx 16 sinc ? dds pll xm/n mux mux control registers adc adc adc mux mux clamp tx - - _out ad9879 4 8 10 12 rxq 2 2 general description the ad9879 is a single-supply cable modem/set-top box mixed signal front end. the device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit dac. the receive path contains a 12-bit adc, a 10-bit adc, and dual 7-bit adcs. all internally required clocks and an output system clock are generated by the pll from a single crystal or clock input. the transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 8.3 mhz. carrier frequencies up to 65 mhz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (dds). the transmit dac resolution is 12 bits and can run at sampling rates as high as 232 m sps. analog output scaling from 0 db to 7.5 db in 0.5 db steps is available to preserve snr when reduced output levels are required. mxfe and txdac are trademarks of analog devices, inc. the 12-bit and 10-bit if adcs can convert direct if inputs up to 70 mhz and run at sample rates up to 33 msps. a video input with an adjustable signal clamping level, along with the 10-bit adc, allow the ad9879 to process an ntsc and a qam channel simultaneously. the programmable sigma-delta dac can be used to control external components, such as variable gain amplifiers (vgas) or voltage controlled tuners. the ca port provides an interface to the ad8321/ad8323 or ad8322/ad8327 programmable gain amplifier (pga) cable drivers enabling host processor control via the mxfe sport. the ad9879 is available in a 100-lead mqfp package. it offers enhanced receive path undersampling performance and lower cost when compared with the pin com pat- ible ad9873. the ad9879 is specified over the commercial (?0 c to +85 c) temperature range.
rev. 0 e2e ad9879especifications test parameter temp level min typ max unit oscin and xtal characteristics frequency range full ii 3 29 mhz duty cycle full ii 35 50 65 % input impedance 25?c iii 100 || 3m || pf mclk cycle to cycle jitter 25?c iii 6 ps rms tx dac characteristics resolution n/a n/a 12 bits maximum sample rate full ii 232 mhz full-scale output current full ii 4 10 20 ma gain error (using internal reference) full ii e2.0 e1.0 +2.0 %fs offset error 25?c iii 1.0 %fs reference voltage (refio level) 25?c iii 1.23 v differential nonlinearity (dnl) 25?c iii 2.5 lsb integral nonlinearity (inl) 25?c iii 8 lsb output capacitance 25?c iii 5 pf phase noise @ 1 khz offset, 42 mhz crystal and oscin multiplier enabled at 16 25?c iii e110 dbc/hz output voltage compliance range full ii e0.5 +1.5 v wideband sfdr 5 mhz analog out, i out = 10 ma full i 60.8 66.9 dbc 65 mhz analog out, i out = 10 ma full i 44.0 46.2 dbc narrow-band sfdr ( 1 mhz window): 5 mhz analog out, i out = 10 ma full i 65.4 72.3 dbc tx modulator characteristics i/q offset full ii 50 55 db pass-band amplitude ripple (f < f iqclk /8) full ii 0.1 db pass-band amplitude ripple (f < f iqclk /4) full ii 0.5 db stop-band response (f > f iqclk 3/4) full ii e63 db tx gain control gain step size 25?c iii 0.5 db gain step error 25?c iii <0.05 db settling time to 1% (full-scale step) 25?c iii 1.8 s iq adc characteristics resolution * n/a n/a 6 bits maximum conversion rate full iii 14.5 mhz pipeline delay n/a n/a 3.5 adc cycles offset matching between i and q adcs 4.0 lsbs gain matching between i and q adcs 2.0 lsbs analog input input voltage range * full iii 1 vppd input capacitance 25?c iii 2.0 pf differential input resistance 25?c iii 4 k ac performance (a in = 0.5 dbfs, f in = 5 mhz) effective number of bits (enob) full i 5.25 5.8 bits signal-to-noise ratio (snr) full i 36.5 db total harmonic distortion (thd) full i e50 db spurious-free dynamic range (sfdr) full i 51 db (v as = 3.3 v 5%, v ds = 3.3 v 10%, f oscin = 27 mhz, f sysclk = 216 mhz, f mclk = 54 mhz (m = 8), adc clock from oscin, r set = 4.02 k , 75 dac load) * iq adc in default mode. adc clock select register 8, bit 3 set to 0.
rev. 0 ad9879 e3e test parameter temp level min typ max unit 10-bit adc characteristics resolution n/a n/a 10 bits maximum conversion rate full ii 29 mhz pipeline delay n/a n/a 4.5 adc cycles analog input input voltage range full iii 2.0 vppd input capacitance 25?c iii 2 pf differential input resistance 25?c ii 4 k reference voltage error (reft10erefb10) e1 v full i 4 200 mv ac performance (a in = e0.5 dbfs, f in = 5 mhz) adc sample clock source = oscin signal-to-noise and distortion (sinad) full i 58.3 59.9 db effective number of bits (enob) full i 9.4 9.65 bits signal-to-noise ratio (snr) full i 58.6 60 db total harmonic distortion (thd) full i e73 e62 db spurious-free dynamic range (sfdr) full i 65.7 76 db ac performance (a in = e0.5 dbfs, f in = 50 mhz) adc sample clock source = oscin signal-to-noise and distortion (sinad) full ii 57.7 59.0 db effective number of bits (enob) full ii 9.29 9.51 bits signal-to-noise ratio (snr) full ii 57.8 59.1 db total harmonic distortion (thd) full ii +57 e75 db spurious-free dynamic range (sfdr) full ii 64 78 db 12-bit adc characteristics resolution n/a n/a 12 bits maximum conversion rate full ii 29 mhz pipeline delay n/a n/a 5.5 adc cycles analog input input voltage range full iii 2 vppd input capacitance 25?c iii 2 pf differential input resistance 25?c iii 4 k reference voltage error (reft12erefb12) e1 v full i 16 200 mv ac performance (a in = e0.5 dbfs, f in = 5 mhz) adc sample clock source = oscin signal-to-noise and distortion (sinad) full i 60.0 65.2 db effective number of bits (enob) full i 9.67 10.53 bits signal-to-noise ratio (snr) full i 60.3 65.6 db total harmonic distortion (thd) full i e76.6 e58.7 db spurious-free dynamic range (sfdr) full i 64.7 79 db ac performance (a in = e0.5 dbfs, f in = 50 mhz) adc sample clock source = oscin signal-to-noise and distortion (sinad) full ii 59.5 62.7 db effective number of bits (enob) full ii 9.59 10.1 bits signal-to-noise ratio (snr) full ii 59.7 63.0 db total harmonic distortion (thd) full ii e75.5 e60.5 db spurious-free dynamic range (sfdr) full ii 63.8 79 db
rev. 0 e4e ad9879 test parameter temp level min typ max unit channel-to-channel isolation tx dac-to-adc isolation (a out = 5 mhz) isolation between tx and iq adcs 25?c iii >60 db isolation between tx and 10-bit adc 25?c iii >80 db isolation between tx and 12-bit adc 25?c iii >80 db adc-to-adc (a in = e0.5 dbfs, f = 5 mhz) isolation between if10 and if12 adcs 25?c iii >85 db isolation between q and i inputs 25?c iii >50 db timing characteristics (10 pf load) minimum reset pulsewidth low (t rl ) n/a n/a 5 t mclk cycles digital output rise/fall time full ii 2.8 4 ns tx/rx interface mclk frequency (f mclk ) full ii 66 mhz txsync/txiq setup time (t su ) full ii 3 ns txsync/txiq hold time (t hd ) full ii 3 ns mclk rising edge to rxsync/rxiq/if valid delay (t md ) full ii 0 1.0 ns oscout rising or falling edge to rxsync/rxiq/if valid delay (t od ) full ii t osc /4 e 2.0 t osc /4 + 3.0 ns oscout edge to mclk falling edge (t ee ) full ii e1.0 +1.0 ns serial control bus maximum sclk frequency (f sclk ) full ii 15 mhz minimum clock pulsewidth high (t pwh ) full ii 30 ns minimum clock pulsewidth low (t pwl ) full ii 30 ns maximum clock rise/fall time full ii 1 ms minimum data/chip-select setup time (t ds ) full ii 25 ns minimum data hold time (t dh ) full ii 0 ns maximum data valid time (t dv ) full ii 30 ns cmos logic inputs logic 1 voltage 25?c ii v drvdd e 0.7 v logic 0 voltage 25?c ii 0.4 v logic 1 current 25?c ii 12 a logic 0 current 25?c ii 12 a input capacitance 25?c ii 3 pf cmos logic outputs (1 ma load) logic 1 voltage 25?c ii v drvdd e 0.6 v logic 0 voltage 25?c ii 0.4 v power supply supply current, i s (full operation) 25 cii 163 178 ma analog supply current, i as 25?c iii 95 ma digital supply current, i ds 25?c iii 68 ma supply current, i s standby ( pwrdn pa 2c 2 a pdr2 2c a pdtpr2 2c a pdrpr2 2c a
rev. 0 ad9879 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9879 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * power supply (v avdd ,v dvdd ,v drvdd ) . . . . . . . . . . . . . . 3.9 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs . . . . . . . . . . . . . . . . . e0.3 v to v drvdd + 0.3 v analog inputs . . . . . . . . . . . . . . . . . . e0.3 v to v avdd + 0.3 v operating temperature . . . . . . . . . . . . . . . . . e40?c to +85?c maximum junction temperature . . . . . . . . . . . . . . . . . 150?c storage temperature . . . . . . . . . . . . . . . . . . e65?c to +150?c lead temperature (soldering 10 sec) . . . . . . . . . . . . . . 300?c * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package model range description ad9879bs e40?c to +85?c 100-lead mqfp explanation of test levels i. devices are 100% production tested at +25?c and guaranteed by design and characterization testing for commercial operating temperature range (e40?c to +85?c). ii. parameter is guaranteed by design and/or characterization testing. iii. parameter is a typical value only. n/a test level definition is not applicable. thermal characteristics thermal resistance 100-lead mqfp ja = 40.5?c/w
rev. 0 e6e ad9879 pin configuration 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 top view 100-lead mqfp video in agnd if12+ if12e agnd avdd reft12 refb12 avdd agnd if10+ if10e agnd avdd reft10 refb10 avdd agnd q+ qe txiq(1) txiq(0) dvdd dgnd dnc profile reset ddd dnd dnd sc cs sd sd dndt dddt pwrdn re sad andt dnc dnc dnc dnc and add drdd rec drnd dnd _t a ddd ca_en ca_data ca_c dddsc scn ta dndsc andp pt addp dddp dndp addt t t dnc drnd drdd r r r r rsnc drnd drdd c ddd dnd tsnc t t t t ad
rev. 0 ad9879 ? pin function assignments pin no. mnemonic pin function 56 avddpll pll analog 3.3 v supply 57 pllfilt pll loop filter connection 58 agndpll pll analog ground 59 dgndosc oscillator digital ground 60 xtal crystal oscillator inv. output 61 oscin oscillator clock input 62 dvddosc oscillator digital 3.3 v supply 63 ca_clk serial clock to cable driver 64 ca_data serial data to cable driver 65 ca_en serial enable to cable drive 66 dvdd - sigma delta digital 3.3 v supply 67 flag1 digital output flag 1 68 - _out sigma-delta dac output 69 dgnd - sigma-delta digital ground 71 refclk oscillator clock output 73 avddiq 7-bit adcs analog 3.3 v supply 74 agndiq 7-bit adcs analog ground 78, 79 i? i+ differential input to i adc 81, 82 q? q+ differential input to q adc 83, 88, agnd 12-bit adc analog ground 91, 96, 99 84, 87, avdd 12-bit adc analog 3.3 v supply 92, 95 85 refb10 10-bit adc decoupling node 86 reft10 10-bit adc decoupling node 89, 90 if10? if10+ differential input to 10-bit adc 93 refb12 12-bit adc decoupling node 94 reft12 12-bit adc decoupling node 97, 98 if12? if12+ differential input to if adc 100 video in video clamp input, 12-bit adc pin no. mnemonic pin function 1, 35, dnc do not connect. pins are not 75?7, 80 bonded to die. 2, 21, 70 drgnd pin driver digital ground 3, 22, 72 drvdd pin driver digital 3.3 v supply 4?5 if[11:0] 12-bit adc digital output 16?9 rxiq[3:0] muxed i and q adcs output 20 rxsync sync output, if, i and q adcs 23 mclk master clock output 24, 33, 38 dvdd digital 3.3 v supply 25, 34, dgnd digital ground 39, 40 26 txsync sync input for transmit port 27?2 txiq[5:0] digital input for transmit port 36 profile profile selection inputs 37 reset chip reset input (active low) 41 sclk sport clock 42 cs sport chip select 43 sdio sport data i/o 44 sdo sport data output 45 dgndtx tx path digital ground 46 dvddtx tx path digital 3.3 v supply 47 pwrdn power-down transmit path 48 refio txdac decoupling (to agnd) 49 fsadj dac output adjust (external res.) 50 agndtx tx path analog ground 51, 52 tx? tx+ tx path complementary outputs 53 avddtx tx path analog 3.3 v supply 54 dgndpll pll digital ground 55 dvddpll pll digital 3.3 v supply
rev. 0 ? ad9879 definitions of specifications differential nonlinearity error (dnl, no m issing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. phase noise single-sideband phase noise power is specified relative to the car- rier (dbc/hz) at a given frequency offset (1 khz) from the carrier. phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measure- ments. it detects the relative power between the carrier and the offset (1 khz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10log(rbw). it also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. spurious-free dynamic range (sfdr) the difference, in db, between the rms amplitude of the dac output signal (or the adc input signal) and the peak spurious signal over the specified bandwidth (nyquist bandwidth unless otherwise noted). pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. offset error first transition should occur for an analog value 1/2 lsb above ?s. offset error is defined as the deviation of the actual transi- tion from that point. gain error the first code transition should occur at an analog value 1/2 lsb above full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. aperture delay the aperture delay is a measure of the sample-and-hold ampli- fier (sha) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion. aperture uncertainty (jitter) aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the adc. input reference noise the rms output noise is measured using histogram techniques. the adc output codes?standard deviation is calculated in lsb and converted to an equivalent voltage. this results in a noise figure that can directly be referred to the input of the mxfe. signal-to-noise and distortion (s/n+d, sinad) ratio sinad is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula: n = ( sinad ?1.76) db /6.02 it is possible to get a performance measurement expressed as n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. power supply rejection power supply rejection specifies the converter? maximum full- scale change when the supplies are varied from nominal to minimum and maximum specified voltages. channel-to-channel isolation (crosstalk) in an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. the channel- to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.
rev. 0 ad9879 ? table i. register map address default (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) type 00h sdio spi bytes reset oscin 0x08 read/write bidirectional lsb first multiplier m[4:0] 01h pll mclk/refclk ratio 0x00 read/write lock r[5:0] detect 02h power-down power-down power-down power-down power-down power-down power-down power-down 0x00 read/write pll dac tx digital tx if12 adc reference if10 adc reference iq adc if12 adc iq and if10 adc 03h sigma-delta output control word [3:0] flag 1 flag 0 0x00 read/write enable 04h flag 0 sigma-delta output control word [11:4] 0x00 read/write 05h 0 0 0 0 0 0 0 0 0x00 read/write 06h 0 0 0 0 0 0 0 0 0x00 read-only 07h video input clamp level for video input [6:0] 0x00 read/write enable 08h adcs clocked 0 rx port power-down enable 7-bits 0 send 12-bit send 10-bit 0x80 read/write direct from fast edge rate rxsync and iq adc adc data only adc data only oscin iq adc clocks 09h 0 0 0 0 0 0 0 0 0x00 read/write 0ah 0 0 0 0 0 0 0 0 0x00 read/write 0bh 0 0 0 0 0 0 0 0 0x00 read/write 0ch 0 0 0 0 version [3:0] 0x05 read/write 0d h0 000 tx frequency tuning word tx frequency tuning word 0x00 read/write profile 1 lsbs [1:0] profile 0 lsbs [1:0] 0eh 0 0 0 0 dac fine gain control [3:0] 0x00 read/write 0fh 0 0 tx path 0 tx path tx path tx path tx path 0x00 read/write select profile 1 ad8322/ bypass spectral transmit ad8327 gain sinc -1 inversion single tone control mode filter 10h tx path frequency tuning word profile 0 [9:2] 0x00 read/write 11h tx path frequency tuning word profile 0 [17:10] 0x00 read/write 12h tx path frequency tuning word profile 0 [25:18] 0x00 read/write 13h cable driver amplifier coarse gain control profile 0 [7:4] fine gain control profile 0 [3:0] 0x00 read/write 14h tx path frequency tuning word profile 1 [9:2] 0x00 read/write 15h tx path frequency tuning word profile 1 [17:10] 0x00 read/write 16h tx path frequency tuning word profile 1 [25:18] 0x00 read/write 17h cable driver amplifier coarse gain control profile 1 [7:4] fine gain control profile 1 [3:0] 0x00 read/write register bits denoted with ??must be programmed with a ??every time that register is written.
rev. 0 ?0 ad9879 register bit definitions register 00 ?initialization bits 0 to 4: oscin multiplier this register field is used to program the on-chip multiplier (pll) that generates the chip? high frequency system clock f sysclk . the value of m will depend on the adc clocking mode selected as shown in the table below. table ii. adc clock select m 1, f oscin 8 0, f mclk (pll derived) 16 when using the ad9879 in systems where the tx path and rx path do not operate simultaneously, the value of m can be pro- grammed from 1 to 31. the maximum f sysclk rate of 236 mhz must be observed, whatever value is chosen for m. when m is set to 1, the internal pll is disabled and all internal clocks are derived directly from oscin. bit 5: reset writing a 1 to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back 0. the bits in register 0 are not affected by this software reset. how- ever, a low level at the reset pin would force all registers, including all bits in register 0, to their default state. bit 6: spi bytes lsb first active high indicates spi serial port access of instruction byte and data registers is least significant bit (lsb) first. default low indicates most significant bit (msb) first format. bit 7: sdio bidirectional active high configures the serial port as a three signal port with the sdio pin used as a bidirectional input/output pin. default low indicates the serial port uses four signals with sdio config- ured as an input and sdo configured as an output. register 01 ?clock configuration bits 0 to 5: mclk/refclk ratio this bit field defines, r, the ratio between the auxiliary clock output, refclk and mclk. r can be any integer number between 2 and 63. at default zero (r = 0), refclk provides a buffered version of the oscin clock signal. bit 7: pll lock detect when this bit is set low, the refclk pin functions in its default mode, and provides an output clock with frequency f mclk /r as described above. if this bit is set to 1, the refclk pin is configured to indicate whether the pll is locked to f oscin . in this mode, the refclk pin should be low-pass filtered with an rc filter of 1.0 k w and 0.1 m f. a high output on refclk indicates that the pll has achieved lock with f oscin . register 02 ?power-down sections of the chip that are not used can be powered down when the corresponding bits are set high. this register has a default value of 0x00; all sections active. bit 0: power-down iq adc active high powers down the iq adc. bit 1: power-down iq and if10 adc reference active high powers down the iq and if10 adc reference. bit 2: power-down if10 adc active high powers down the if10 adc. bit 3: power-down if12 adc reference active high powers down the 12-bit adc reference. bit 4: power-down if12 adc active high powers down the if12 adc. bit 5: power-down digital tx active high powers down the digital transmit section of the chip, similar to the function of the pwrdn pin. bit 6: power-down dac tx active high powers down the dac. bit 7: power-down pll active high powers down the oscin multiplier. registers 03 and 04 ?sigma-delta and flag control the sigma-delta control word is 12 bits wide and split in msb bits [11:4] and lsb bits [3:0]. changes to the sigma-delta control words take effect immediately for every msb or lsb register write. sigma-delta output control words have a default value of ?.?the control words are in straight binary format with 0x000 corresponding to the bottom of the scale and 0xfff corre spond- ing to the top of the scale. see figure 6 for details. if the flag 0 enable (register 3, bit 0) is set high, the - _out pin will maintain a fixed logic level determined directly by the msb of the sigma- delta control word. the flag1 pin assumes the logic level programmed into the flag1 bit (register 3, bit 1). register 07 ?ideo input configuration bits 0-6: clamp level control value the 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. the actual adc output will have a clamp level offset equal to 16 times the clamp level control value as shown: clamp level offset clamp level control value = () 16 the default value for the clamp level control value is 0x20. this results in an adc output clamp level offset of 512 lsbs. the valid programming range for the clamp level control value is from 0x16 to 0x127. register 08 ?adc clock configuration bit 0: send 10-bit adc data only when this bit is set high, the device enters a nonmultiplexed mode and only the data from the 10-bit adc will be sent to the if [11:0] digital output port. bit 1: send 12-bit adc data only when this bit is set high, the device enters a nonmultiplexed mode and only data from the 12-bit adc will be sent to the if [11:0] digital output port. bit 3: enable 7-bits, iq adc when this bit is active the iq adc is put into 7-bit mode. in this mode, the full-scale input range is 2 vppd. when this bit is set inactive, the iq adc is put into 6-bit mode and the full- scale input voltage range is 1 vppd. bit 4: power-down rxsync and iq adc clocks setting this bit to 1 powers down the iq adc? sampling clock and stops the rxsync output pin. it can be used for additional power saving on top of the power-down selections in register 2.
rev. 0 ad9879 ?1 bit 5: rx port fast edge rate setting this bit to 1 increases the output drive strength of all digital output pins, except mclk, refclk, - _out, and flag1. these pins always have high output drive capability. bit 7: adc clocked direct from oscin when set high, the input clock at oscin is used directly as the adc sampling clock. when set low, the internally generated master clock, mclk, is divided by two and used as the adc sampling clock. best adc performance is achieved when the adcs are sampled directly from f oscin using an external crystal or low jitter crystal oscillator. register c?ie revision bits 0 to 3: version the die version of the chip can be read from this register. register d?x frequency tuning words lsbs this register accommodates two least significant bits for both of the frequency tuning words. see description of carrier frequency tuning. register e?ac gain control bits 0 to 3: dac fine gain control this bit field sets the dac gain if the tx path ad8321/ad 8323 gain control select bit (register f, bit 3) is set to 0. the dac gain can be set from 0.0 db to 7.5 db in increments of 0.5 db. table iii details the programming. table iii. bits [3:0] dac gain 0000 0.0 db (default) 0001 0.5 db 0010 1.0 db 0011 1.5 db .... .... 1110 7.0 db 1111 7.5 db register f ?tx path configuration bit 0: tx path transmit single tone active high configures the ad9879 for single-tone applications (e.g., fsk). the ad9879 will supply a single frequency output as determined by the frequency tuning word selected by the active profile. in this mode, the txiq input data pins are ignored but should be tied to a valid logic voltage level. default value is 0 (inactive). bit 1: tx path spectral inversion when set to 1, inverted modulation is performed: modular_out i cos t q sin t = () + () [] ww default is logic zero, noninverted modulation: modular_out i cos t q sin t = () + () [] ww bit 2: tx path bypass sinc ? filter setting this bit high bypasses the digital inverse sinc filter of the tx path. bit 3: tx path ad8322/ad8327 gain control mode this bit changes the manner in which transmit gain control is performed. typically either ad8321/ad8323 (default 0) or ad8222/ad8327 (default 1) variable gain cable drivers are programmed over the chip? 3-wire ca interface. the tx gain control select changes the interpretation of the bits in registers 13 and 17. see cable driver gain control. bit 5: tx path select profile 1 the ad9879 quadrature digital upconverter is capable of stor- ing two preconfigured modulation modes called profiles. each profile defines a transmit frequency tuning word and cable driver amplifier gain (/dac gain) setting. the profile select bit or profile pin programs the current register profile to be used. the profile select bit should always be ??if the profile pin is to be used to switch between profiles. using the profile select bit as a means of switching between different profiles requires the profile pin to be tied low. registers 10?7: carrier frequency tuning tx path frequency tuning words the frequency tuning word ( ftw ) determines the dds-generated carrier frequency ( f c ) and is formed via a concatenation of reg is ter addresses. the 26-bit ftw is spread over four register addresses. bit 25 is the msb and bit 0 is the lsb. the carrier frequency equation is given as: f ftw f c sysclk = [] /2 26 where fmf and ftw sysclk oscin = < 0 2000000 changes to ftw bytes take effect immediately. cable driver gain control the ad9879 has a 3-pin interface to the ad832x family of programmable gain cable driver amplifiers. this allows direct control of the cable driver? gain through the ad9879. in its default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (ca) interface. if bit 3 of register f is set high, bits [7:4] determine the 8-bit word sent over the ca interface according to table iv. table iv. bits [7:4] ca interface transmit word 0000 0000 0000 (default) 0001 0000 0001 ... ... 0111 0100 0000 1000 1000 0000 in this mode, the lower bits determine the fine gain setting of the dac output. table v. bits [3:0] dac fine gain 0000 0.0 db (default) 0001 0.5 db ... ... 1110 7.0 db 1111 7.5 db new data is automatically sent over the 3-wire ca interface (and dac gain adjust) whenever the value of the active gain control register changes or a new profile is selected. the default value is 0x00 (lowest gain).
rev. 0 ?2 ad9879 the formula for the combined output level calculation of the ad9879 fine gain and ad8327 or ad8322 coarse gain is: vv fine coarse 8327 9877 0 26 19 =+ () + () - () vv fine coarse 8322 9877 0 26 14 =+ () + () - () with: fine = decimal value of bits [3:0] coarse = decimal value of bits [7:8] v 9877 (0) : level at ad9879 output in dbmv for fine = 0. v 8327 : level at output of ad8327 in dbmv. v 8322 : level at output of ad8322 in dbmv. device overview to gain a general understanding of the ad9879, it is helpful to refer to figure 1, which displays a block diagram of the device architecture. the device consists of a transmit path, receive path, and auxiliary functions, such as a dpll, a sigma-delta dac, a serial control port, and a cable amplifier interface. transmit path the transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a txiq txsync mclk refclk ca_port profile sport rxiq[3:0] rxsync if[11:0] fsadj xtal oscin - _out flag1 i input q input if10 input if12 input video input 6 3 12 12 10 7 12 ad9879 data assembler quadrature modulator fir lpf cic lpf cos sin (f iqclk ) (f sysclk ) (f oscin ) (f mclk ) dac gain control pll oscin m dds mux mux ca interface profile select serial interface 12 4 4 sinc ?1 mux dac iq if clamp level adc adc adc adc mux dac 2 8 4 2 12 12 (f oscin ) (f oscin ) 7 r 4 4 12 i q rxport tx - input reg ? + ? 2 4 4 4 12 ? sinc ?1 bypass - figure 1. block diagram 12-bit current output dac. the maximum output current of the dac is set by an external resistor. the tx output pga provides additional transmit signal level control. the transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 5.8 mhz. carrier frequencies up to 65 mhz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (dds). the transmit dac resolution is 12 bits and can run at sampling rates as high as 232 msps. analog output scaling from 0 db to 7.5 db in 0.5 db steps is available to preserve snr when reduced output levels are required. data assembler the ad9879 data path operates on two 12-bit words, the i and q components, that form a complex symbol. the data assembler builds the 24-bit complex symbols from four consecutive 6-bit nibbles read over the txiq[5:0] bus. the nibbles are strobed synchronous to the master clock, mclk, into the data assemb ler. a high level on txsync signals the start of a transmit symbol. the first two nibbles of the symbol form the i component, the second two nibbles form the q component. symbol compo nents are assumed to be in twos complement format. the tim ing of the interface is fully described in the transmit timing section of this data sheet.
rev. 0 ad9879 ?3 interpolation filter once through the data assembler, the iq data streams are fed through a 4 fir low-pass filter and a 4 cascaded integrator- comb (cic) low-pass filter. the combination of these two filters results in the sample rate increasing by a factor of 16. in addi- tion to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images between the original sampling frequency and the new (16 higher) sampling frequency. digital upconverter the digital quadrature modulator stage following the cic filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream up to the desired carrier frequency. the carrier frequency is controlled numerically by a direct digital synthesizer (dds). the dds uses the internal system clock (f sysclk ) to generate the desired carrier frequency with a high degree of precision. the carrier is applied to the i and q multi- pliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is the modulated carrier. the modulated carrier becomes the 12-bit sample sent to the dac. the receive path contains a 12-bit adc, a 10-bit adc, and a dual 7-bit adc. all internally required clocks and an output system clock are generated by the pll from a single crystal or clock input. the 12-bit and 10-bit if adcs can convert direct if inputs up to 70 mhz and run at sample rates up to 33 msps. a video input with an adjustable signal clamping level along with the 10-bit adc allow the ad9879 to process an ntsc and a qam channel simultaneously. the programmable sigma-delta dac can be used to control external components, such as variable gain amplifiers (vgas) or voltage controlled tuners. the caport provides an interface to the ad8321/ad8323 or ad8322/ad8327 programmable gain amplifier (pga) cable drivers enabling host processor control via the mxfe sport. oscin clock multiplier the ad9879 can accept either an input clock into the oscin pin or a fundamental mode xtal across the oscin pin and xtal pins as the devices main clock source. the internal pll then generates the f sysclk signal from which all other internal signals are derived. the dac uses f sysclk as its sampling clock. for dds applica tions, the carrier is typically limited to about 30% of f sysclk . for a 65 mhz carrier, the system clock required is above 216 mhz. the oscin multiplier function maintains clock integrity as evidenced by the ad9879? systems excellent phase noise char- acteristics and low clock-related spur in the output spectrum. external loop filter components consisting of a series resistor (1.3 k w ) and capacitor (0.01 m f) provide the compensation zero for the oscin multiplier pll loop. the overall loop perfor- mance has been optimized for these component values. dpll-a clock distribution figure 1 shows the clock signals used in the transmit path. the dac sampling clock, f dac , is generated by dpll-a. f dac has a frequency equal to the l f oscin , where f oscin is the internal signal generated either by the crystal oscillator when a crystal is connected between the oscin and xtal pins, or by the clock that is fed into the oscin pin, and l is the multiplier pro grammed through the serial port. l can have the values of 1, 2, 3, or 8. the transmit path expects a new half word of data at the rate of f clk-a . when the tx multiplexer is enabled, the frequency of tx port is: ffklfk clk a dac oscin - = = 22 where k is the interpolation factor. the interpolation factor can be programmed to be 1, 2, or 4. when the tx multiplexer is disabled, the frequency of the tx port is: ffklfk clk a dac oscin - == receive section the ad9879 includes two high speed, high performance adcs. the 10-bit and 12-bit direct if adc? deliver excellent undersampling performance with input frequencies as high as 70 mhz. the sampling rate can be as high as 33 msps. the adc sampling frequency can be derived directly from the oscin signal or from the on-chip oscin multiplier. for highest dynamic performance, it is recommended to choose an oscin frequency that can directly be used as the adc sampling clock. digital iq adc outputs are multiplexed to one 4-bit bus, clocked by a frequency (f mclk ) of four times the sampling rate. the if adcs use a multiplexed 12-bit interface with an output word rate of f mclk . clock and oscillator circuitry the ad9879? internal oscillator generates all sampling clocks from a simple, low cost, parallel resonance, fundamental fre- quency quartz crystal. figure 2 shows how the quartz crystal is connected between oscin (pin 61) and xtal (pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. the internal oscillator circuitry can also be overdriven by a ttl-level clock applied to oscin with xtal left unconnected. ffm oscin mclk = an internal phase-locked loop (pll) generates the dac sampling frequency, f sysclk , by multiplying oscin frequency m times. the mclk signal (pin 23), f mclk , is derived by dividing f sysclk by 4. ffm sysclk oscin = ffm mclk oscin = 4 an external pll loop filter (pin 57) consisting of a series resistor and ceramic capacitor (figure 15, r1 = 1.3 k w , c12 = 0.01 f) is required for stability of the pll. also, a shield surrounding these components is recommended to minimize external noise coupling into the pll? voltage controlled oscillator input (guard trace connected to avddpll). figure 1 shows that adcs are either sampled directly by a low jitter clock at oscin or by a clock that is derived from the pll output. operating modes can be selected in register 8. sampling the adcs directly with the oscin clock requires mclk to be programmed to be twice the oscin frequency.
rev. 0 e14e ad9879 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 top view (pins down) video in agnd if12+ if12e agnd avdd reft12 refb12 avdd agnd if10+ if10e agnd avdd reft10 refb10 avdd agnd q+ qe txiq(1) txiq(0) dvdd dgnd dnc profile reset ddd dnd dnd sc cs sd sd dndt dddt pwrdn re sad andt dnc dnc dnc dnc and add drdd rec drnd dnd _t a ddd ca_en ca_data ca_c dddsc scn ta dndsc andp pter addp dddp dndp addt t t dnc drnd drdd s sr r r r rsnc drnd drdd c ddd dnd tsnc st t t t ad c cp c c c cp c c r set c c c ard trace r c cd prraaecctptrec tadp rectc r , determines its output frequency as shown in the equations: f refclk = f mclk / r , for r = 2e63 f refclk = f oscin , for r = 0 in its default setting (0x00 in register 1), the refclk pin provides a buffered output of f oscin .
rev. 0 ad9879 e15e reset and transmit power-down power-up sequence on initial power-up, the reset reset ad tp reset pwrdn p cadccsr sscdnr pwrdn p pwrdn pwrdn ppddt pwrdn p t reset t reset a sctt reset p t ps pwrdn t tsnc nss datass nss c n tstdp ar r s reset p wrdn c n pstdp tpd a pwrdn ccd pwrdn tcc c pwrdn t2 pwrdn pwrdn 2t dac spddtr2 pwrdn
rev. 0 e16e ad9879 sigma-delta outputs the ad9879 contains an on-chip sigma-delta output that pro- vides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the pro- grammed code, as shown in figure 5. 000h 001h 002h 800h fffh 8 t mclk 4096 8 t mclk 4096 8 t mclk 8 t mclk figure 5. sigma-delta output signals this bit stream can be low-pass filtered to generate a program- mable dc voltage of: v dc = ( sigma-delta code /4096)( v h ) + v l w here: v h = v drvdd e 0.6 v v l = 0.4 v in cable modem set-top box applications, the output can be used to control external variable gain amplifiers or rf tuners. a simple single-pole rc low-pass filter provides sufficient filtering (see figure 6). ad9879 mclk dac 12 control word 8 - r c dc(v l to v h ) typical: r = 50k c = 0.1 f f e3db = 1/(2 rc) = 318hz figure 6. sigma-delta rc filter in more demanding applications where additional gain, level shift, or drive capability is required, a first or second order active filter might be considered for each sigma-delta output (see figure 7). ad9879 sigma-delta r c v sd r v out r r1 v offset v out = (v sd + v offset ) (1 + r/r1)/2 typical: r = 50k c = 0.1 f f e3db = 1/(2 rc) = 318hz c op250 - figure 7. sigma-delta active filter with gain and offset serial interface for register control the ad9879 serial port is a flexible, synchronous serial commu- nications port that allows easy interface to many industry-standard microcontrollers and microprocessors. the interface allows read/write access to all registers that configure the ad9879. single or multiple byte transfers are supported. also, the inter face can be programmed to read words either msb first or lsb first. the ad9879?s serial interface port i/o can be configured to have one bidirectional i/o (sdio) pin or two unidirectional i/o (sdio/sdo) pins. general operation of the serial interface there are two phases to a communication cycle with the ad 9879. phase 1 is the instruction cycle, which is the writing of an in struction byte into the ad9879, coincident with the first eight sclk rising edges. the instruction byte provides the ad9879 serial port controller with information regarding the data trans- fer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data trans fer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communica tion cycle are used to write the instruction byte into the ad9879. the eight remaining sclk edges are for phase 2 of the communi- cation cycle. phase 2 is the actual data transfer between the ad9879 and the system controller. phase 2 of the communica tion cycle is a transfer of 1 to 4 data bytes as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the following information as shown below: msb lsb 17 16 15 14 13 12 11 10 r/w n1 n0 a4 a3 a2 a1 a0 the r/w bit of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates a read operation. logic zero indi- cates a write operation. the n1:n0 bits determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table vi. table vi. n1 n0 description 00 transfer 1 byte 01 transfer 2 bytes 10 transfer 3 bytes 11 transfer 4 bytes the bits a4:a0 determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9879.
rev. 0 ad9879 e17e serial interface port pin description sclk?serial clock. the serial clock pin is used to synchro nize data transfers from the ad9879 and to run the serial port state machine. the maximum sclk frequency is 15 mhz. input data to the ad9879 is sampled on the rising edge of sclk. output data changes on the falling edge of sclk. cs csa tsdsd cs c sdsddad t rtsd sdsdd ad sst tad sst sr ts wad ss s wad ss s w w nsp tad ra c tr aa ra a2a a areset scn a ssc c cs sc sd sd nstrctncce datatransercce rw n n a a a a a d d d d d d d d d d srts cs sc sd sd nstrctncce datatransercce a a a a a n n rw d d d d d d d d d d srts cs sc sd nstrctnt nstrctnt sc ds pw pw ds d tdrwad cs sc sd datatn d datatn sd tdrr transtpatt tt tadc tt tsnctsnc ssss da tt t c c t c tn c n
rev. 0 e18e ad9879 half-band filters (hbfs) hbf 1 and hbf 2 are both interpolating filters, each of which doubles the sampling rate. together, hbf 1 and hbf 2 have 26 taps and provide a factor-of-four increase in the sampling rate (4 f iqclk or 8 f nyq ). in relation to phase response, both hbfs are linear phase filters. as such, virtually no phase distortion is introduced within the pass band of the filters. this is an important feature as phase distortion is generally intolerable in a data transmission system. cascaded integrator-comb (cic) filter the cic filter is configured as a programmable interpolator and provides a sample rate increase by a factor of 4. the frequency response of the cic filter is given by: hf e e f f jf jf () sin( ) sin( ) (()) = ? ?
=
? 1 4 1 1 1 4 4 24 2 3 3 the frequency response in this form is such that f is scaled to the output sample rate of the cic filter. that is, f = 1 corresponds to the frequency of the output sample rate of the cic filter. h(f/r) will yield the frequency response with respect to the input sample of the cic filter. combined filter response the combined frequency response of hbf 1, hbf 2, and cic puts a limit on the input signal bandwidth that can be propagated through the ad9879. the usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the ad9879. a look at the pass-band detail of the combined filter response (figure 12 and figure 13) indicates that in order to maintain an amplitude error of no more than 1 db, we are re stricted to t hd t su mclk txsync txiq txi[11:6] txi[11:6] txi[5:0] txq[11:6] txq[5:0] txi[5:0] txq[11:6] txq[5:0] txi[11:6] txi[5:0] figure 11. timing diagram for register read frequency relative to i/q nyquist bw 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 magnitude e db e1 e2 e3 e4 e5 e6 figure 12. cascaded filter pass-band detail (n = 4) frequency relative to i/q nyquist bw 0 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 magnitude e db e1 e2 e3 e4 e5 e6 figure 13. cascaded filter pass-band detail (n = 3) signals having a bandwidth of no more than about 60% of f nyq . thus, in order to keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of two prior to representing it to the ad9879. note that without oversampling, the nyquist bandwidth of the baseband data corresponds to the f nyq . as such, the upper end of the data bandwidth will suffer 6 db or more of attenuation due to the frequency response of the digital filters. furthermore, if the baseband data applied to the ad9879 has been pulse shaped, there is an additional concern. typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. in such cases, an value is used to modify the band- width of the data where the value of is such that 0 < < 1. a value of 0 causes the data bandwidth to correspond to the nyquist bandwidth. a value of 1 causes the data bandwidth to be extended to twice the nyquist bandwith. thus, with 2 over- sampling of the baseband data and =1, the nyquist bandwidth of the data will correspond with the i/q nyquist bandwidth. as stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. the maximum value of that can be implemented is 0.45. this is because the data bandwidth becomes: 12 1 0 725 + () = ff nyq nyq . which puts the data bandwidth at the extreme edge of the flat portion of the filter response. if a particular application requires an value between 0.45 and 1, then the user must oversample the baseband data by at least a factor of four. the combined hb1, hb2, and cic filter introduces, over the frequency range of the data to be transmitted, a worst-case droop of less than 0.2 db.
rev. 0 ad9879 e19e tx signal level considerations the quadrature modulator itself introduces a maximum gain of 3 db in signal level. to visualize this, assume that both the i data and q data are fixed at the maximum possible digital value, x . then the output of the modulator, z is: zx cos t x sin t = () () [] e i o x z x figure 14. 16-quadrature modulation it can be shown that | z | assumes a maximum value of | z | = (x 2 + x 2 ) = 2 z |values, as is used to repre- sent the x values, an overflow would occur. to prevent this possibility, an effective e3 db attenuation is internally imple- mented on the i and q data path: || / / zx =+ () = 12 12 3 low- pass filter tx ad 832x dac ad 9879 ca 75 variable gain cable driver amplif ier ca_data ca_clk ca_en tp maximum symbol component input value lsbs db lsbs = ? () = 2047 0 2 2000 . maximum complex input rms value lsbs db pk rms db lsbs rms = ? () = 2000 6 1265 the maximum complex input rms value calculation uses both i and q symbol components that add a factor of 2 (= 6 db) to the formula. table vii shows typical i-q input test signals with ampli- tude levels related to 12-bit full scale (fs). tx throughput and latency data inputs effect the output fairly quickly but remain effective due to ad9879?s filter characteristics. data transmit latency through the ad9879 is easiest to describe in terms of f sysclk clock cycles (4 f mclk ). the numbers quoted are when an effect is first seen after an input value change. latency of i/q data entering the data assembler (ad9879 input) to the dac output is 119 f sysclk clock cycles (29.75 f mclk cycles). dc values applied to the data assembler input will take up to 176 f sysclk clock cycles (44 f mclk cycles) to propagate and settle at the dac output. frequency hopping is accomplished via changing the profile input pin. the time required to switch from one frequency to another is less than 232 f sysclk cycles (58.5 f mclk cycles). d/a converter a 12-bit digital-to-analog converter (dac) is used to convert the digitally processed waveform into an analog signal. the worst-case spurious signals due to the dac are the harmonics of the fundamental signal and their aliases (please see the analog devices dds tutorial at: www.analog.com/dds). the conver sion process will produce aliased components of the fun- damental signal at n f sysclk f carrier ( n = 1, 2, 3). these are typically filtered with an external rlc filter at the dac output. it is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest so as to avoid modulation impairments. a relatively inexpensive seventh order elliptical low-pass filter is sufficient to suppress the aliased components for hfc network applications. the ad9879 provides true and complement current outputs. the full-scale output current is set by the r set r esistor at pin 49 and the dac gain register. assuming maximum dac gain, the value of r set for a particular full-scale i out is determined using the following equation: rv i i set dacrset out out == 32 39 4 . for example, if a full-scale output current of 20 ma is desired, then r set = (39.4/0.02) , or approximately 2 k . the following equation calculates the full-scale output current including the programmable dac gain control. ir ngain out set =+ [./ ] ((e . . ) / ) 39 4 10 7 5 0 5 20 where n gain is the value of dac fine gain control[3:0]. table vii. ieq input test signals analog output digital input input level modulator output level single tone (f c e f) i = cos(f) fs e 0.2 db fs e 3.0 db q = cos(f + 90 ) = esin(f) fs e 0.2 db single tone (f c + f) i = cos(f) fs e 0.2 db fs e 3.0 db q = cos(f + 270 ) = +sin(f) fs e 0.2 db dual tone (f c f) i = cos(f) fs e 0.2 db fs q = cos(f + 180 ) = ecos(f) or q = +cos(f) fs e 0.2 db
rev. 0 e20e ad9879 the full-scale output current range of the ad9879 is 4 mae20 ma. full-scale output currents outside of this range will degrade sfdr performance. sfdr is also slightly affected by output matching, that is, the two outputs should be termi- nated equally for best sfdr performance. the output load should be located as close as possible to the ad9879 package to minimize stray capacitance and inductance. the load may be a simple resistor to ground, an op amp current-to-voltage con- verter, or a transformer-coupled circuit. it is best not to attempt to directly drive highly reactive loads (such as an lc filter). driving an lc filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. the parallel combination of the two terminations will determine the load that the ad9879 will see for signals within the filter pass band. for example, a 50 terminated input/output low-pass filter will look like a 25 load to the ad9879. the output compliance voltage of the ad9879 is e0.5 v to +1.5 v. any signal developed at the dac output should not exceed +1.5 v, otherwise signal distortion will result. furthermore, the signal may extend below ground as much as 0.5 v without damage or signal distortion. the ad9879 true and complement outputs can be differentially combined for common-mode rejection using a broadband 1:1 transformer. using a grounded center tap results in signals at the ad9879 dac output pins that are symmetrical about ground. as previ- ously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. a differential combiner might consist of a transformer or an operational amplifier. the object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 hz hum or clock feedthrough that is equally present on both individual signals. dac low-pass filter 75 variable gain cable driver amplifier ca_en ca_data ca_c ca t ad ad cac ca_en ca_c ca_data c c c c c s s cat cad adadadad t ad prranteadadradad caedreraperancntr pad ad ad tadadadad ttcs rr scdc r d pr ad adtad srwa ad tad cpstadpr eps ad t ad wadcdacr tad ad ad c cca_en tad t c
rev. 0 ad9879 e21e receive path (rx) if10 and if12 adc operation the if10 and if12 adcs have a common architecture and share many of the same characteristics from an applications standpoint. most of the information in the section below will be applicable to both if adcs. differences, where they exist, will be highlighted. input signal range and digital output codes the if adcs have differential analog inputs labelled if+ and ife. the signal input, v ain , is the voltage difference between the two input pins, v ain = v if+ e v ife . the full-scale input voltage range is determined by the internal reference voltages, reft and refb, which define the top and bottom of the scale. the peak input voltage to the adc is the difference between reft and refb which is 1 v pd . this results in the adc full- scale input voltage range of 2 v ppd . the digital output code is straight binary and is illustrated in table viii. table viii. if[11:0] input signal voltage 111...111 v ain >= +1.0 v 111...111 v ain = +1.0 e (1 lsb) v 111...110 v ain = +1.0 e (2 lsb) v ... 100...001 v ain = +1 lsb v 100...000 v ain = 0.0 v 011...111 v ain = e1 lsb v ... 000...001 v ain = e1.0 + (2 lsb) v 000...000 v ain = e1.0 v 000...000 v ain < e1.0 v the if10 adc digital output code occupies the 10 most signifi- cant bits of the rx digital output port (if[11:2]). the output codes clamp to the top or the bottom of the scale when the inputs are overdriven. driving the input the if adcs have differential switched capacitor sample-and- hold amplifier (sha) inputs. the nominal differential input impedance is 4.0 k || 3 pf. this impedance can be used as the effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from non-zero source impedances. it should be noted however that for best performance additional requirements must be met by the signal source. the sha has input capacitors that must be recharged each time the input is sampled. this results in a dynamic input current at the device input. this demands that the source has low (<50 v) output impedance at frequencies up to the adc sampling frequency. also, the source must have settling to better than 0.1% in <1/2 adc clk period. another consideration for getting the best performance from the adc inputs is the dc biasing of the input signal. ideally, the signal should be biased to a dc level equal to the midpoint of the adc reference voltages, reft12 and refb12. nominally, this level will be 1.2 v. when ac-coupled, the adc inputs will self- bias to this voltage and requires no additional input circuitry. figure 20 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the adc input. the 33 series termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. the series capacitors provide ac signal coupling which ensures that the adc inputs operate at the optimal dc bias voltage. the shunt capacitor sources the dynamic currents required to charge the sha input capacitors, removing this requirement from the adc buffer. the values of cc and cs should be calculated to get the correct hpf and lpf corner frequencies. t ee t md t od mclk rxsync rxiq data i[7:4] i[3:0] i[7:4] i[3:0] q[7:4] q[3:0] if10 if12 if10 if12 if10 if12 refclk if data m = 8 figure 18. rx port timing (default mode: multiplexed if adc data) t ee t md t od mclk rxsync rxiq data i[7:4] i[3:0] i[7:4] i[3:0] q[7:4] q[3:0] if10 or if12 refclk if data if10 or if12 if10 or if12 m = 8 figure 19. rx port timing (nonmultiplexed data) ainp ainn 33 c s v s c c c c 33 figure 20. simple adc drive configuration
rev. 0 e22e ad9879 pcb design considerations although the ad9879 is a mixed-signal device, the part should be treated as an analog component. the digital circuitry on-chip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. following the power, grounding, and layout recommen- dations in this section will help the user get the best performance from the mxfe. component placement if the three following guidelines of component placement are followed, chances for getting the best performance from the mxfe are greatly increased. first, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. in order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this will keep the highest frequency return current paths short, and prevent them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device which will further reduce the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the mxfe. the analog circuits should be placed furthest from the power supply. the ad9879 has several pins which are used to decouple sensi- tive internal nodes. these pins are refio, refb10, reft10, refb12, and reft12. the decoupling capacitors connected to these points should have low esr and esl. these capacitors should be placed as close to the mxfe as possible and be con- nected directly to the analog ground plane. the resistor connected to the fsadj pin and the rc network connected to the pllfilt pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling the ad9879 evaluation board demonstrates a good power supply distribution and decoupling strategy. the board has four layers; two signal layers, one ground plane and one power plane. the power plane is split into a 3 vdd section which is used for the 3 v digital logic circuits, a dvdd section that is used to supply the digital supply pins of the ad9879, an avdd section that is used to supply the analog supply pins of the ad9879, and a vanlg section that supplies the higher voltage analog components on the board. the 3 vdd section will typically have the highest frequency currents on the power plane and should be kept the furthest from the mxfe and analog sections of the board. the dvdd portion of the plane brings the current used to power the digital portion of the mxfe to the device. this should be treated similar to the 3vdd power plane and be kept from going underneath the mxfe or analog compon ents. the mxfe should largely sit above the avdd portion of the power plane. the avdd and dvdd power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the dvdd portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source and dvdd and between the source and avdd. both dvdd and avdd should have a low esr, bulk decoupling capacitor on the mxfe side of the ferrite as well as a low esr, esl decoupling capacitors on each supply pin (i.e., the ad9879 requires 17 power supply decoupling caps). the decoupling caps should be placed as close to the mxfe supply pins as possible. an example of the proper decoupling is shown in the ad9875 evaluation board schematic. ground planes in general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. all ground connections should be made as short as possible. this will result in the lowest imped- ance return paths and the quietest ground connections. if the components cannot be placed in a manner that would keep the high frequency ground currents from traversing under the mxfe and analog components, it may be necessary to put current steering channels into the ground plane to route the high fre- quency currents around these sensitive areas. these current steering channels should be made only when and where necessary. signal routing the digital rx and tx signal paths should be kept as short as possible. also, the impedance of these traces should have a controlled impedance of about 50 . this will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, then series termi- nation resistors (33 to 47 ) should be placed close to all signal sources. it is a good idea to series terminate all clock signals at their source regardless of trace length. the receive (i in, q in, and rf in) signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the rx+/e signals form a differential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe will further reduce the possibility of noise corrupting these signals.
rev. 0 ad9879 e23e outline dimensions 100-lead plastic quad flatpack (mqfp) (s-100c) dimensions shown in millimeters 81 100 1 50 31 30 51 top view (pins down) pin 1 80 12.35 ref 23.20 bsc 3.40 max seating plane 0.13 coplanarity 1.03 0.88 0.73 2.90 2.70 2.50 20.00 bsc 18.85 ref 14.00 bsc 17.20 bsc 0.40 0.22 0.65 bsc 0.50 0.25 compliant to jedec standards ms-022-gc-1
c02773e0e8/02(0) printed in u.s.a. e24e

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