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myson technology MTL005 rev 0.9 this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. revision 0.9 - 1 - 2000/12/29 xga flat panel controller features general auto configuration of sampling clock frequency, phase, h/v center, as well as white balance. auto detection of present or non-present or over range sync signals and their polarities. composite sync separation and odd/even field detection of interlaced video. no external memory required. on-chip out put pll provide clock frequency fine-tune (inverse, duty cycle and delay). serial 2-wire i 2 c host interface. 3.3v supplier, 5v i/o tolerance in 128-pin pqfp package. input processor single rgb (24-bit) input rates up to 100mhz. support both non-interlaced and interlaced rgb graphic input signals. yuv 4:2:2 or yuv 4:1:1 (ccir601/ccir656) interla ced video input. glue-free connection to philips saa711x digital video decoder. built-in yuv to rgb color space converter. compliant with digital lvds/ panellink tmds input interface. pc input resolution up to xga 1024x768 @85hz. video processor independent programmable horizontal and vertical scaling up ratios from 1 to 32 flexible de-interlacing unit for digital yuv video input data. zoom to full screen resolution of de-interlaced yuv video data stream. built-in programmable gain control for white balance alignments. built-in programmable 8-bit gamma correction table. built-in programmable temporal color dithering. built-in programmable interpolatio n look-up table. support smooth panning under viewing window change. output processor single pixel (18/24-bit) or dual pixel (36/48-bit) per clock digital rgb output. built-in output timing generator with programmable clock and h/v sync. support vga/svga/xga display resolution. overlay input interface with external osd controller. double scan capability for interlaced input. general description the MTL005 flat panel display (fpd) controller is a low-cost input format converter for tft-lcd monitor or lcd tv application which accepts 15-pin d-sub rgb graphic signals (through adc), yuv signals from digital video decoder or digital rgb graphic signals from panellink tmds receiver. it comprises a rgb/yuv input processor, video scaling up processor , osd input interface and output display processor in 128-pin pqfp.
myson technology MTL005 rev 0.9 revision 0.9 - 2 - 2000/12/29 block diagram applications MTL005 fpd monitor controller mtv212 8-bit mcu mtv130 osd tft-lcd flat panel lvds/ panellink tmds receiver digital video decoder adc composite/ s-video d-sub rgb graphic signals yuv input yuv to rgb rgb input zoom buffer ditherin g host interface mode detect auto calibration osd & output mux digital video pc rgb to i2c bus to external osd rgb output scale up gain contr ol gamma correct display timing generator
myson technology MTL005 rev 0.9 revision 0.9 - 3 - 2000/12/29 1. pin connection MTL005 (128-pin pqfp) pvss * 103 scl * 104 sda * 105 testmode * 106 extdclk2 * 107 pvdd * 108 extdclk1 * 109 dvss * 110 b2out0 * 111 b2out1 * 112 b2out2 * 113 b2out3 * 114 b2out4 * 115 b2out5 * 116 b2out6 * 117 b2out7 * 118 dvdd * 119 g2out0 * 120 g2out1 * 121 g2out2 * 122 g2out3 * 123 g2out4 * 124 g2out5 * 125 g2out6 * 126 g2out7 * 127 dvss * 128 038 * nc 037* r1out1 036 * r1out0 035 * dvdd 034 * g1out7 033 * g1out6 032 * g1out5 031 * g 1out4 030 * g1out3 029 * g1out2 028 * g1out1 027 * g1out0 026 * dvss 025 * b1out7 024 * b1out6 023 * b1out5 022 * b1out4 021 * b1out3 020 * b1out2 019 * b1out1 018 * b1out0 017 * d vdd 016 * dhsync 01 5 * dvsync 014 * dvss 013 * ddclk 1 012 * dden 011 * d dclk2 010 * pvdd 009 * r2out7 008 * r2out6 007 * r2out5 006 * r2out4 005 * r2out3 004 * r2out2 003 * r2out1 002 * r2out0 001 * pvss 064 * d vss 063* rawhs 06 2 * rgbsel 061 * adhs 060 * advs 059* clamp 05 8 * tmdssel 057 * d vdd 056* ohsync 05 5 * oclk 05 4 * ovsync 05 3 * irq 052 * pvdd 051 * osden 050 * osdblu 049 * osdgrn 048 * osdred 047 * rstz 046 * dvss 045 * r1out 7 044 * r1out 6 043 * r1out 5 042 * r1out 4 041 * r1out 3 0 40 * r1out 2 03 9 * pvss dvss * 065 tdie * 066 vsync * 067 ipclk * 068 hsync * 069 dvdd * 070 r in7 * 071 r in6 * 072 r in5 * 073 rin4 * 074 r in3 * 075 r in2 * 076 r in1 * 077 r in0 * 078 dvss * 079 g in7 * 080 g in6 * 081 g in5 * 082 gin4 * 083 gin3 * 084 g in2 * 085 g in1 * 086 g in0 * 087 dvdd * 088 b in7 * 089 b in6 * 090 b in5 * 091 bin4 * 092 bin3 * 093 bin2 * 094 bin1 * 095 bin0 * 096 dvdd * 097 avdd * 098 xi * 099 xo * 100 avss * 101 dvss * 102
myson technology MTL005 rev 0.9 revision 0.9 - 4 - 2000/12/29 2. pin description adc input interface (rgb or yuv or tmds input data) name type pin# description ipclk i 68 input pixel clock vsync i 67 input vertical sync hsync/cs i 69 input horizontal or composite sync rin[7:0]/yin[7:0] i 71-78 red or y channel or tmds input data gin[7:0]/uvin[7:0] i 80-87 green or uv channel or tmds input data bin[7:0] i 89-96 blue or tmds input data, or control bit for yuv video input bit 4: vphref, video input horizontal reference signal bit 3: vpvs, video input vsync signal bit 2: vpodd, video input odd/even field signal bit 1: vphs, video input hsync signal bit 0: vpclk, video input clock signal rawhs i 63 input source hsync for measurement tdie i 66 tmds digital input enable rgbsel o 62 input select. 1:rgb input, 0:yuv input tmdssel o 58 tmds input select, active high clamp o 59 clamp pulse output for adc display output interface name type pin# description dden o 12 display data output enable dvsync o 15 display vertical sync output dhsync o 16 display horizontal sync output ddclk1 o 13 display output clock 1 ddclk2 o 11 display output clock 2 r1out[7:0] o 45-40, 37-36 red output even data , bit[7:2] for 6-bit panel g1out[7:0] o 34-27 green output even data , bit[7:2] for 6-bit panel b1out[7:0] o 25-18 blue output even data , bit[7:2] for 6-bit panel r2out[7:0] o 9-2 red output odd data , bit[7:2] for 6-bit panel g2out[7:0] o 127-120 green output odd data , bit[7:2] for 6-bit panel b2out[7:0] o 118-111 blue output odd data , bit[7:2] for 6-bit panel host interface name type pin# description rst# i 47 system reset input, active low. scl i 104 serial bus clock sda i/o 105 serial bus data testmode i 106 test mode, normally grounded. irq o 53 interrupt request output osd interface name type pin# description oclk o 55 clock for external osd ovsync o 54 vertical sync for external osd ohsync o 56 horizontal sync for external osd osdred i 48 osd red input osdgrn i 49 osd green input osdblu i 50 osd blue input osden i 51 osd overlay enable
myson technology MTL005 rev 0.9 revision 0.9 - 5 - 2000/12/29 other interface name type pin# description xi i 99 oscillator frequency input xo o 100 oscillator frequency output extdclk1 i 109 external display clock input 1 extdclk2 i 107 external display clock input 2 advs o 60 vertical sync for a/d converter adhs o 61 horizontal sync for a/d converter nc - 38 no connection 3.3v power and ground name pin# description dvdd 17, 35, 57, 70, 88, 97, 119 digital power 3.3v dvss 14, 26, 46, 64, 65, 79, 102, 110, 128 digital ground pvdd 10, 52, 108 pad power 3.3v pvss 1, 39, 103 pad ground avdd 98 analog power 3.3v avss 101 analog ground
myson technology MTL005 rev 0.9 revision 0.9 - 6 - 2000/12/29 3. functional description 3.1 input processor general description the function of input interface is to provide the interface between MTL005 and external input devices. it can process both non-interlaced and interlaced rgb graphic input, yuv video input, and digital rgb input compliant with digital lvds/ panellink tmds interface. it also contains the built-in yuv to rgb color space converter. 3.1.1 rgb input format since MTL005 is a low cost solution, the rgb input port can only work in single pixel mode (24 bits). the r/g/bin ports are sampled at the rising edge of the rgb input clock. 3.1.2 tmds input format the digital rgb input port works likewise as described in sec 3.1.1 except one more input pin is needed: digital input enable dien. with a single pixel input interface, the supported format is up to true color, including 18 bit/pixel or 24 bit/pixel. 3.1.3 yuv i nput format the yuv input port supports interlaced video data from the most common video decoder ics like saa711x. the 16 bit data bus is shared with the ports rin[7:0] and gin[7:0]. the 16 bit data is sampled at the rising edge of the shared video clock vpclk when the shared data enable href is active. the supported formats are yuv4 :1:1 and yuv4:2:2 with ccir601/ccir656 standard. 3.1.4 input hsync path besides the pin hsync, MTL005 provides another pin rawhs to support sync processor in MTL005. generally, the hsync generated by an adc may have a very narrow pulse width and a different polarity from the original hsync provided by the source. the rawhs input provides the path of original hsync connection to MTL005, which makes sync processor in MTL005 work correctly. 3.1.5 yuv to rgb converter it is used to convert ycbcr format into rgb format. the basic equations are as follows: r = y + 1.371( cr - 128) g = y - 0.698( cr - 128) - 0.336( cb - 128) b = y + 1.732( cb - 128) 3.1.6 de-interlace mode for interlace input, MTL005 features several de-interlacing algorithms for processing interlaced video data depending on the type of input images. toggle mode in this mode, only one field is displayed at the time. first field and second field is toggled displayed. the missing lines are calculated from duplicating the neighbor lines. spatial mode in this mode, two fields are toggled displayed, just like toggle mode. the missing lines are calculated from interpolating the neighbor lines. an average good quality for still and moving pictures is achieved in this mode. 3.1.7 sync processor the v/h sync processing block performs the functions of composite signal separation/insertion, sync inputs presence check, frequency counting, polarity detection and control. it contains a de-glitch circuit to filter out any pulse shorter than one osc period treated as noises on v/h sync pulses.
myson technology MTL005 rev 0.9 revision 0.9 - 7 - 2000/12/29 v/h sync frequency counter MTL005 can measure vsync/hsync frequency counted in proper clocks and save the information in registers. users can read it out to calculate vsync/hsync frequency as in the following formulas: f vsync = f osc / n vsync 5 1/256 f hsync = f osc / n hsync 5 8 ,where f vsync : vsync frequency f hsync : hsync frequency f osc : oscillator clock with 14.31818 mhz n vsync : counted number of vsync n hsync : counted number of hsync v/h sync presence check this function checks the input vsync, where vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz ,and the input hsync, where hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. v/h polarity detect this function detects the input vsync/hsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. composite sync separation/insertion MTL005 continuously monitors the input hsync. if the input vsync can be extracted from it, a cvpre flag is set. MTL005 can insert hsync pulse during composite vsync ? s active time and the insertion frequency can adapt to original hsync ? s. 3.1.8 auto tune auto tune function consists of auto position automatically centering the screen and auto calibration containing phase calibration, histogram, min/max value, and pixel grab described as below. with this auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of adc. the horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. firmware can adjust input image registers automatically by reading auto tune ? s registers in single or burst mode. auto position MTL005 provides horizontal/vertical back porch and active region values. users can use these values to set input sample registers to aid in centering the screen automatically. phase calibration MTL005 provides auto calibration registers to measure the quality of current adc ? s phase and frequency. the biggest auto calibration registers value means the right value of adc ? s phase and frequency. MTL005 has two kinds of algorithms to calculate auto calibration ? s value. one is traditional difference method , another is myson ? s proprietary method. it is suggested to use the latter one for better performance histogram histogram means the total number of input pixels below/above one threshold value, for individual r, g, b colors. this advanced function helps firmware to analyze adc performance. usually firmware can use this information to measure adc ? s noise margin, adjust its offset and gain, or even aid in the mode detection. min/max value min/max value means minimum or maximum pixel value within the specified input active image region for each rgb channel. this information is usually used to adjust adc ? s offset and gain. pixel grab pixel grab means users can grab a single input pixel at any one point. the position of the point can be programmed by users. this is another traditional method to measure adc ? s phase and frequency.
myson technology MTL005 rev 0.9 revision 0.9 - 8 - 2000/12/29 3.2 video processor general description MTL005 possesses a powerful and programmable video processor by providing the following functions: scaling up/down, gain control, brightness control, gamma correction, dithering control, and flip & mirror. the block diagram of video processor is as follows: fig. 3.2.1 video processor block diagram 3.2.1 scaling MTL005 provides scaling function up ranging from 1 to 32, and for both horizontal and vertical processing. for scaling up, both horizontal and vertical processing, MTL005 provides four methods: pass mode : image will be passed through without considering any scaling factor. duplicate mode : image will be scaled up based on scaling factor. every point of output image comes from the input. in this method, output image will have the good contrast but may be non-uniformed. bilinear mode : image will be scaled up based on scaling factor. every point of output image data will be filtered by bilinear filter. in this method, output image will have the good scaling quality but may be blurred. interpolation table mode : image will be scaled up based on scaling factor. every point of output image data will be filtered by user defined filter. gain brightness gamma dithering scaling transition table scaling factor brightness factor gamma table gain factor dithering table flip/mirror
myson technology MTL005 rev 0.9 revision 0.9 - 9 - 2000/12/29 fig. 3.2.2 scaling filter 3.2.2 gain/brightness control MTL005 provides gain and brightness control to adjust the contrast and brightness of output color by programming gain and brightness coefficients. this adjustment is applied to rgb colors individually. auto- white balance is possible by using this function. 3.2.3 gamma correction gamma correction is used to compensate the non-linearity of lcd display panel. MTL005 contains a 8-bit gamma table to fix this phenomenon. 3.2.4 color dithering MTL005 supports true color (8 bits per color) or high color (6 bits per color) display. in the latter case, users can turn on dithering function to avoid artificial contour due to truncation. for dithering, it supports two methods: static dithering: dithering coefficient is fixed. temporal dithering: dithering coefficient will change by time. interpolation pixel input pixel a b o 64 sc 32 63 32 63 sc sc ? o = [(64-sc ? )*a + sc ? *b]/64 [ a] [ b] [ c] [ a]: duplicate filter [ b]: bilinear filter [ c]: user defined filter
myson technology MTL005 rev 0.9 revision 0.9 - 10 - 2000/12/29 3.3 output processor general description output processor provides the interface for both lcd panel and osd controller. output frame rate must be equal to input frame rate and output display time must be equal to input display time, because of no frame buffer. 3.3.1 display timing generation output frame rate is equal to input frame and external frame buffer is not needed. fig. 3.3.1 display timing modes 3.3.2 osd overlay MTL005 allows the integration of overlay data with the scaled output pixel stream. it provides a fully compatible osd interface. individual osd clock, osd hsync and osd vsync are sent to external osd device. MTL005 receives osd enable, osd red, osd green, and osd blue from external osd device. 3.3.3 rgb output format MTL005 output interface consists of two pixel ports, each containing red, green, and blue color information with a resolution of 6/8 bits per color. these two ports are mapped to port1 and port2. the control signals for output port are display horizontal sync signal (dhsync) , display vertical sync signal (dvsync) and display data enable signal (dden). all the signals mentioned above are synchronous to the output clock. the output timing relative to the active edge of the output clock is programmable. there are two rgb output formats: single pixel mode it is designed to support tft panels with single pixel input. only port1 is active. the frequency of dclk1 is equal to internal display clock. dual pixel mode it is designed to support tft panels with dual pixel input. port1 and port2 are used. the first pixel is at port1, and the second at port2. x x: lock position input frame output frame
myson technology MTL005 rev 0.9 revision 0.9 - 11 - 2000/12/29 dclk dden r1out/g1out /b1out 000 rgb0 rgb1 rgb2 rgb3 rgb4 dclk1 dden dclk2 dclk r1out/g1out /b1out 000 rgb0 rgb2 rgb4 rgb6 rgb8 r2out/g2out /b2out 000 rgb1 rgb3 rgb5 rgb7 rgb9 single port dual port fig. 3.3.2 display data timing
myson technology MTL005 rev 0.9 revision 0.9 - 12 - 2000/12/29 3.4 host interface general description the main function of host interface is to provide the interface between MTL005 and external cpu by 2-wire i2c bus. it can generate all the i/o decoded control timing to control all the registers in MTL005. 3.4.1 i2c serial bus the i2c serial interface use 2 wires, sck (clock) and sda(data i/o). the sck is used as the sampling clock and sda is a bi-directional signal for data. the communication must be started with a valid start condition, concluded with stop condition and acknowledged with ack condition by receiver. the i2c bus device address of MTL005 is 0111010x. sck, serial bus clock. sda, bi-directional serial bus data. the start condition means a high to low transition of sda when sck is high , the stop condition means a low to high transition of sda when sck is high. and data of sda only can change during sck is low. ref. fig.3.5.1. fig. 3.4.1 start, stop ,and data definition the i2c interface supports random write, sequential write, current address read, random read and sequential read operations. random write for random write operation, it contains the slave address with r/w bit set to 0 and the word address which is comprised of eight bits and provides to access any one of 256 bytes in the selected memory range. upon receipt of the word address, MTL005 responds with an acknowledge, waits the data bits again responding an acknowledge, and then the master generates a stop condition. ref. fig.3.5.2. sda sck start data change data change stop
myson technology MTL005 rev 0.9 revision 0.9 - 13 - 2000/12/29 fig. 3.4.2 random write sequential write the initial step of sequential write is the same as random write, after the receipt of each word data, MTL005 will respond with an acknowledge and then internal address counter will increment by one for next data write. if the master would stop writing data, it generates stop condition. ref. fig. 3.5.3. fig. 3.4.3 sequential write current address read MTL005 contains an address counter which maintains the last access address incremented by one. if the last access address is n, the read data should access from address n+1. upon receipt of the slave address with r/w bit set to 1, MTL005 generates an acknowledge and transmits eight bits data. after receiving data the master will generate a stop condition instead of an acknowledge. ref. fig. 3.5.4. fig. 3.5.4 current address read s t a r t a c k slave address data r sda s t o p s t a r t a c k a c k a c k s t o p slave address word address data w sda sda s t a r t a c k a c k a c k slave address word address data n w data n+1 s t o p a c k a c k data n+x
myson technology MTL005 rev 0.9 revision 0.9 - 14 - 2000/12/29 random read the operation of random read allows accessing any address. before reading data operation, it must issue a ? dummy write ? operation ? a start condition, a slave address with r/w bit set to 0, and word address for read. after responding an acknowledge, MTL005 then transmits eight bits data right after the master generating the start condition and slave address with r/w bit set to 1. after completion of receiving data, the master will generate a stop condition instead of an acknowledge. ref. fig 3.5.5. fig. 3.4.5 random read sequential read the initial step can be as either current address read or random read. the first read data is transmitted the same manner as other read methods. however, the master generates an acknowledge indicating that it requires more data to read. MTL005 continues to output data for each acknowledge received. the output data is sequential and the internal address counter increments by one for next read data. ref. fig. 3.5.6. fig. 3.4.6 sequential read 3.4.2 interrupt MTL005 supports one interrupt output signal (irq) which can be programmed to provide sync related or function status related interrupts to the system. upon receiving the interrupt request, firmware needs to first check the interrupt event by reading the interrupt flag control registers (reg. e8h and e9h) to decide what events are happening. after the operation is finished, firmware needs to clear interrupt status by writing the same registers reg. e8h and e9h. furthermore, by using the interrupt flag enable registers (reg. eah and ebh), each interrupt event can be masked. 3.4.3 update register contents i/o write operation to some consecutive register set can have the ? double buffer ? effect by setting the reg. c1h/d4. written data is first stored in an intermediate bank of latches and then transferred to the active register set by setting reg. c1h/d1-0. s t a r t a c k a c k a c k slave address word address w sda s t a r t slave address r data s t o p s t a r t a c k slave address data n r sda data n+1 a c k a c k data n+x s t o p
myson technology MTL005 rev 0.9 revision 0.9 - 15 - 2000/12/29 3.5 on-chip pll general description the MTL005 needs two clock sources to drive synchronous circuits on chip. these clocks are generated from the internal phase lock loop (pll) circuits with reference to the oscillator clock which is applied to pin xi and xo by an external quartz crystal at 14.31818 mhz. first one is the same as to the oscillator clock at frequency (14.31818 mhz) to detect and measure graphic vertical and horizontal sync frequency, polarity as well as presence. the second is the display clock for display controller on chip and output signals to lcd panel. 3.5.1 reference clock it is the counting basis of counter values in sync processor such as vs and hs period count registers; that is, the read back values from these registers must multiply the period of this clock to estimate vs and hs frequency. incorporating with polarity and frequency information of vs and hs, it can show the input graphic image mode and pixel clock frequency. 3.5.2 display clock this clock is the synchronous clock for lcd panel. according to the lcd panel resolution of applications, the display clock range is from 50 mhz to 200 mhz by means of choosing a set of appropriate values for m, n as well as r. the formula to calculate desired frequency of display clock is as follows: f mclk = f osc 5 (m+2)/(n+2) 5 1/r where f mclk : the desired display clock f osc : oscillator clock with 14.31818 mhz m : post-divider ratio n : pre-di vider ratio r : optional divider ratio
myson technology MTL005 rev 0.9 revision 0.9 - 16 - 2000/12/29 4. register description input control registers address mode registers reset value 00h r/w input image vertical active line start - low 00h 01h r/w input image vertical active line start - high 00h 02h r/w input image vertical active lines - low 00h 03h r/w input image vertical active lines - high 00h 04h r/w input image horizontal active pixel start - low 00h 05h r/w input image horizontal active pixel start - high 00h 06h r/w input image horizontal active pixels - low 00h 07h r/w input image horizontal active pixels - high 00h 10h r/w input image control register 0 00h 11h r/w input image control register 1 00h 12h r/w input image control register 2 00h 13h r/w input image control register 3 00h 14h r/w input image control register 4 00h 15h r/w input image control register 5 00h 16h r/w input image control register 6 00h 1ah r/w input delay control 2 00h 1ch r/w hs1 sample window forward extend 00h 1dh r/w hs1 sample window backward extend 00h 1fh ro input image status register - 20h r/w input image back porch guard band 00h 21h r/w input image front porch guard band 00h frame sync registers address mode registers reset value 2ch r/w input image vertical lock position - low 00h 2dh r/w input image vertical lock position - high 00h 2eh r/w input image horizontal lock position - low 00h 2fh r/w input image horizontal lock position - high 00h auto calibration registers address mode registers reset value 30h r/w auto calibration control 0 80h 31h r/w auto calibration control 1 00h 34h ro auto calibration red value - byte 0 - 35h ro auto calibration red value - byte 1 - 36h ro auto calibration red value - byte 2 - 37h ro auto calibration red value - byte 3 - 38h ro auto calibration green value - byte 0 - 39h ro auto calibration green value - byte 1 - 3ah ro auto calibration green value - byte 2 - 3bh ro auto calibration green value - byte 3 - 3ch ro auto calibration blue value - byte 0 - 3dh ro auto calibration blue value - byte 1 - 3eh ro auto calibration blue value - byte 2 - 3fh ro auto calibration blue value - byte 3 - 40h r/w pixel grab v reference position ? low 00h
myson technology MTL005 rev 0.9 revision 0.9 - 17 - 2000/12/29 41h r/w pixel grab v reference position ? high 00h 42h r/w pixel grab h reference position ? low 00h 43h r/w pixel grab h reference position ? high 00h 44h r/w histogram reference color - red 00h 45h r/w histogram reference color - green 00h 46h r/w histogram reference color - blue 00h sync processor registers address mode registers reset value 48h r/w sync processor control 00h 49h r/w auto position control 00h 4ah r/w auto position reference color - red 00h 4bh r/w auto position reference color - green 00h 4ch r/w auto position reference color - blue 00h 4eh r/w clamp pulse control 0 00h 4fh r/w clamp pulse control 1 00h 50h ro input vs period count by refclk - low - 51h ro input vs period count by refclk - high - 52h ro input v back porch count by input hs - low - 53h ro input v back porch count by input hs - high - 54h ro input v active lines count by input hs - low - 55h ro input v active lines count by input hs - high - 56h ro input v total lines count by input hs - low - 57h ro input v total lines count by input hs - high - 58h ro input hs period count by refclk - low - 59h ro input hs period count by refclk - high - 5ah ro input h back porch count by input pixel clock - low - 5bh ro input h back porch count by input pixel clock - high - 5ch ro input h active pixels count by input pixel clock - low - 5dh ro input h active pixels count by input pixel clock - high - 5eh ro input h total pixels count by input pixel clock - low - 5fh ro input h total pixels count by input pixel clock - high - display control registers address mode registers reset value 60h r/w display vertical total - low 00h 61h r/w display vertical total - high 00h 62h r/w display vertical sync end- low 00h 63h r/w display vertical sync end - high 00h 64h r/w display vertical active start - low 00h 65h r/w display vertical active start - high 00h 66h r/w display vertical active end - low 00h 67h r/w display vertical active end - high 00h 70h r/w display horizontal total - low 00h 71h r/w display horizontal total - high 00h 72h r/w display horizontal sync end - low 00h 73h r/w display horizontal sync end - high 00h 74h r/w display horizontal active start - low 00h 75h r/w display horizontal active start - high 00h
myson technology MTL005 rev 0.9 revision 0.9 - 18 - 2000/12/29 76h r/w display horizontal active end - low 00h 77h r/w display horizontal active end - high 00h 7fh r/w nfb timing control 60h 88h r/w output image control register 0 00h 89h r/w output image control register 1 00h 8ah r/w output image control register 2 00h 90h r/w color gain control - red 80h 91h r/w color gain control - green 80h 92h r/w color gain control - blue 80h 93h r/w brightness control - red 00h 94h r/w brightness control - green 00h 95h r/w brightness control - blue 00h 9fh r/w gamma table data port - a0h r/w osd control register 0 08h a1h r/w osd control register 1 00h a2h r/w osd control register 2 00h a4h r/w output invert control 00h a5h r/w output tri-state control 00h a6h r/w output clocks delay adjustment 00h a7h r/w output clocks duty cycle adjustment 00h a9h r/w output miscellaneous control 00h aah r/w output vertical active line number - low ffh abh r/w output vertical active line number - high 02h ach ro output horizontal total pixel number ? low - adh ro output horizontal total pixel number ? high - aeh ro output horizontal total residue number ? low - afh ro output horizontal total residue number - high - zoom control registers address mode registers reset value b0h r/w zoom control register 0 00h b1h r/w zoom control register 1 00h b4h r/w zoom vertical scale ratio - low 00h b5h r/w zoom vertical scale ratio - high 00h b6h r/w zoom horizontal scale ratio - low 00h b7h r/w zoom horizontal scale ratio ? high 00h bfh r/w interpolation table data port - host control registers address mode registers reset value c1h r/w host control register 1 00h cbh ro host access mode status - clock control registers address mode registers reset value e0h r/w clock control register 00h
myson technology MTL005 rev 0.9 revision 0.9 - 19 - 2000/12/29 e1h wo clock synthesizer value load - e2h r/w clock synthesizer n value 0bh e3h r/w clock synthesizer m value 32h e6h r/w clock synthesizer r value 00h interrupt control registers address mode registers reset value e8h r/w sync interrupt flag control 00h e9h r/w general interrupt flag control 00h eah r/w sync interrupt enable control 00h ebh r/w general interrupt enable control 00h ech r/w hs frequency change interrupt compare 00h miscellaneous registers address mode registers reset value f1h r/w power management control 00h input image vertical active line start - low (address 00h) (r/w) it defines the low byte of the start position of the vertical active window. d7-0 iv_act_ start[7:0] input image vertical active line start - high (address 01h) (r/w) it defines the high byte of the start position of the vertical active window. d7-3 reserved d2-0 iv_act_ start[10:8] input image vertical active lines - low (address 02h) (r/w) it defines the low byte of the number of active lines of the vertical active window. d7-0 iv_act_ len[7:0] input image vertical active lines - high (address 03h) (r/w) it defines the high byte of the number of active lines of the vertical active window. d7-3 reserved d2-0 iv_act_ len[10:8] input image horizontal active pixel start - low (address 04h) (r/w) it defines the low byte of the start position of the horizontal active window. d7-0 ih_act_ start[7:0] input image horizontal active pixel start - high (address 05h) (r/w)
myson technology MTL005 rev 0.9 revision 0.9 - 20 - 2000/12/29 it defines the high byte of the start position of the horizontal active window. d7-3 reserved d2-0 ih_act_ start[10:8] input image horizontal active pixels - low (address 06h) (r/w) it defines the low byte of the number of active pixels of the horizontal active window. d7-0 ih_act_ width[7:0] input image horizontal active pixels - high (address 07h) (r/w) it defines the high byte of the number of active pixels of the horizontal active window. d7-3 reserved d2-0 ih_act_ width[10:8] input image control register 0 (address 10h) (r/w) d7 horizontal sampling point reference 0: from input hsync 1: from input href (only for video decoder) d6 input ycbcr format 0: 4-2- 2 1: 4-1-1 d5 digital rgb 6 bit mode 0: 8 bits 1: 6 bits d4 digital rgb mode select 0: rgb input from adc 1: rgb input from panel link d3 input image format 0: rgb888 1: ycbcr d2 reserved d1 input image source 0: from graphic sou rce through adc 1: from video source through video decoder like saa7111a d0 adc configuration 0: double pixel mode 1: single pixel mode input image control register 1 (address 11h) (r/w) d7-5 reserved
myson technology MTL005 rev 0.9 revision 0.9 - 21 - 2000/12/29 d4 de-interlace mode select 0: spat ial filtering write mode 1: toggle field write mode d3 ccir656 mode enable 0: disable 1: enable d2-0 reserved input image control register 2 (address 12h) (r/w) d7 input odd field invert 0: normal 1: invert d6 external input interl ace select 0: non-interlace 1: interlace d5 external input vsync polarity 0: active low 1: active high d4 external input hsync polarity 0: active low 1: active high d3 input odd field source 0: from internal detection 1: from externa l pin d2 input interlace source 0: from internal detection 1: from register setting (d6) d1 input vsync polarity source 0: from internal detection 1: from register setting (d5) d0 input hsync polarity source 0: from internal detection 1: from register setting (d4) input image control register 3 (address 13h) (r/w) d7 active position area for auto position in tmds 0: from internal detection 1: from external data enable (tdie) d6-3 reserved d2 sync on green select 0: select normal hsync/ composite sync 1: select sync on green
myson technology MTL005 rev 0.9 revision 0.9 - 22 - 2000/12/29 d1 input vertical timing based on vsync 0: leading edge 1: trailing edge d0 input horizontal timing based on hsync 0: leading edge 1: trailing edge input image control register 4 (address 14h) (r/w) d7 input odd field detection point 0: at the start of vsync pulse. 1: at the end of vsync pulse. d6-5 reserved d4 input image cbcr order swap 0: normal 1: swap d3-0 reserved input image control register 5 (address 15h) (r/w) d7 horizontal pixel valid select 0: from internal programming 1: from external href d6-0 reserved input image control register 6 (address 16h) (r/w) d7 reserved d6 bit order in port a 0: normal 1: reverse d5-3 reserved d2 adc hs polarity invert when d1=1 0: active low 1: active high d1 raw hs path enable 0: disable 1: enable d0 reserved input delay control 2 (address 1ah) (r/w) d7-4 input vsync delay adjustment 1111: 7 idclks delay 1110: 6 idclks delay 110 1: 5 idclks delay
myson technology MTL005 rev 0.9 revision 0.9 - 23 - 2000/12/29 1100: 4 idclks delay 1011: 3 idclks delay 1010: 2 idclks delay 1001: 1 idclk delay 1000: no delay 0111: 7ns gate delay 0110: 6ns gate delay 0101: 5ns gate delay 0100: 4ns gate delay 0011: 3ns gate delay 0010: 2ns gate delay 0001: 1ns gate delay 0000: no delay d3-0 input hsync delay adjustment 16 steps to change, each of them is 1ns delay/step. input hs pulse width forward extend (address 1ch) (r/w) d7-0 input hs pulse width forward extend by idclk hs1fwext[7:0]: used when interlace first/second field detection. input hs pulse width backward extend (address 1dh) (r/w) d7-0 input hs pulse width backward extend by idclk hs1bwext[7:0]: used when interlace first/second field detection. input image status register (address 1fh) (ro) d7 display vsync monitor show display vsync signal directly. d6 input vsync monitor show input vsync signal directly. d5 external input interlace status 0: non-interlace 1: interlace d4 extracted cv sync present status 0: not present 1: present d3 external input vsync present status 0: not present 1: present d2 external input hsync present status 0: not present 1: present d1 external input vsync polarity status 0: active low 1: a ctive high d0 external input hsync polarity status
myson technology MTL005 rev 0.9 revision 0.9 - 24 - 2000/12/29 0: active low 1: active high input image back porch guard band (address 20h) (r/w) d7-0 input image back porch guard band by idclk hbpgb[7:0]: used in auto position detection to mask out unwanted data. input image front porch guard band (address 21h) (r/w) d7-0 input image front porch guard band by idclk hfpgb[7:0]: used in auto position detection to mask out unwanted data. input image vertical lock position - low (address 2ch) (r/w) it defines the low byte of the number of input lines where display image timing synchronizes the input image source. d7-0 ipv_lock_ pos[7:0] input image vertical lock position - high (address 2dh) (r/w) it defines the high byte of the number of input lines where display image timing synchronizes the input image source. d7-3 reserved d2-0 ipv_lock_ pos[10:8] input image horizontal lock position - low (address 2eh) (r/w) it defines the low byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-0 iph_lock_ pos[7:0] input image horizontal lock position - high (address 2fh) (r/w) it defines the high byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-3 reserved d2-0 iph_lock_ pos[10:8] auto calibration control 0 (address 30h) (r/w) d7 pixel grab ready flag (ro) 0: ready 1: not ready d6 pixel grab update enable 0: stop updating 1: continue updating d5 threshold s elect
myson technology MTL005 rev 0.9 revision 0.9 - 25 - 2000/12/29 used in histogram mode or min/max mode. 0: high bound / max 1: low bound / min d4 phase calibration method select 0: myson proprietary method 1: difference value method d3-2 auto calibration modes select the measured value is availabl e one item at a time, selected as shown: 00: phase calibration mode 01: histogram mode 10: min/max mode 11: pixel grab mode d1 auto calibration burst mode enable ( except pixel grab mode) 0: single mode 1: burst mode d0 auto calibration enable (w) ( except pixel grab value) 0: disable 1: enable auto calibration ready flag (r) 0: ready 1: not ready auto calibration control 1 (address 31h) (r/w) d7-3 reserved d2-0 mask lsbs of input image select 000: no mask 001: mas k bit0 010: mask bit0 ,1 011: mask bit0 ,1,2 100: mask bit0 ,1,2,3 101: mask bit0 ,1,2,3,4 110: mask bit0 ,1,2,3,4,5 111: mask bit0 ,1,2,3,4,5,6 auto calibration red value - byte 0 (address 34h) (ro) it states the byte 0 of the number of phase calibration red value in one frame or the byte 0 of the number of histogram red value in one frame or the pixel grab red value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[7:0] auto calibration red value - byte 1 (address 35h) (ro) it states the byte 1 of the number of phase calibration red value in one frame or the byte 1 of the number of histogram red value in one frame or the pixel grab green value in one frame of non_interlace mode or first field of interlace mode.
myson technology MTL005 rev 0.9 revision 0.9 - 26 - 2000/12/29 d7-0 calval_ r[15:8] auto calibration red value - byte 2 (address 36h) (ro) it states the byte 2 of the number of phase calibration red value in one frame or the byte 2 of the number of histogram red value in one frame or the pixel grab blue value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[23:16] auto calibration red value - byte 3 (address 37h) (ro) it states the byte 3 of the number of phase calibration red value in one frame. d7-6 reserved d5-0 calval_ r[29:24] auto calibration green value - byte 0 (address 38h) (ro) it states the byte 0 of the number of phase calibration green value in one frame or the byte 0 of the number of histogram green value in one frame or the pixel grab red value in one frame of non_interlace mode or second field of interlace mode. d7-0 calval_ g[7:0] auto calibration green value - byte 1 (address 39h) (ro) it states the byte 1 of the number of phase calibration green value in one frame or the byte 1 of the number of histogram green value in one frame or the pixel grab green value in one frame of non_interlace mode or second field of interlace mode. d7-0 calval_ g[15:8] auto calibration green value - byte 2 (address 3ah) (ro) it states the byte 2 of the number of phase calibration green value in one frame or the byte 2 of the number of histogram green value in one frame or the pixel grab blue value in one frame of non_interlace mode or second field of interlace mode. d7-0 calval_ g[23:16] auto calibration green value - byte 3 (address 3bh) (ro) it states the byte 3 of the number of phase calibration green value in one frame. d7-6 reserved d5-0 calval_ g[29:24] auto calibration blue value - byte 0 (address 3ch) (ro) it states the byte 0 of the number of phase calibration blue value in one frame or
myson technology MTL005 rev 0.9 revision 0.9 - 27 - 2000/12/29 the byte 0 of the number of histogram blue value in one frame or the min/max red value in one frame. d7-0 calval_ b[7:0] auto calibration blue value - byte 1 (address 3dh) (ro) it states the byte 1 of the number of phase calibration blue value in one frame or the byte 1 of the number of histogram blue value in one frame or the min/max green value in one frame. d7-0 calval_ b[15:8] auto calibration blue value - byte 2 (address 3eh) (ro) it states the byte 2 of the number of phase calibration blue value in one frame or the byte 2 of the number of histogram blue value in one frame or the min/max blue value in one frame. d7-0 calval_ b[23:16] auto calibration blue value - byte 3 (address 3fh) (ro) it states the byte 3 of the number of phase calibration blue value in one frame. d7-6 reserved d5-0 calval_ b[29:24] pixel grab v reference position - low (address 40h) (r/w) it states the low byte of vertical reference position in pixel grab mode. d7-0 vgrab_ pos[7:0] pixel grab v reference position - high (address 41h) (r/w) it states the high byte of vertical reference position in pixel grab mode. d7-3 reserved d2-0 vgrab_ pos[10:8] pixel grab h reference position - low (address 42h) (r/w) it states the low byte of horizontal reference position in pixel grab mode. d7-0 hgrab_ pos[7:0] pixel grab h reference position - high (address 43h) (r/w) it states the high byte of horizontal reference position in pixel grab mode. d7-3 reserved d2-0 hgrab_ pos[10:8]
myson technology MTL005 rev 0.9 revision 0.9 - 28 - 2000/12/29 histogram reference color - red (address 44h) (r/w) it states the histogram reference red color in histogram mode. d7-0 hist_ r[7:0] histogram reference color - green (address 45h) (r/w) it states the histogram reference green color in histogram mode. d7-0 hist_ g[7:0] histogram reference color - blue (address 46h) (r/w) it states the histogram reference blue color in histogram mode. d7-0 hist_ b[7:0] sync processor control (address 48h) (r/w) d7-2 reserved d1-0 sync source 00: from h/v sync 01: from cvsync (composite sync) 1x: auto switch to cvsync when cvsync is present, but vsync not. auto position control (address 49h) (r/w) d7-2 reserved d1 auto position burst mode enable 0: single mode 1: burst mode d0 auto position enable (w) 0: disable 1: enable auto position ready flag (r) 0: ready 1: not ready auto position reference color - red (address 4ah) (r/w) it defines the red component color for selecting between black and non-black pixels. d7-0 ref_color_ red[7:0] auto position reference color - green (address 4bh) (r/w) it defines the green component color for selecting between black and non-black pixels. d7-0 ref_color_ green[7:0] auto position reference color - blue (address 4ch) (r/w)
myson technology MTL005 rev 0.9 revision 0.9 - 29 - 2000/12/29 it defines the blue component color for selecting between black and non-black pixels. d7-0 ref_color_ blue[7:0] clamp pulse control 0 (address 4eh) (r/w) d7 clamp pulse mask 0: normal 1: mask out clamp pulse d6 clamp pulse start reference edge 0: from input hsync trailing edge. 1: from input hsync leading edge. d5 clamp pulse output polarity 0: active high 1: active low d4-0 clamp pulse start start of clamp pulse after the selected edge of input hsync by input dclk. clamp pulse control 1 (address 4fh) (r/w) d7 clock source for clamp pulse generation 0: from input clock, idclk 1: from osc clock, refclk d6-5 reserved d4-0 clamp pulse width to adjust clamp pulse width by input dclk. input vs period count by refclk - low (address 50h) (ro) it states the low byte of the number of refclk of the vertical sync period measurement. d7-0 vsprd[7:0] input vs period count by refclk - high (address 51h) (ro) it states the high byte of the number of refclk of the vertical sync period measurement. d7-4 reserved d3-0 vsprd[11:8] input v back porch count by input hs - low (address 52h) (ro) it states the low byte of the number of lines between the end of vsync and the active image. d7-0 vbpw[7:0] input v back porch count by input hs - high (address 53h) (ro) it states the high byte of the number of lines between the end of vsync and the active image
myson technology MTL005 rev 0.9 revision 0.9 - 30 - 2000/12/29 d7-3 reserved d2-0 vbpw[10:8] input v active image count by input hs - low (address 54h) (ro) it states the low byte of the number of the active image lines. d7-0 vactw[7:0] input v active image count by input hs - high (address 55h) (ro) it states the high byte of the number of the active image lines d7-3 reserved d2-0 vactw[10:8] input v total image count by input hs - low (address 56h) (ro) it states the low byte of the number of the total image lines. d7-0 vtotw[7:0] input v total image count by input hs - high (address 57h) (ro) it states the high byte of the number of the total image lines. d7-3 reserved d2-0 vtotw[10:8] input hs period count by refclk - low (address 58h) (ro) it states the low byte of the number of refclks of the horizontal sync period measurement. d7-0 hsprd[7:0] input hs period count by refclk - high (address 59h) (ro) it states the high byte of the number of refclks of the horizontal sync period measurement. d7-5 reserved d4-0 hsprd[12:8] input h back porch count by input pixel clock -low (address 5ah) (ro) it states the low byte of the number of pixels between the end of hsync and the active image. d7-0 hbpw[7:0] input h back porch count by input pixel clock -high (address 5bh) (ro) it states the high byte of the number of pixels between the end of hsync and the active image.
myson technology MTL005 rev 0.9 revision 0.9 - 31 - 2000/12/29 d7-3 reserved d2-0 hbpw[10:8] input h active image count by input pixel clock-low(address 5ch) (ro) it states the low byte of the number of the horizontal active image pixels. d7-0 hactw[7:0] input h active image count by input pixel clock-high(address 5dh)(ro) it states the high byte of the number of the horizontal active image pixels. d7-3 reserved d2-0 hactw[10:8] input h total image count by input pixel clock- low (address 5eh) (ro) it states the low byte of the number of the horizontal total image pixels. d7-0 htotw[7:0] input h total image count by input pixel clock- high (address 5fh) (ro) it states the high byte of the number of the horizontal total image pixels. d7-3 reserved d2-0 htotw[10:8] display vertical total - low (address 60h) (r/w) it defines the low byte of the number of lines per display frame. d7-0 dv_ total[7:0] display vertical total - high (address 61h) (r/w) it defines the high byte of the number of lines per display frame. d7-3 reserved d2-0 dv_ total[10:8] display vertical sync end - low (address 62h) (r/w) it defines the low byte of vertical sync end position in lines. d7-0 dv_sync_ end[7:0] display vertical sync end - high (address 63h) (r/w) it defines the high byte of vertical sync end position in lines.
myson technology MTL005 rev 0.9 revision 0.9 - 32 - 2000/12/29 d7-3 reserved d2-0 dv_sync_ end[10:8] note: display vertical sync start is always equal 0. display vertical active start - low (address 64h) (r/w) it defines the low byte of vertical active region start position in lines. d7-0 dv_act_ start[7:0] display vertical active start - high (address 65h) (r/w) it defines the high byte of vertical active region start position in lines. d7-3 reserved d2-0 dv_act_ start[10:8] display vertical active end - low (address 66h) (r/w) it defines the low byte of vertical active region end position in lines. d7-0 dv_act_ end[7:0] display vertical active end - high (address 67h) (r/w) it defines the high byte of vertical active region end position in lines. d7-3 reserved d2-0 dv_act_ end[10:8] display horizontal total - low (address 70h) (r/w) it defines the low byte of the number of display clock cycles per display line. d7-0 dh_ total[7:0] display horizontal total - high (address 71h) (r/w) it defines the high byte of the number of display clock cycles per display line. d7-3 reserved d2-0 dh_ total[10:8] display horizontal sync end - low (address 72h) (r/w) it defines the low byte of horizontal sync end position in display clock cycles. d7-0 dh_sync_ end[7:0] display horizontal sync end - high (address 73h) (r/w)
myson technology MTL005 rev 0.9 revision 0.9 - 33 - 2000/12/29 it defines the high byte of horizontal sync end position in display clock cycles. d7-3 reserved d2-0 dh_sync_ end[10:8] note: display horizontal sync start is always equal 0. display horizontal active start - low (address 74h) (r/w) it defines the low byte of horizontal active region start position in display clock cycles. d7-0 dh_act_ start[7:0] display horizontal active start - high (address 75h) (r/w) it defines the high byte of horizontal active region start position in display clock cycles. d7-3 reserved d2-0 dh_act_ start[10:8] display horizontal active end - low (address 76h) (r/w) it defines the low byte of horizontal active region end position in display clock cycles. d7-0 dh_act_ end[7:0] display horizontal active end - high (address 77h) (r/w) it defines the high byte of horizontal active region end position in display clock cycles. d7-3 reserved d2-0 dh_act_ end[10:8] nfb timing control (address 7fh) it defines the nfb timing setting and high byte of nfb horizontal counter load value. d7 free running mode select 0: normal 1: free running d6-4 nfb synchronization mode 000: delay mode. output hsync trimmed in output vsync and vde issued on next hsync when lock event occurs. 010: immediate mode. output hsync trimmed immediately and vde issued on next hsync when lock event occurs. 110: early mode. output hsync trimmed immediately and vde issued immediately when lock event occurs. d3-0 reserved output image control register 0 (address 88h) (r/w)
myson technology MTL005 rev 0.9 revision 0.9 - 34 - 2000/12/29 d7-5 reserved d4 output port msb / lsb change 0: no exchange 1: exchange d3 reserved d2 output pixel 18 bit rgb mode select 0: 24 bit rgb 1: 18 bit rgb d1 output dual pixel data exchange 0: normal 1: exchange d0 output dual pixel select 0: dual pixel 1: single pixel output image control register 1 (address 89h) (r/w) d7-6 reserved d5 rgb brightness control enable 0: disable 1: enable d4 rgb gain control enable 0: disable 1: enable d3-1 reserved d0 output blank screen 0: normal 1: output pixel masked as black color output image control register 2 (address 8ah) (r/w) d7 reserved d6 temporal dithering enable 0: static dithering 1: temporal dithering d5 reserved d4 dithering enable 0: disable 1: enable d3 color gain control resolution select 0: 8-bit resolution 1: 9-bit reso lution
myson technology MTL005 rev 0.9 revision 0.9 - 35 - 2000/12/29 d2 reserved d1 gamma table r/w access enable 0: disable 1: enable d0 gamma correction function 0: off 1: on color gain control - red (address 90h) (r/w) it can be used to adjust the gain of red component of the display image. d7-0 rgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - green (address 91h) (r/w) it can be used to adjust the gain of green component of the display image. d7-0 ggain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - blue (address 92h) (r/w) it can be used to adjust the gain of blue component of the display image. d7-0 bgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color brightness control - red (address 93h) (r/w) it can be used to adjust the brightness of red component of the display image. d7-0 rbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) color brightness control - green (address 94h) (r/w) it can be used to adjust the brightness of green component of the display image. d7-0 gbright[7:0] -128 (80h) ~ 0(00h) ~127(7fh) color brightness control - blue (address 95h) (r/w) it can be used to adjust the brightness of blue component of the display image. d7-0 bbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) gamma table data port (address 9fh) (r/w) since the gamma table is downloadable, this data port is the entry address.
myson technology MTL005 rev 0.9 revision 0.9 - 36 - 2000/12/29 d7-0 gamma_ port[7:0] osd control registers 0 (address a0h) (r/w) d7 osd output clock select 0: from internal display dot clock 1: from internal display dot clock x 2 d6 osd output vs invert 0: normal 1: invert d5-4 reserved d3 osd function 0: off 1: on d2 reserved d1-0 osd type select 00: osdrgb = { r 0000000, g 0000000, b 0000000} 01: osdrgb = { rr 000000, gg 000000, bb 000000} 10: osdrgb = { rrrr 0000, gggg 0000, bbbb 0000} 11: osdrgb = { rrrrrrrr , gggggggg , bbbbbbbb } r = osdr, g = osdg, b = osdb osd control register 1 (address a1h) (r/w) d7 osd output hs invert 0: normal 1: invert. d6 osd output dclk invert 0: normal 1: invert. d5-4 osd output hs d elay 4 steps to change, each of them is 1ns delay/step. d3 osd input data sample clock invert 0: normal. 1: invert. d2-0 osd input data sample clock delay 8 steps to change, each of them is 1ns delay/step. osd control register 2 (address a2h) (r/w) d7-4 reserved d3-0 osd output clock delay 16 steps to change, each of them is 1ns delay/step. output invert control (address a4h) (r/w)
myson technology MTL005 rev 0.9 revision 0.9 - 37 - 2000/12/29 d7 reserved d6 rgb data invert enable 0: disable 1: enable d5 display dclkh invert 0: normal 1: invert d4 display dclk invert 0: normal 1: invert d3 reserved d2 display data enable (dden) invert 0: normal 1: invert d1 display vsync invert 0: normal 1: invert d0 display hsync invert 0: normal 1: invert output tri_state control (address a5h) (r/w) d7 display data r2out, g2out, b2out output disable 0: normal 1: tri_stated d6 display data r1out, g1out, b1out output disable 0: normal 1: tri_stated d5 display dclk 2 output disable 0: normal 1: tri_stated d4 display dclk 1 output disable 0: normal 1: tri_stated d3 osd oclk / ovsync / ohsync output disable 0: normal 1: tri_stated d2 display data enable (dden) output disable 0: normal 1: tri_stated d1 display vsync output disable 0: n ormal
myson technology MTL005 rev 0.9 revision 0.9 - 38 - 2000/12/29 1: tri_stated d0 display hsync output disable 0: normal 1: tri_stated output clocks delay adjustment (address a6h) (r/w) d7-4 display dclkh delay adjustment 16 steps to adjust, typical 1ns delay/step d3-0 display dclk delay adjustmen t 16 steps to adjust, typical 1ns delay/step output clocks duty cycle adjustment (address a7h) (r/w) d7 display dclkh duty cycle increase/decrease 0: decrease 1: increase d6-4 display dclkh duty cycle adjustment 8 steps to adjust, typical 0. 5ns delay/step d3 display dclk duty cycle increase/decrease 0: decrease 1: increase d2-0 display dclk duty cycle adjustment 8 steps to adjust, typical 0.5ns delay/step output miscellaneous control (address a9h) (r/w) d7 second field line buf fer overflow status for interlace input (ro) 0: not overflow 1: overflow d6 second field line buffer underflow status for interlace input (ro) 0: not underflow 1: underflow d5 first field line buffer overflow status for interlace input or l ine buffer overflow status for non-interlace input (ro) 0: not overflow 1: overflow d4 first field line buffer underflow status for interlace input or line buffer overflow status for non-interlace input (ro ) 0: not underflow 1: underflow d3 auto output horizontal total calculation start (w) 0: disable 1: enable auto output horizontal total calculation ready flag (r) 0: ready 1: not ready
myson technology MTL005 rev 0.9 revision 0.9 - 39 - 2000/12/29 d2-0 reserved output vertical active line number - low (address aah) (r/w) it defines the low byte of output vertical active line number -1, only used for getting the values of reg. ach and adh . d7-0 ovde[7:0] output vertical active line number - high (address abh) (r/w) it defines the high byte of output vertical active line number -1, only used for getting the values of reg. ach and adh . d1-0 ovde[9:8] output horizontal total pixel number - low (address ach) (ro) it states the low byte of output horizontal total pixel number. d7-0 ohtot[7:0] output horizontal total pixel number - high (address adh) (ro) it states the high byte of output horizontal total pixel number. d2-0 ohtot[10:8] output horizontal total residue number - low (address aeh) (ro) it states the low byte of output horizontal total pixel residue number. d7-0 ohtot_ res[7:0] output horizontal total residue number - high (address afh) (ro) it states the high byte of output horizontal total pixel residue number. d7-2 reserved d1-0 ohtot_ res[9:8] zoom control register 0 (address b0h) (r/w) d7 res erved d6-4 vertical scale select 0xx: pass mode 10x: duplicate mode 110: bilinear mode 111: interpolation table mode d3 reserved d2-0 horizontal scale select 0xx: pass mode
myson technology MTL005 rev 0.9 revision 0.9 - 40 - 2000/12/29 10x: duplicate mode 110: bilinear mode 111: interpolation ta ble mode zoom control register 1 (address b1h) (r/w) d7-1 reserved d0 interpolation table r/w access enable 0: disable 1: enable zoom vertical scale ratio ? low (address b4h) (r/w) it defines the low byte of vertical scale ratio value for scale up. d7-0 zvsf[7:0] zoom vertical scale ratio - high (address b5h) (r/w) it defines the high byte of vertical scale ratio value for scale up. d7-0 zvsf[15:8] zvsf = ceil[( input_height ? 1)/ ( output_height ? 1)* 2 16 ] zoom horizontal scale ratio - low (address b6h) (r/w) it defines the low byte of horizontal scale ratio value for scale up. d7-0 zhsf[7:0] zoom horizontal scale ratio - high (address b7h) (r/w) it defines the high byte of horizontal scale ratio value for scale up. d7-0 zhsf[15:8] zhsf = ceil[( input_width ? 1)/ ( output_width ? 1)* 2 16 ] interpolation table data port (address bfh) (r/w) it defines the entry address of the interpolation table data port. d7-0 tfport[7:0] host control register 1 (address c1h) (r/w) d7 reserved d6 i2c bus address no increment 0: normal 1: no increment d5 double buffer load select 0: immediately
myson technology MTL005 rev 0.9 revision 0.9 - 41 - 2000/12/29 1: delay to display vsync d4 registers double buffer function enable 0: disable 1: enable d3-2 reserved d1 display reg isters double buffer load (wo) d0 input registers double buffer load (wo) host access mode status (address cbh) (ro) d7-1 reserved d0 host access mode 0: 2-wire serial mode (iic) 1: 8-bit parallel mode clock synthesizer control register (address e0h) (r/w) d7 external display clock selection 0: external display clock 1 1: external display clock 2 d6-3 reserved d2 display clock source 0: internal display clock 1: external reference clock d1 reserved d0 display clock synthe sizer enable 0: enable 1: disable clock synthesizer value load (address e1h) (wo) d7-1 reserved d0 display clock synthesizer value load ( wo) display clock synthesizer n value (address e2h) (r/w) d7-0 display clock synthesizer n value display clock synthesizer m value (address e3h) (r/w) d7-0 display clock synthesizer m value clock synthesizer r value (address e6h) (r/w) d7-2 reserved
myson technology MTL005 rev 0.9 revision 0.9 - 42 - 2000/12/29 d1-0 display clock synthesizer r value 00: no divided 01: divided by 2 1x: divide d by 4 sync interrupt flag control (address e8h) (r) it contains the status of sync interrupts. d7 display vsync pulse interrupt status 0: no display vsync pulse detected 1: any display vsync pulse detected d6 input vsync pulse interrupt status 0: no input vsync pulse detected 1: any input vsync pulse detected d5 vsync presence change status 0: no change 1: change d4 hsync presence change status 0: no change 1: change d3 vsync polarity change status 0: no change 1: change d2 hsync polarity change status 0: no change 1: change d1 vsync frequency change status 0: no change 1: change d0 hsync frequency change status 0: no change 1: change sync interrupt flag control (address e8h) (w) it is used to clear the corresponding sync interrupt signal when software finishes serving the interrupt service routine. d7 clear display vsync pulse interrupt enable 0: disable 1: enable d6 clear input vsync pulse interrupt enable 0: disable 1: enable d5 clear v sync presence change interrupt enable 0: disable
myson technology MTL005 rev 0.9 revision 0.9 - 43 - 2000/12/29 1: enable d4 clear hsync presence change interrupt enable 0: disable 1: enable d3 clear vsync polarity change interrupt enable 0: disable 1: enable d2 clear hsync polarity change interrupt enable 0: disable 1: enable d1 clear vsync frequency change interrupt enable 0: disable 1: enable d0 clear hsync frequency change interrupt enable 0: disable 1: enable general interrupt flag control (address e9h) (r) it contains the status of general interrupts. d7-2 reserved d1 auto position finish status (valid for single mode only) 0: not finish 1: finish d0 auto calibration finish status (valid for single mode only) 0: not finish 1: finish general interrupt flag control (address e9h) (w) it is used to clear the corresponding general interrupt signal when software finishes serving the interrupt service routine. d7-2 reserved d1 clear auto position finish interrupt enable 0: disable 1: enable d0 clear auto c alibration finish interrupt enable 0: disable 1: enable sync interrupt enable control (address eah) (r/w) it is used to enable sync interrupt function. d7 display vsync pulse interrupt enable
myson technology MTL005 rev 0.9 revision 0.9 - 44 - 2000/12/29 0: disable 1: enable d6 input vsync pulse interr upt enable 0: disable 1: enable d5 vsync presence change interrupt enable 0: disable 1: enable d4 hsync presence change interrupt enable 0: disable 1: enable d3 vsync polarity change interrupt enable 0: disable 1: enable d2 hsync po larity change interrupt enable 0: disable 1: enable d1 vsync frequency change interrupt enable 0: disable 1: enable d0 hsync frequency change interrupt enable 0: disable 1: enable general interrupt enable control (address ebh) (r/w) it is used to enable general interrupt functions. d7 interrupt output polarity 0: active high 1: active low d6-2 reserved d1 auto position finish interrupt enable 0: disable 1: enable d0 auto calibration finish interrupt enable 0: disable 1: enable hs frequency change interrupt compare (address ech) (r/w) it is used to control interrupt generation by comparing the frequency change value when input hs frequency changes. d7-0 hscmpreg[7:0]
myson technology MTL005 rev 0.9 revision 0.9 - 45 - 2000/12/29 power management control (address f1h) (r/w) d7 reserved d6 power down gamma & interpolation table 0: normal 1: power down d5 reserved d4 power down line buffers 0: normal 1: power down d3 reserved d2 mask refclk 0: disable 1: enable d1 power down all the clocks except re fclk 0: normal 1: power down d0 software reset enable 0: disable 1: enable
myson technology MTL005 rev 0.9 revision 0.9 - 46 - 2000/12/29 5. electrical characteristics 5.1 dc characteristics table 5.1 recommended operating conditions symbol parameter min typ max unit vcc operation voltage 3.0 3.3 3.6 v tamb operating ambient temperature 0 70 o c tstg storage temperature -55 150 o c table 5.2 dc electrical characteristics for 3.3 v operation symbol parameter conditions min typ max unit vil input low voltage 0.8 v vih input high voltage 2.0 v vt- input schmitt trigger low voltage at pins sda and sck 1.0 vt+ input schmitt trigger high voltage at pins sda and sck 1.7 vol output low voltage 0.4 v voh output high voltage 2.4 v ri input pull-up/down resistance vil = 0v or vih = vcc 75 kohm ili input leakage current -10 10 ua ilo output leakage current -20 20 ua
myson technology MTL005 rev 0.9 revision 0.9 - 47 - 2000/12/29 5.2 ac characteristics input interface timing figure 5.2.1 input interface timing table 5.2.1 input interface timing symbol parameter min max unit tids input image signal setup time for ipclk 2 ns tidh input image signal hold time for ipclk 3 ns tivhs input vsync/hsync setup time for ipclk 2 ns tivhh input vsync/hsync hold time for ipclk 3 ns output interface timing figure 5.2.2 output interface timing tids tidh tivhh tivhs ipclk input vs/hs pixin[23:0] tdde tdhs tddp tdvs ddclk display vs pixout1[23:0] / pixout2[23:0] display hs display dden
myson technology MTL005 rev 0.9 revision 0.9 - 48 - 2000/12/29 table 5.2.2 output interface timing symbol parameter min max unit tdvs display vsync output delay to ddclk 2 ns tdhs display hsync output delay to ddclk 0.5 ns tdde display dden output delay to ddclk 1 ns tddp display data output delay to ddclk 1.5 ns note: ddclk phase can be adjusted relative to data and control outputs using the ddclk_inv (reg. a4h/d5-4) and ddclk_ delay[2:0] (reg. a6h/d7-0) programming controls. osd interface timing figure 5.2.3 osd interface timing table 5.2.3 osd interface timing symbol parameter min max unit tosdd osd vs / hs output delay to oclk 2 ns tosds osd signal input setup time for oclk 5.5 ns tosdh osd signal input hold time for oclk 0 ns note: oclk phase can be adjusted using oclk_inv (reg. a1h/d3) programming control and ohsync phase can be adjusted using ohsync_delay[1:0] (reg. a1h/d5-4) programming control. tosdd tosds tosdh oclk input osdden / osdred / osdgrn / osdblu ovsync / ohsync
myson technology MTL005 rev 0.9 revision 0.9 - 49 - 2000/12/29 i2c host interface timing figure 5.2.4 i2c host interface timing table 5.2.4 i2c host interface timing symbol parameter min max unit thigh clock high period 500 ns tlow clock low period 500 ns tsu:dat data in setup time 200 ns thd:dat data in hold time 100 ns tsu:sta start condition setup time 500 ns thd:sta start condition hold time 500 ns tsu:sto stop condition setup time 500 ns thd:sto stop condition hold time 500 ns tsu :dat thd :dat tsu :sta thd :sto tsu :sto thd :sta tlow thigh
myson technology MTL005 rev 0.9 revision 0.9 - 50 - 2000/12/29 6. package dimension 128 qfp a1 stand-off a2 body thickness l1 lead length b lead width c lead thickness e lead pitch (all units are in mm) body size d1 e1 lead count a1 a2 l1 b c e 14 20 128 0.25 2.72 1.6 0.2 0.15 0.5

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