fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 features ? 1024 x 1 photosite array ? 13 m x 13 m photosites on 13 m pitch ? anti-blooming and integration control ? enhanced spectral response (particularly in the blue region) ? improved low-light performance over ccd133a ? low dark signal ? high responsivity ? high-speed operation ? on-chip clock drivers ? dynamic range typical: 7500:1 ? over 1v peak -to-peak outputs ? dark and white references contained in sample- and -held outputs ? special selections available ?consult factory ccd 134 1024-element linear image sensor general description the CCD134 is a 1024-element line image sensor designed for industrial measurement, telecine, and document scanning applications which require high resolution, high sensitivity and high data rate. the in- corporation of on-chip antiblooming and integration control allow the CCD134 to be extremely useful in an industrial measurement and control environment or en- vironments where lighting conditions are difficult to control. .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 2 CCD134 the CCD134 is similar to the ccd133a except for the additional features of anti-blooming and integration control. the CCD134 is a third generation device having an overall improved performance compared with first and second generation devices, including en- hanced blue response and excellent low light level performance. the device incorporates on-chip clock driver circuitry and is capable of high-speed operation up to a 20mhz data rate. the photoelement size is 13 m (0.51 mils) x 13 m (0.51 mils) on 13 m (0.51 mils) centers. the device is manufactured using fairchild weston ad- vanced charge-coupled device n-channel isoplanar buried-channel technology. functional description the CCD134 consists of the following functional elements illustrated in the block diagram and circuit diagram (fig1.). photosites ? a row of 1024 image sensor elements separated by a diffused channel stop and covered by a silicon dioxide surface passivation layer. image photons pass through the transparent sili- con creating hole-electron pairs. the photon generated electrons are accumulated in the photosites. the amount of charge accumu- lated in each photosite is a linear function of the incident illumination intensity and the integration period. the output signal will vary in an analog manner from a thermally generated background level at zero illumination to a maximum at saturation under bright illumination. transfer gates ? this gate is a structure adjacent to the row of image sensor elements. the charge packets accumulated in the photosites are transferred in parallel via the transfer gate to the trans- port shift registers whenever the transfer gate voltage goes high. alternate charge packets are transferred to the a and b transport registers. four 529 bit analog transport shift registers ? two reg- isters are on each side of the line of image sensor elements and are separated from it by the transfer gate. the two inside registers, called the transport shift registers are used to move the light gener- ated charge packets delivered by the transfer gates serially to the charge detector amplifier. the complementary phase relationship of the last elements of the two transport registers provides for alter- nate delivery of charge packets at the output amplifiers. the outer fig. 1 block diagram two registers serve to reduce peripheral electron noise in the inner shift registers. two gated charge detector/amplifiers ? charge packets are transported to a precharged capacitor whose potential changes linearly in response to the quantity of the signal charge delivered. this potential is applied to the input gate of the two-stage nmos amplifiers producing a signal at the output ?v out pins. the sample- and-hold gate is a switching mos transistor in the output amplifier that allows the output to be delivered as a sample-and held wave- form. the diode is recharged internally before the arrival of each new signal charge-packet from the transport shift register. integration and anti-blooming control ? in many applica- tions the dynamic range in parts of the image is larger than the dy- namic range of the ccd, which may cause more electrons to be generated in the photosite area than can be stored in the ccd shift register. this is particularly common in industrial inspection and sat- ellite applications. the excess electrons generated by bright illumi- nation tend to ?bloom? or ?spill over? to neighboring pixels along the shift register, thus ?smearing? the information. this smearing can be eliminated using two methods: anti-blooming operation: a dc voltage applied to the integration control gate (approximately 5 to 7 volts) will cause excess charge generated in the photosites to be diverted to the anti-blooming sink (v sink ) instead of the shift regis- ters. this acts as a ?clipping circuit? for the ccd output (see fig. 2) integration control operation: variable integration times which are less than the ccd exposure time may be attained by supplying a clock to the integration control gate. clocking ic reduces the photosite signal in all photosites by the ra- tion t exposure / t int . greater than 10:1 reduction in the average photosite signal can be achieved with integration control. the integration-control and anti-blooming features can be imple- mented simultaneously. this is done by setting the ic clock-low level to approximately 5 to 7 volts. .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 3 CCD134 fig. 2 integration-control timing diagram and notes fig. 3 test load configuration (internal sample-and-hold enabled) fig. 4 test load configuration (internal sample-and-hold disabled) fig. 5 maximum output voltage vs. ic voltage .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 CCD134 4 package outline 24- pin dual in-line ceramic package definition of term charge-coupled device ? a charge-coupled device is a semi- conductor device in which finite isolated charge-packets are trans- ported from one position in the semiconductor to an adjacent posi- tion by sequential clocking of an array of gates. the charge-packets are minority carriers with respect to the semiconductor substrate. sample-and hold clock ( shca , shcb ) - the voltage wave form for triggering the sample-and-hold gates in the output amplifiers to create a continuous sampled video signal at the output. the sample- and-hold feature may be defeated by connecting shca and shcb to v dd . use of the internal sample-and-hold capability is possible for data rates upt to 13mhz. for use above 13mhz consult factory. dark reference ? video output level generated from sensing elements covered with opague metalization which provides a refer- ence voltage equivalent to device operation in the dark. this per- mits use of external dc restoration circuitry. isolation cell ? this is a site on-chip producing an element in the video output that serves as a buffer between valid video data and dark reference signals. the output from an isolation cell contains no valid information and should be ignored. dynamic range ? the saturation exposure divided by the rms temporal noise equivalent exposure., dynamic range is sometimes defined in terms of peak-to-peak noise. to compare the two defini- tions a factor of four to six is generally appropriate in that peak-to- peak noise is approximately equal to four to six times rms noise. rms noise equivalent exposure ? the exposure level that gives an output signal equal to the rms noise level at the output in the dark. saturation exposures ? the minimum exposure level that will provide a saturation output signal. exposure is equal to the light intensity times the photosite integration time. charge transfer efficiency ? percentage of valid charge in- formation that is transferred between each successive stage of the transport registers. responsivity ? the output signal voltage per unit exposure for a specified spectral type of radiation. responsivity equals output volt- age divided by exposure. total photoresponse non-uniformity - the difference of the response levels of the most and the least sensitive element under uniform illumination. measurement of prnu excludes first and last elements. dark signal - the output signal in the dark caused by thermally generated electrons that is a linear function of the integration time and is highly sensitive to temperature. saturation output voltage - the maximum usable signal out- put voltage. charge transfer efficiency decreases sharply when the saturation output voltage is exceeded. integration time - the time interval between the falling edge of the integration control clock and the falling edge of the transfer clock. the integration time is the time in which charge is accumulated in the photosites. exposure time - the time interval between the falling edge of the two transfer pulses ( x ) as shown in the timing diagram. the expo- sure time is the time between transfers of signal charge from the photosites into the transport registers. pixel - a picture element (photosite). .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 5 CCD134 .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 6 CCD134 .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 7 CCD134 typical performance curves .com .com .com .com 4 .com u datasheet
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 8 CCD134 timing diagram (internal sample & hold enabled, see fig. 5) timing details between t and v out a and v out b (near pixel #1) general notes: 1. white reference cell output signals will be approximately equal in height. this output can be reduced by connecting v ei to v dd . 2. the isolation cells may contain output signals as part of their buffer function. these signals should be disregarded. 3. integration control clock ( ic ) omitted for clarity. refer to ?integration control clock timing diagram? (figure 3) for details. .com .com .com 4 .com u datasheet
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