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www.fairchildsemi.com features 30 msps conversion rate, 15 mhz analog bandwidth 9-bit resolution and linearity sample-and-hold circuit not required differential phase 0.5 degrees differential gain 1.0% over?w ?g single -5.2v power supply differential ecl outputs available in a 64-pin dip, 68-contact lcc and 68-pin ceramic pin grid array applications video data conversion radar data conversion high-speed data acquisition description the TDC1049 is a ?sh (full-parallel) analog-to-digital converter capable of converting analog signals with full- power frequency components up to 15 mhz into 9-bit words at rates up to 30 msps (megasamples per second). a sample-and-hold circuit is not required. all digital inputs and outputs are differential ecl. the TDC1049 consists of 512 latching comparators, encod- ing logic and an output register. a differential convert signal controls the conversion operation. the outputs can be connected to give either true or inverted binary or offset twos complement fommats. block diagram 0 1 2 255 256 511 v in conv conv r t r ts r m r bs r b r 2 r/2 r r r r/2 r/2 r/2 r/2 r/2 r 4 differential comparators (512) 512 to 9 encoder latch 2 18 ovf, ovf d 1-9 d 1-9 r mid r 5 r 3 r 1 ofs 65-1049-01 TDC1049 high-speed a/d converter 9-bit, 30 msps rev. 1.0.0
TDC1049 product specification 2 functional description general inf ormation the TDC1049 has three functional sections: a comparator array , encoding logic and output re gister . the comparator array compares the input signal with 512 reference v oltages to produce an n- of- 512 code or ?hermometer?code. the comparators referenced to v oltages less than the input signal will be on and those referenced to v oltages greater than the input signal will be of f. the encoding logic con v erts the n- of- 512 code into 9- bit binary data. the output re gister holds the output between updates. p o wer f or optimum performance, separate analog and digital po wer , v eea and v eed should be supplied to the TDC1049. separate analog and digital po wer supplies or a common supply with separate analog and digital paths and high- frequenc y decoupling can be used. the return path for the current dra wn from v eea and v eed is a gnd and d gnd , respecti v ely . the returns a gnd and d gnd should also be k ept separate and connected together at the po wer supply terminals. it is recommended that pro visions be made on the printed circuit board for shorting jumpers between analog and digital ground as close to the a/d con v erter as possible. the installation of the jumpers depends upon the printed circuit board layout and o v erall system performance once the system is in operation. the v oltage dif ference between v eea and v eed must be less than +0.1v . the same v oltage dif ference limit applies to the dif ference between a gnd and d gnd . all po wer and ground inputs to the con v erter must be connected. ref erence the TDC1049 con v erts analog signals in the range v rb < v in < v r t into digital form. v rb (the v oltage applied to r b ) at the bottom of the reference resistor chain, and v r t (the v oltage applied to r t ) at the top of the refer - ence resistor chain, should both be between +0.1v and - 2.1v . w ithin that range, v r t must be more positi v e than v rb . the linearity speci cation is based upon a 2.0v dif fer - ence between v r t and v rb . the nominal v oltages are v r t = 0.0v and v rb = - 20v . t o a v oid damage to the con- v erter , the v oltage across v r t and v rb must not e xceed 2.2v . a decoupling capacitor is recommended between r b and a gnd . noise introduced at this point, as well as the other reference inputs (r t , r ts , r m , r bs , ofs), may result in encoding errors. a midpoint tap, r m , allo ws the con v erter to be adjusted for optimum inte gral linearity . it can also be used to achie v e a nonlinear transfer function, b ut adjustment of r m is not required to meet 9-bit linearity . if this node is dri v en by e xternal circuitry , it should be dri v en from a lo w- impedance source; if not used, it must be left open. p arasitic resistances, r1 and r2, introduce of fset errors at the top and bottom of the reference resistor chain. sense points, r ts , r bs and ofs, may be used to reduce the ef fect of these of fset errors. ov er o w sense (ofs) may be used to reduce the ef fect of the of fset at the o v er o w (most positi v e) comparator whene v er the ov er o w (o vf , o vf ) ags are used. sense points are not required for 9- bit linearity and, if not used, the y must be left open. con ver t the TDC1049 requires a dif ferential ecl clock (conv and conv ) signal. the con v ersion occurs (the comparators are latched) within t st o (sampling t ime of fset) of the rising edge of conv . the 512 to 9 encoding is performed on the f alling edge of the conv signal. the coded result is trans- ferred to the output re gister on the ne xt rising edge of conv . data for sample n is a v ailable at the output t d (output delay t ime) after the rising edge of sample n+1. analog input the TDC1049 uses latching comparators which are con- nected to the analog inputs v in . f or optimal performance, the source impedance of the dri v er ampli er should be less than 25 w . the input signal will not damage the TDC1049 if it remains within the range of v eea to +0.5v . if the input signal is between the v r t and v rb , the output will be a binary number between 0 and 511 inclusi v e. all v e analog inputs must be connected. outputs the outputs of the TDC1049 are dif ferential ecl. the rec- ommended pull- do wn resistance is 500 w to - 2v , or a 220/330 w termination between d gnd and v eed . the o vf signal indicates that the analog input has e xceeded the threshold of the most positi v e comparator . data is held v alid at the output re gister for at least t ho (output hold t ime) after the rising edge of conv . ne w data becomes v alid t d after the rising edge of conv . no connects there are se v eral pins labeled nc (no connect). these pins are not connected internally and may be either left open or connected to analog ground to aid heat transfer from the package and to reduce electrical noise.
product specification TDC1049 3 pin assignments 64 lead sidebraz ed ceramic dip 64 lead bottombraz e ceramic dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d 8 d 7 d 7 d 6 d 6 d 5 d 5 a gnd nc nc v eed nc nc v eea nc nc pin name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v eea nc v eea nc nc v eed nc nc a gnd nc nc d 4 d 4 d 3 d 3 d 2 pin name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 d 2 d 1 (msb) d 1 (msb) ovf ovf d gnd d gnd r bs r b nc v in nc a gnd a gnd v in r m pin name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 v in v in a gnd a gnd v in nc r t ofs r ts d gnd conv conv d gnd d 9 (lsb) d 9 (lsb) d 8 pin name 65-1049-02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d 8 d 9 (lsb) d 9 (lsb) d gnd conv conv d gnd r ts ofs r t nc v in a gnd a gnd v in v in pin name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 r m v in a gnd a gnd nc v in nc r b r bs d gnd d gnd ovf ovf d 1 (msb) d 1 (msb) d 2 pin name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 d 2 d 3 d 3 d 4 d 4 nc nc a gnd nc nc v eed nc nc v eea nc v eea pin name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc v eea nc nc v eed nc nc a gnd d 5 d 5 d 6 d 6 d 7 d 7 d 8 pin name 65-1049-03
TDC1049 product specification 4 pin assignments (contin ued) 68 lead lcc 68 lead ceramic pin grid arra y 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d 8 d 7 d 7 d 6 d 6 d 5 d 5 nc a gnd nc nc nc v eed v eea nc v eea nc pin name 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 v eea nc v eea v eea v eed nc nc nc nc a gnd nc nc nc d 4 d 4 d 3 d 3 pin name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 d 2 d 2 d 1 (msb) d 1 (msb) ovf ovf d gnd nc r bs r b nc v in nc a gnd a gnd v in nc pin name 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 r m v in v in a gnd nc a gnd v in r t nc ofs r ts conv conv d gnd d 9 (lsb) d 9 (lsb) d 8 pin name 65-1049-04 11 10 9 8 7 6 5 4 3 2 1 l k j bo tt om view or ientation pin h g f e d c b a a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 nc v eed nc nc nc nc nc nc v eed nc a gnd v eea nc v eea v eea v eea nc pin name b9 b10 b11 c1 c2 c10 c11 d1 d2 d10 d11 e1 e2 e10 e11 f1 f2 v eea nc a gnd nc nc d 5 nc d 4 d 4 d 6 d 5 d 3 d 3 d 7 d 6 d 2 d 2 pin name f10 f11 g1 g2 g10 g11 h1 h2 h10 h11 j1 j2 j10 j11 k1 k2 k3 d 8 d 7 d 1 (msb) d 1 (msb) d 9 (lsb) d 8 ovf ovf d gnd d 9 (lsb) nc d gnd conv d gnd r bs r b v in pin name k4 k5 k6 k7 k8 k9 k10 k11 l2 l3 l4 l5 l6 l7 l8 l9 l10 a gnd v in v in nc a gnd v in r ts conv nc nc a gnd r m nc v in a gnd r t ofs pin name 65-1049-05
product specification TDC1049 5 pin de nitions pin name pin number v alue pin function description bottom- braz ed dip sidebraz ed dip lcc pga v eea 46, 48, 51 14,17,19 14, 16, 18, 20, 21 b9, b7, b6, b5 - 5.2v analog supply voltage v eed 43, 54 11, 22 13, 22 a3, a10 - 5.2v digital supply voltage d gnd 4, 7, 26, 27 38, 39, 58, 61 41, 65 j2, j11, h10 0.0v digital ground a gnd 13, 14, 19, 20, 40, 57 8, 25, 45, 46, 51, 52 9, 27, 48, 49, 55, 57 b2, k4, l4, k8, l8, 0.0v analog ground r t 10 55 59 l9 0.0v reterence resistor, top r ts 8 57 62 k10 0.0v reference resistor, top sense r b 24 41 44 k2 - 2.0v reference resistor, bottom r bs 25 40 43 k1 - 2 0v reference resistor, bottom sense r m 17 48 52 l5 - 1.0v reference resistor, midpoint ofs 9 56 61 l10 0.0v overflow sense conv 5 60 64 j10 ecl convert conv 6 59 63 k11 ecl convert, complement v in 12, 15, 16, 18, 22 43, 47, 49, 50, 53 46, 50, 53, 54, 58 k3, k5, k6, l7, k9 0v to - 2v analog signal input d 1 msb 30 35 38 g1 ecl most significant bit d 2 ? 8 32, 34, 36, 58, 60, 62, 64 33, 31, 29, 7, 5, 3, 1 36, 34, 7, 5, 3, 1 f1, e1, d1, c10, d10, e10, f10 ecl d 9 lsb 2 63 67 g10 ecl least significant bit d 1 msb 31 34 37 g2 ecl most significant bit complement d 2 d 8 33, 35, 37, 59, 61, 63, 1 32, 30, 28, 6, 4, 2, 64 35, 33, 31, 6, 4, 2, 68 f2, e2, d2, d11, e11, f11, g11 ecl d 9 lsb 3 62 66 h11 ecl least significant bit complement ovf 28 37 40 h2 ecl ovedlow output ovf 29 36 39 h1 ecl overflow output complement nc 11, 21, 23, 38, 39, 41, 42, 44, 45, 47, 49, 50, 52, 53, 55, 56 9, 10, 12, 13, 15,16, 18, 20, 21, 23, 24, 26, 27, 42, 44, 54 8, 10, 11, 12, 15, 17, 19, 23, 24, 25, 26, 28, 29, 30, 42, 45, 47, 51, 56, 60 b1, c2, c1, j1, l2, l3, l6, k7, c11, b10, a9, b8, a8, a7, a6, a5, b4, a4, a2 open no connect
TDC1049 product specification 6 absolute maxim um ratings (be y ond which the de vice ma y be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range. operating conditions note: 1. v rt must be more postive than v rb , and the voltage reference differential must be within the specified range. p arameter min. max. unit suppl y v olta g es v eed (measured to d gnd ) - 7.0 +0.5 v v eea (measured to a gnd ) 7.0 +0.5 v a gnd (measured to d gnd ) - 1.0 +1.0 v v eea (measured to v eed ) - 0.5 +0.5 v input v olta g es 2 conv, conv (measured to d gnd ) +0.5 v ee v v in , v rt , v rb (measured to a gnd ) +0.5 v ee v v rt (measured to v rb ) - 2.5 +2.5 v output short- circuit duration (single output in high state to ground) in nite t emperature operating, case - 60 +140 c junction +175 c lead, soldering (10 seconds) 300 c storage - 65 +150 c p arameter t emperature rang e units standar d extended min. nom. max. min. nom. max. v eed digital supply voltage (measured to d gnd ) - 4.9 - 5.2 - 5.5 - 4.9 - 5.2 - 5.5 v v eea analog supply voltage (measured to a gnd ) - 4.9 - 5.2 - 5.5 - 4.9 - 5.2 - 5.5 v v agnd analog ground voltage (measured to d gnd ) - 0.1 0.0 +0.1 - 0.1 0.0 +0.1 v v eea - v eed supply voltage differential - 0.1 0.0 +0.1 - 0.1 0.0 +0.1 v t pwl conv pulse width, ldw 12 12 ns t pwh conv pulse width, high 15 15 ns v lcm input voltage, common mode - 0.5 - 2.5 - 0.5 - 2.5 v v ldf input voltage, differential 0.3 1.2 0.3 1.2 v v in input voltage range v rb v r t v rb v r t v v rt most positive reference inputs 1 - 0.1 0.0 0.1 - 0.1 0.0 +0.1 v v rb most negative reference input 1 - 1.9 - 2.0 - 2.1 - 1.9 -2.0 - 2.1 v v rt - v rb voltage reference differential 1.8 2.0 2.2 1.8 2.0 2.2 v t a ambient temperature, still air 0 70 c t c case temperature - 55 125 c
product specification TDC1049 7 dc electrical characteristics note: 1. test load = 500 w to - 2v on each output. a c electrical characteristics note: 1. test load = 500 w to - 2v on each output, c load = 20pf. timing dia grams figure 1. timing diagram p arameter t est conditions t emperature rang e units standar d extended min. max. min. max. i ee supply current v eed , v eea = max t a = 0 c to 70 c - 950 ma t a = 70 c - 750 ma i c = - 55 c to 125 c - 1090 ma t c = 125 c - 750 ma i ref reference current v rt , v rb = nom 10 36 10 36 ma r ref total reference resistance 56 200 56 200 w r in input equivalent resistance v rt , v rb = nom, v in = v rb 16 16 k w c in analog input capacitance v rt , v rb = nom, v in = v rb 160 160 pf i cb inpul constant bias current v eea = max, v in = 0v 500 750 m a i i input current, conv, conv v eed = max, v l = - 0.7v 150 180 m a v ol output voltage, logic low 1 v eed = nom - 1.6 - 1.5 v v oh output voltage, logic high 1 v eed = nom - 0.95 - 1.1 v c l digital input capacitance t a = 25 c, f = 1mhz 20 20 pf p arameter t est conditions t emperature rang e units standar d extended min. max. min. max. f s maximum conversion rate v eed , v eea = min 30 30 msps t sto sampling time offset v eed , v eea = min - 2 6 - 2 6 ns t d output delay 1 v eed , v eea = min 27 27 ns t ho output hold time 1 v eed , v eea = min 3 3 ns t pwh t sto t ho t d sample n conv conv analog input digital output sample n+1 data n-1 data n+1 data n sample n+2 t pwh 1 f s 65-1049-06
TDC1049 product specification 8 timing dia grams (contin ued) figure 2. convert, conv ert switching levels system p erf ormance characteristics p arameter t est conditions t emperature rang e units standar d extended min. max. min. max. e li linearity error integral, independent v rt , v rb = nom 0.15 0.20 % v rt , v rb = nom, v rm adjusted 0.10 0.10 % e ld linearity error differential v rt , v rb = nom 0.1 0.1 % q code size v rt , v rb = nom 15 185 15 185 % nominal e ots offset error, top v in = v rt , r ts connected 4 4 mv e ot offset error, top v in = v rt 30 30 mv e obs offset error, bottom v in = v rb , r bs connected 4 4 mv e ob offset error, bottom v in = v rb -30 -30 mv t co offset error, temperature coefficient 20 20 m v/ c t tr transient response, full- scale 20 20 ns bw bandwidth, full power input 0.9db frequency response 15 15 mhz snr signal- to- noise ratio 30msps conversion rate, 10mhz bandwidth peak signal/rms noise 1.25mhz input 57 57 db 5.0mhz input 53 53 db rms signal/rms noise 1.25mhz input 48 48 db 5.0mhz input 44 44 db e ap aperture error 50 50 ps dp differential phase error f s = 4 x ntsc 0.5 0.5 degree dg differential gain error f s = 4 x ntsc 1.5 1.5 % v idf v icm min v icm max 0.0v -1.3v conv conv 65-1049-07
product specification TDC1049 9 t ypical p erf ormance cur ves figure 3. power supply current vs. temperature figure 4. snr vs. analog input frequency equiv alent cir cuits figure 5. simplified analog input equivalent circuits figure 6. digital input equivalent circuit figure 7. output circuits -55 -25 0 25 case temperature ( c) power supply current vs. temperature power supply current (ma) 50 75 100 125 -850 -800 -750 -700 -650 -600 -550 -500 -450 65-1049-08 analog input frequency (mhz) snr vs. analog input frequency rms signal noise snr (db) 1.248 2.438 3.58 5 0 10 20 30 40 50 60 6 7 8 9 10 11 12 13 14 15 65-1049-09 v in v eea v eea v in c in c in is a nonlinear junction capacitance v rb is a voltage equal to the voltage on pin r b v eea i cb r in v rb reference resistor chain 65-1049-10 v eed d gnd conv conv 65-1049-11 d gnd to output pin v eed d 5k 5k 20pf 500 -2.0v load 1 test load for delay measurements d output equivalent circuit 65-1049-12
TDC1049 product specification 10 output coding t ab le 1 note: 1. voltages are code midpoints. standar d militar y dra wing these de vices are also a v ailable as products manuf actured, tested, and screened in compliance with standard military dra wings (smds). the nearest v endor equi v alent product is sho wn on the back page of this document; ho we v er , the applicable smd is the sole controlling document de ning the smd product. v in o vf d 1 d 9 msb lsb +0.0039v 0.0000v -0.0039v 1 0 0 000000000 000000000 000000001 -0.9980v - 1.0020v - 1.0059v 0 0 0 011111111 100000000 100000001 - 1.9961v - 2.0000v 0 0 111111110 111111111
product specification TDC1049 11 notes:
product specification TDC1049 12 mec hanical dimensions 64 lead sidebraz ed ceramic dip d b2 e b1 e q a l s1 ea s2 c1 note 1 32 33 64 1 a .120 .175 3.05 4.44 symbol inches min. max. min. max. millimeters notes .023 .58 b1 .015 .38 b2 .040 .065 1.02 1.65 d 3.170 3.240 80.52 82.30 .125 .175 3.18 4.45 e q .025 .065 .63 1.65 e .880 .910 14.60 15.48 l .100 bsc 2.54 bsc .900 bsc 22.86 bsc s2 .005 .13 ea s1 .005 .13 c1 .008 .015 .20 .38 7 2 7 6 3 4, 8 5 notes: 1. index area: a notch or a pin one identification mark shall be located adjacent to pin one. the manufacturer's identification shall not be used as pin one identification mark. 2. the minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 32, 33, and 64 only. 3. dimension "q" shall be measured from the seating plane to the base plane. 4. the basic pin spacing is .100 (2.54mm) between centerlines. each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 64. 5. applies to all four corners (leads number 1, 32, 33, and 64). 6. "ea" shall be measured at the centerline of the leads. 7. all leads e increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. sixty-two spaces.
product specification TDC1049 13 mec hanical dimensions (contin ued) 64 lead bottombraz ed ceramic dip d b2 e b1 e q a l s1 ea s2 c1 note 1 32 33 64 1 a .125 .200 3.18 5.08 symbol inches min. max. min. max. millimeters notes .023 .58 b1 .015 .38 b2 .040 .065 1.02 1.65 d 3.110 3.240 80.00 82.30 .125 .175 3.18 4.45 e q .050 .100 1.27 2.54 e .790 .810 20.07 20.57 l .100 bsc 2.54 bsc .900 bsc 22.86 bsc s2 .005 .13 ea s1 .005 .13 c1 .008 .015 .20 .38 7 2 7 6 3 4, 8 5 notes: 1. index area: a notch or a pin one identification mark shall be located adjacent to pin one. the manufacturer's identification shall not be used as pin one identification mark. 2. the minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 32, 33, and 64 only. 3. dimension "q" shall be measured from the seating plane to the base plane. 4. the basic pin spacing is .100 (2.54mm) between centerlines. each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 64. 5. applies to all four corners (leads number 1, 32, 33, and 64). 6. "ea" shall be measured at the centerline of the leads. 7. all leads e increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. sixty-two spaces.
product specification TDC1049 14 mec hanical dimensions (contin ued) 68 lead lcc lid a1 a b1 b3 l3 plane 1 plane 2 detail "a" (j) x 45 index corner detail "a" see note 1 (h) x 45 3 plcs d2 d1 l2 l1 e e d e3 e2 e1 d3 (j) x 45 4 a .082 .110 2.08 2.79 symbol inches min. max. min. max. millimeters notes a1 .071 .093 1.83 2.39 b1 .022 .560 .028 .710 b3 .006 .022 .150 .560 3, 6 3, 6 2 2,5 d1/e1 e j .800 bsc 20.32 bsc l1 .400 bsc 10.16 bsc l2 .050 bsc 1.27 bsc .040 bsc 1.02 bsc .020 bsc .510 bsc 4 4 l3 .003 .015 .080 .380 5 .075 .095 1.91 2.41 .045 .055 1.14 1.40 h nd/ne 17 17 n 68 68 d/e .938 .962 23.82 24.43 d2/e2 4 1 notes: 1. the index feature for terminal 1 identification, optical orientation or handling purposes, shall be within the shaded index areas shown on planes 1 and 2. plane 1 terminal 1 identification may be an extension of the length of the metallized terminal which shall not be wider than the b1 dimension. 2. unless otherwise specified, a minimum clearance of .015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). 3. dimension "a" controls the overall package thickness. the maximum "a" dimension is the package height before being solder dipped. 4. the corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. the index corner shall be clearly unique. 5. dimension "b3" minimum and "l3" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. dimension "b3" maximum and "l3" maximum define the maximum width and depth of the castellation at any point on its surface. measurement of these dimensions may be made prior to solder dripping. 6. chip carriers shall be constructed of a minimum of two ceramic layers.
product specification TDC1049 15 mec hanical dimensions (contin ued) 68 lead plastic grid arra y a2 a p d1 d pin 1 identifier bottom view top view beveled corner vendor option a .080 .125 2.03 3.18 symbol inches min. max. min. max. millimeters notes a1 .025 .060 0.64 1.52 .180 4.57 a2 .105 2.67 ? .017 .020 0.43 0.51 d 1.140 1.180 28.96 29.97 d1 .120 .140 3.05 3.56 e .050 nom. 1.27 nom. 1.000 bsc 25.40 bsc .100 bsc 2.54 bsc l .003 .076 m 11 11 68 68 2 3 n p ?2 notes: 1. 2. 3. 4. pin #1 identifier shall be within shaded area shown. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. controlling dimension: inch. l ? e ?2 a1
product specification TDC1049 1/14/99 0.0m 001 stock# ds90001049 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com or dering inf ormation pr oduct number t emperature rang e screening p ac ka g e p ac ka g e marking TDC1049j0c std - t a = 0 c to 70 c commercial 64 lead sidebr az ed cer amic dip 1049j0c TDC1049j0v ext - t c = - 55 c to 125 c mil- std- 883 64 lead sidebr az ed cer amic dip 1049j0v 5962-8853201xa ext - t c = - 55 c to 125 c p er standard mil dr a wing 64 lead sidebr az ed cer amic dip 5962- 8853201xa TDC1049c1c std - t a = 0 c to 70 c commercial 68- lead lcc 1049c1c TDC1049c1v ext - t c = - 55 c to 125 c mil- std- 883 68- lead lcc 1049c1v 5962- 8853201za ext - t c = - 55 c to 125 c p er standard mil dr a wing 68- lead lcc 5962- 8853201za TDC1049g8c std - t a = 0 c to 70 c commercial 68 lead cer amic pga 1049g8c TDC1049g8v ext - t c = - 55 c to 125 c mil- std- b83 68 lead cer amic pga 1049g8v standar d militar y dra wing nearest equiv alent f air c hild pr oduct no. p ac ka g e 5962-8853201xa TDC1049j0v 64 lead sidebr az ed cer amic dip 5962- 8853201ya TDC1049j3v 64 lead bottombr az ed cer amic dip 5962- 8853201za TDC1049c1v 68- lead lcc 5962- 8853201ua TDC1049l1v 68- lead lcc

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