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65com/132seg driver & controller for stn lcd KS0713 1 introduction the KS0713 is a driver and controller lsi for graphic dot-matrix liquid crystal display systems. it contains 65 common and 132 segment driver circuits. this chip is connected directly to a microprocessor, accepts 8-bit serial or parallel display data, and stores an on-chip display data ram of 65 132 bits. it provides a highly-flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. furthermore, the chip performs display data ram read/write operation with no external operating clock to minimize power consumption. because KS0713 contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features ? driver output circuits ? 65 common outputs / 132 segment outputs ? on-chip display data ram ? capacity: 65 132 = 8,580 bits ? multi-chip operation ? master, slave available ? applicable duty-ratios ? microprocessor interface ? 8-bit parallel bidirectional interface with 6800-series or 8080-series ? serial interface (only write operation) available ? function set ? various instruction set: power control, adc, shl, entire display on/off, sleep mode, standby mode, .... etc. ? h/w, s/w reset capable ? built-in analog circuit ? built-in oscillator circuit ? voltage converter ( 2 / 3 / 4 / 5) ? voltage regulator (temperature coefficient: - 0.05%/ c, - 0.2%/ c) ? voltage follower ? electronic contrast control functions (64 steps) duty ratio applicable lcd bias maximum display area 1/65 1/7 or 1/9 65 132 1/49 1/6 or 1/8 49 132 1/33 1/5 or 1/6 33 132
KS0713 65com/132seg driver & controller for 2 ? operating voltage range ? supply voltage (v dd ): 2.4 to 5.5 v ? lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 15.0 v ? low power consumption ? 80 m a typ. (v dd = 3v, 4 boosting, v0 = 11v, internal power supply on) ? 10 m a max. (standby mode) ? package type ? slim chip for cog, and tcp available.
65com/132seg driver & controller for stn lcd KS0713 3 block diagram figure 1. block diagram status register bus holder page address circuit display data ram 65 5 132 = 8,580bits line address circuit i/o buffer column address circuit power supply v / f circuit v / r circuit v / c circuit hpm c1 - c1+ c2 - c2+ c3 - c3+ dcdc5b bsts v0 vr intrs temps instruction register instruction decoder mpu interface ( parallel & serial ) db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) mi resetb ps rw_wr e_rd rs cs2 cs1b display timing generator circuit oscillator ms cl m frs disp duty0 duty1 cls vdd v0 v1 v2 v3 v4 vss 132 segment driver circuits 33common driver circuits 33 common driver circuits common output control circuit display data control circuit coms com64 com33 seg132 seg131 seg130 : : : : seg4 seg3 seg2 seg1 : : com32 com1 coms vout
KS0713 65com/132seg driver & controller for 4 pad configuration figure 2. pad configuration item pad no. size unit x y chip size - 10860 2920 m m pad pitch 1 - 110 90 111 - 324 70 bumped pad size 1 - 110 56 114 111 - 147 108 50 148 - 287 50 108 288 - 324 108 50 bumped pad height 1 - 324 17 (typ) eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 148 287 147 288 111 324 110 1 KS0713 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee
65com/132seg driver & controller for stn lcd KS0713 5 table 1. pad location [unit: m m] pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dummy dummy frs m cl disp vss cs1b cs2 vdd resetb rs vss rw_wr e_rd vdd db0 db1 db2 db3 db4 db5 db6 db7 vss vdd vdd vdd duty0 duty1 vss ms cls vdd mi ps vss vss vss vss vss vss vss vss vss vss vdd vdd vdd vdd -4905 -4815 -4725 -4635 -4545 -4455 -4365 -4275 -4185 -4095 -4005 -3915 -3825 -3735 -3645 -3555 -3465 -3375 -3285 -3195 -3105 -3015 -2925 -2835 -2745 -2655 -2565 -2475 -2385 -2295 -2205 -2115 -2025 -1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 vdd vdd vdd vdd vdd vdd vout vout vout vout c3+ c3+ c3+ c3+ c3- c3- c3- c3- c1+ c1+ c1+ c1+ c1- c1- c1- c1- c2+ c2+ c2+ c2+ c2- c2- c2- c2- vss vss vr vr v0 v0 v1 v1 v2 v2 v3 v3 v4 v4 vss vss -405 -315 -225 -135 -45 45 135 225 315 405 495 585 675 765 855 945 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2025 2115 2205 2295 2385 2475 2565 2655 2745 2835 2925 3015 3105 3195 3285 3375 3465 3555 3645 3735 3825 3915 4005 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 bsts dcdc5b vdd hpm intrs vss temps vdd dummy dummy dummy dummy coms com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 dummy dummy dummy dummy dummy 4095 4185 4275 4365 4455 4545 4635 4725 4815 4905 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 5271 4865 4795 4725 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1316 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1321 1321 1321 pad center coordinates
KS0713 65com/132seg driver & controller for 6 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 dummy seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 4655 4585 4515 4445 4375 4305 4235 4165 4095 4025 3955 3885 3815 3745 3675 3605 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 seg129 seg130 seg131 seg132 dummy dummy dummy dummy dummy dummy coms com64 com63 com62 com61 com60 com59 com58 com57 com56 com55 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3535 -3605 -3675 -3745 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 -4865 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1321 1260 1190 1120 1050 980 910 840 770 700 630 560 490 420 table 1. pad location (continued) [unit: m m] pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y
65com/132seg driver & controller for stn lcd KS0713 7 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 com54 com53 com52 com51 com50 com49 com48 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 dummy dummy -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 -5271 350 280 210 140 70 0 -70 -140 -210 -280 -350 -420 -490 -560 -630 -700 -770 -840 -910 -980 -1050 -1120 -1190 -1260 table 1. pad location (continued) [unit: m m] pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coordinate x y x y x y
KS0713 65com/132seg driver & controller for 8 pin description table 2. pin description name i/o description power supply v dd power power supply connect to mpu power supply pin. v ss 0 v (gnd) v0 v1 v2 v3 v4 i/o the voltage determined by the lcd pixel is impedance-converted for application by an operational amplifier. voltages have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the on-chip power circuit is active, these voltages are generated according to the state of lcd bias, as shown in the table below. lcd driver supply c1+ o capacitor1+ connect for the internal voltage converter c1 - capacitor1 - connect for the internal voltage converter c2+ capacitor2+ connect for the internal voltage converter c2 - capacitor2 - connect for the internal voltage converter c3+ capacitor3+ connect for the internal voltage converter c3 - capacitor3 - connect for the internal voltage converter vout i/o voltage converter output dcdc5b i 5 times boosting circuit enable input pin. when this pin is low in 4 times boosting circuit, the 5 times boosted voltage appears at vout. vr i v0 voltage adjustment pin, valid only when using external resistors (intrs = ? l ? ) lcd bias v1 v2 v3 v4 1/9 bias (8/9) v0 (7/9) v0 (2/9) v0 (1/9) v0 1/8 bias (7/8) v0 (6/8) v0 (2/8) v0 (1/8) v0 1/7 bias (6/7) v0 (5/7) v0 (2/7) v0 (1/7) v0 1/6 bias (5/6) v0 (4/6) v0 (2/6) v0 (1/6) v0 1/5 bias (4/5) v0 (3/5) v0 (2/5) v0 (1/5) v0
65com/132seg driver & controller for stn lcd KS0713 9 system control ms i master/slave mode select input. master makes some signals for display, and slave receives them. this is for display synchronization. ms = ? h ? : master mode ms = ? l ? : slave mode cls i built-in oscillator circuit enable / disable select pin. cls = ? h ? : enable cls = ? l ? : disable (external display clock input to cl pin) cl i/o display clock input/output. when KS0713 is used in master/slave mode (multi-chip), the cl pins must be connected to each other. m i/o lcd ac signal input/output. when KS0713 is used in master/slave mode(multi-chip), the m pins must be connected to each other. ms = ? h ? : output ms = ? l ? : input. frs o static driver output. this pin is used together with the m pin. disp i/o lcd display blanking control input/output. when KS0713 is used in master/slave mode (multi-chip), the disp pins must be connected to each other. ms = ? h ? : output ms = ? l ? : input intrs i internal resistor select. this pin selects the resistors for adjusting v0 voltage level and is available only in master mode. intrs = ? h ? : using built-in resistors, intrs = ? l ? : not using built-in resistors. v0 voltage is controlled by vr pin and external resistive divider. hpm i power control pin of the power supply circuit for lcd driver. hpm = ? h ? : high power mode hpm = ? l ? : normal mode this pin is available only in master mode. temps i selects temperature coefficient of the reference voltage temps = ? l ? : - 0.05%/ c temps = ? h ? : - 0.2%/ c table 2. pin description (continued) name i/o description ms cls osc circuit power supply cl m frs disp h h enable enable output output output output l disable enable input output output output l - disable disable input input output input
KS0713 65com/132seg driver & controller for 10 bsts i selects input voltages of the built-in voltage converter duty1 duty0 i the lcd driver duty ratio depends on the following table. table 2. pin description (continued) name i/o description bsts voltage converter input voltage remarks l 4 v v dd > 4v v dd v dd 4v h v dd 2.4 v dd 5.5v duty1 duty0 duty ratio l l 1/33 l h 1/49 h l/h 1/65
65com/132seg driver & controller for stn lcd KS0713 11 mpu interface resetb i hardware reset input. initialization is performed by edge sensing (rising or falling) of the reset signal. ps i parallel / serial data select input. note: in serial mode, it is impossible to read data from the on-chip ram. db[5:0] is high impedance and e_rd and rw_wr must be fixed on high or low. mi i microprocessor interface select input in parallel mode. mi = ? h ? : 6800 series mpu interface mi = ? l ? : 8080 series mpu interface cs1b cs2 i chip select inputs. data input / output is enabled only when cs1b is low and cs2 is high. when chip select is non-active, db[7:0] will be high impedance. rs i register select input. rs = ? h ? : the data on db[7:0] is display data rs = ? l ? : the data on db[7:0] is control data rw_wr i when interfacing to a 6800-series mpu, read/write is enabled at; rw_wr = ? h ? : read. rw_wr = ? l ? : write. when interfacing to an 8080-series mpu, rw_wr is enabled at low. e_rd i when interfacing to a 6800-series mpu: active high. this is used as an enable clock input pin of the 6800-series mpu. when interfacing to an 8080-series mpu: active low. this input connects the rd signal of the 8080-series mpu. while this signal is low, KS0713 data bus output is enabled. db7 to db0 i/o 8-bit bidirectional data bus. it is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = ? low ? ); db7: serial input data (sid) db6: serial input clock (sclk) db5 to db0: high impedance. when chip select is not active, db7 to db0 will be high impedance. table 2. pin description (continued) name i/o description ps operating mode chip select data / instruction data i/o read / write serial clock h parallel cs1b, cs2 rs db[7:0] e_rd, rw_wr - l serial cs1b, cs2 rs db7 (sid) write only db6 (sclk)
KS0713 65com/132seg driver & controller for 12 lcd driver output seg1 to seg132 o lcd driver output for segment. the display data and the m signal control the output voltage of segment driver. com1 to com64 o lcd driver output for common. the internal scanning data and m signal control the output voltage of common driver. coms o common signal output for the icons. the output signals of two pins are the same. when not used, these pins should be left open. in multi-chip (master/slave) mode, all coms pins on both master and slave units are the same signal. table 2. pin description (continued) name i/o description display data m segs output voltage normal display reverse display h h v0 v2 h l vss v3 l h v2 v0 l l v3 vss power save mode vss scan data m coms output voltage h h vss h l v0 l h v1 l l v4 power save mode vss
65com/132seg driver & controller for stn lcd KS0713 13 functional description microprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the KS0713 can interface with a microprocessor only when cs1b is low and cs2 is high. when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db7 to db0 are set to high impedance. for the serial interface, the internal shift register and the counter are reset. parallel / serial interface the KS0713 has three types of interface with mpu: one serial and two parallel interface. this parallel or serial interface is determined by ps pin as shown in table 3. note: ? - ? don ? t care parallel interface (ps = ? h ? ) the 8-bit bidirectional data bus is used in parallel interface and the type of mpu is selected by mi as shown in table 4. the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 5. . table 3. parallel / serial interface mode ps type cs1b cs2 mi interface mode h parallel cs1b cs2 h 6800-series mpu mode l 8080-series mpu mode l serial cs1b cs2 - serial-mode table 4. microprocessor selection for parallel interface mi cs1b cs2 rs e_rd rw_wr db7 to db0 mpu bus h cs1b cs2 rs e rw db7 to db0 6800-series l cs1b cs2 rs rd wr db7 to db0 8080-series table 5. parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (rd) rw_wr (wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
KS0713 65com/132seg driver & controller for 14 serial interface (ps = ? l ? ) when KS0713 is active (cs1b = ? l ? , cs2 = ? h ? ), serial data (db7) and serial clock (db6) inputs are enabled. when not active, the internal 8-bit shift register and the 3-bit counter are reset. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal[db6] is easily affected by the external noise caused by the line length, the operation check on the actual machine is recommended. busy flag the busy flag indicates whether the KS0713 is operating or not. when db7 is high in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor does not need to check this flag before each instruction, which improves the microprocessor performance. data transfer the KS0713 uses a bus holder and an internal data bus for data transfer with mpu. when writing data from the mpu to an on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 2. when reading data from an on-chip ram to mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6.3. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. figure 3. serial interface timing cs1b cs2 sid sclk rs db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7
65com/132seg driver & controller for stn lcd KS0713 15 external signals internal signals figure 4. write timing external signals internal signals figure 5. read timing rs wr rd db7 ~ db0 n d(n) d(n+1) d(n+2) d(n+3) d(n+4) d(n+5) n preset n+5 wr rd bus holder column address d(n+2) d(n+3) d(n+4) d(n+5) n+1 n+2 n+3 n+4 n d(n) d(n+1) rs wr rd db7 ~ db0 dummy n d(n+3) d(n+4) d(n+2) d(n) d(n+1) n+5 wr rd bus holder column address d(n+3) d(n+4) n+1 n+2 n+3 n+4 n preset n dummy d(n+2) d(n) d(n+1)
KS0713 65com/132seg driver & controller for 16 display data ram (ddram) the display data ram stores pixel data for the lcd. it is a 65-row ((8 page by 8-bit) + 1) by 132-column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the ninth page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6. the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is displayed without causing the lcd to flicker. page address circuit the function of this circuit is to provide a page address to the display data ram shown in table 7. it incorporates a 4-bit page address register changed only by the set page instruction. page address 8 (db3 is high, but db2, db1 and db0 are low) is a special ram area for icons, and only display data db0 is valid. when page address is above 8, it is impossible to access the on-chip ram. line address circuit this circuit assigns ddram a line address corresponding to the first line (com1) of the display. therefore, by setting the line address repeatedly, it is possible to scroll the screen and switch the page without changing the contents of the on-chip ram (refer to table 7). it incorporates a 6-bit line address register which can only be changed by the initial display line instruction and a 6-bit counter circuit. at the beginning of each lcd frame, the contents of a register are copied to the line counter which is increased by the cl signal, and generates the line address for transferring the 132-bit ram data to the 100 display data latch circuit. however, display data of icons are not scrolled because the microprocessor cannot access the line address of icons. figure 6. ram-to-lcd data transfer db0 0 0 1 - 0 db1 1 0 0 1 db2 0 1 1 0 db3 1 0 1 0 db4 0 0 0 1 display data ram com1 - com2 com3 com4 com5 lcd display
65com/132seg driver & controller for stn lcd KS0713 17 column address circuit column address circuit has a 8-bit preset counter that provides column address to the display data ram (shown in table 7). when set column address msb / lsb instruction is issued, 8-bit [y7:y0] is updated. since this address is increased by 1 each time there is a read or write data instruction, the microprocessor can access the display data continuously. however, the counter is not increased and it is locked at a non-existing address above 84h. it is unlocked if a column address is set again by set column address msb/lsb instruction. the column address counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. refer to the following table 6. table 6. segment output direction according to adc seg output seg 1 seg 2 seg 3 seg 4 ...... seg 129 seg 130 seg 131 seg 132 column address [y7:y0] 00h 01h 02h 03h ...... 80h 81h 82h 83h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ...... lcd panel display (adc = 1) ......
KS0713 65com/132seg driver & controller for 18 table 7. display data ram addressing page address p3,p2,p1,p0 data column address line address (hex) common output (1/65) common output (1/49) common output (1/33) 0 0 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page0 00 01 02 03 04 05 06 07 com37 com38 com39 com40 com41 com42 com43 com44 com37 com38 com39 com40 com41 com42 com43 com44 - - - - - - - - 0 0 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page1 08 09 0a 0b 0c 0d 0e 0f com45 com46 com47 com48 com49 com50 com51 com52 com45 com46 com47 com48 - - - - - - - - - - - - 0 0 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page2 10 11 12 13 14 15 16 17 com53 com54 com55 com56 com57 com58 com59 com60 - - - - - - - - - - - - - - - - 0 0 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page3 18 18 1a 1b 1c 1d 1e 1f com61 com62 com63 com64 com1 com2 com3 com4 - - - - com1 com2 com3 com4 - - - - com1 com2 com3 com4 0 1 0 0 db0 db1 db2 db3 db4 db5 db6 db7 page4 20 21 22 23 24 25 26 27 com5 com6 com7 com8 com9 com10 com11 com12 com5 com6 com7 com8 com9 com10 com11 com12 com5 com6 com7 com8 com9 com10 com11 com12 0 1 0 1 db0 db1 db2 db3 db4 db5 db6 db7 page5 28 29 2a 2b 2c 2d 2e 2f com13 com14 com15 com16 com17 com18 com19 com20 com13 com14 com15 com16 com17 com18 com19 com20 com13 com14 com15 com16 com17 com18 com19 com20
65com/132seg driver & controller for stn lcd KS0713 19 note: when the initial display line address is 1ch. 0 1 1 0 db0 db1 db2 db3 db4 db5 db6 db7 page6 30 31 32 33 34 35 36 37 com21 com22 com23 com24 com25 com26 com27 com28 com21 com22 com23 com24 com25 com26 com27 com28 com21 com22 com23 com24 com25 com26 com27 com28 0 1 1 1 db0 db1 db2 db3 db4 db5 db6 db7 page7 38 39 3a 3b 3c 3d 3e 3f com29 com30 com31 com32 com33 com34 com35 com36 com29 com30 com31 com32 com33 com34 com35 com36 com29 com30 com31 com32 - - - - 1 0 0 0 db0 page8 coms coms coms column address [hex] adc = 0 00 01 02 03 04 05 - - - - - - 7e 7f 80 81 82 83 adc = 1 83 82 81 80 7f 7e - - - - - - 05 04 03 02 01 00 lcd output s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 - - - - - - s e g 1 2 7 s e f 1 2 8 s e g 1 2 9 s e g 1 3 0 s e g 1 3 1 s e g 1 3 2 table 7. display data ram addressing (continued) page address p3,p2,p1,p0 data column address line address (hex) common output (1/65) common output (1/49) common output (1/33)
KS0713 65com/132seg driver & controller for 20 lcd display circuits oscillator this is a completely on-chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used to display lcd. the display clock (cl) generated by the oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. the line address of the on- chip ram is generated in synchronization with the display clock (cl). while the 132-bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data which is read to the lcd driver is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. two-frame ac driver waveforms and internal timing signal are shown in figure 7. when this KS0713 is used for a multi-chip, the slave chip must receive the m, cl, disp signals from the master. table 8 shows the m, cl, and disp status. table 8. master and slave signal status operation mode oscillator on / off m cl disp master on (internal clock used) output output output off (external clock used) output input output slave - input input input
65com/132seg driver & controller for stn lcd KS0713 21 display data latch circuit this latch circuit temporarily stores the output display data from the display data ram to the lcd driver in each instruction period. this latch circuit is controlled by the display on/off, reverse display on/off and entire display on/off instructions, and the data in the display data ram remains unchanged. duty ratio: 1/65 figure 7. 2-frame ac driving waveform cl m com1 com2 segn v0 v1 v4 vss v0 v1 v4 vss v0 v2 v3 vss 64 65 1 2 3 4 5 64 65 1 2 3 4
KS0713 65com/132seg driver & controller for 22 common output control circuit this circuit controls the relationship between the number of common output and specified duty ratio. shl select instruction specifies the scanning direction of the common output pins. table 9. the relationship between duty ratio and common output duty shl common output pins com[1:16] com[17:24] com[25:40] com[41:48] com[49:64] coms 1/33 0 com[1:16] no connection no connection no connection com[17:32] coms 1 com[32:17] no connection no connection no connection com[15:0] coms 1/49 0 com[1:24] no connection com[25:48] coms 1 com[48:25] no connection com[24:1] coms 1/65 0 com[1:64] coms 1 com[64:1] coms
65com/132seg driver & controller for stn lcd KS0713 23 lcd driver circuit this driver circuit is configured by a 66-channel common driver and a 132-channel segment driver. this lcd panel driver voltage depends on the combination of display data and m signal. figure 8. segment and common timing com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 |seg2-com1| |seg1-com1| seg3 seg2 seg1 com3 com1 com2 m |v0| |v1| |v2| |v3| |v4| |vss| |v0| |v1| |v2| |v3| |v4| |vss| v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss
KS0713 65com/132seg driver & controller for 24 power supply circuits the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by power control instruction. for details, refers to ? instruction description ? . table 10 shows the referenced combinations in using power supply circuits. table 10. recommended power supply combinations user setup power control register (vc vr vf) v/c circuits v/r circuits v/f circuits vout pin v0 pin v1 - v4 pin only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
65com/132seg driver & controller for stn lcd KS0713 25 voltage converter circuits these circuits boost up the electric potential between v dd and v ss 2, 3, 4, or 5 times toward positive side, boosted voltage is then output from the v out pin. figure 9. boosting two/three/four/five times circuit ? three ? two vout=2 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd vss v dd - + - + c1 c1 gnd v ss v dd vout=3 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v ss v dd v dd - + + - - + c1 c1 c1 gnd v ss v dd ? five ? four vout=4 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd v ss - - + + - + - + c1 c1 c1 c1 gnd v ss v dd v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd v ss c1 + - - + - + - + c1 c1 c1 gnd v ss v dd vout=5 v dd gnd
KS0713 65com/132seg driver & controller for 26 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure. 10, it is necessary to be applied internally or externally. for the equation 1, we determine v0 by ra, rb and vev. the ra and rb are connected internally or externally by intrs pin. voltage of electronic volume (v ev ) is determined by equation 2, where the parameter a is the value selected by instruction, ? set reference voltage register ? , within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 11. table 11. v ref voltage at ta = 25 c temps temp. coefficient v ref [v] 0 - 0.05% / c 2.0 1 - 0.2% / c 2.0 figure 10. internal voltage regulator circuit v01 rb ra -------- + ? ?? v ev [v] = v ev 1 63 a ? () 300 --------------------- ? ? ?? v ref [v] = v ev gnd v ss ra vr rb v0 vout + _ + _
65com/132seg driver & controller for stn lcd KS0713 27 1) using internal resistors, ra and rb (intrs = ? h ? ) when intrs pin is high, resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, ? regulator resistor select ? and ? set reference voltage ? . figure 11. and 12. shows v0 voltage measured by adjusting the internal regulator register ratio (rb/ra), 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. table 12. internal rb/ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb/ra) 1.90 2.19 2.55 3.02 3.61 4.35 5.29 6.48 figure 11. v0 voltage 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 0 8 16 24 32 40 48 56 electronic volume level ( temp. coefficient = -0.05%/c & -0.2%/c ) v0 (1,1,1) (1,1,0) (1,0,1) (1,0,0) (0,1,1) (0,1,0) (0,0,1) (0,0,0)
KS0713 65com/132seg driver & controller for 28 2) using external resistors, ra and rb (intrs = ? l ? ) when intrs pin is low, it is necessary to connect external regulator resistor ra between vr and v ss , and rb between v0 and vr. example: for the following requirements. 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1,0,0,0,0,0) 3. maximum current flowing ra, rb = 1 m a from equation 1 from equation 1 from requirement 3. from equations equation 3, 4 and 5: ra = 1.79 [ w ] rb = 8.21 [ w ] table 13 shows the range of v0 depending on the above requirements. table 13. the range of v0 depending electronic volume level 0 ....... 32 ....... 63 v0 8.83 ....... 10.00 ....... 11.17 101 rb ra -------- + ? ?? v ev [v] = v ev 1 6332 ? () 300 ------------------------ ? ? ?? 2.01.79 @ [v] = 10 ra + rb ----------------------- 1 m a [] =
65com/132seg driver & controller for stn lcd KS0713 29 voltage follower circuits v lcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3, v4), and those output impedance are converted by the voltage follower to increase drive capability. table 14 shows the relationship between v1 - v4 level and each duty ratio. referenced power supply circuit for driving lcd panel table 14. the relationship between v1 - v4 level and each duty ratio duty ratio duty 1 duty 0 lcd bias v1 v2 v3 v4 1/33 l l 1/5 4/5 v0 3/5 v0 2/5 v0 1/5 v0 1/6 5/6 v0 4/6 v0 2/6 v0 1/6 v0 1/49 l h 1/6 5/6 v0 4/6 v0 2/6 v0 1/6 v0 1/8 7/8 v0 6/8 v0 2/8 v0 1/8 v0 1/65 h l/h 1/7 6/7 v0 5/7 v0 2/7 v0 1/7 v0 1/9 8/9 v0 7/9 v0 2/9 v0 1/9 v0 figure 12. when using all lcd power circuits (4-times, vc: on, v/r: on, v/f: on) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c1 c1 c2 - + c2 - + c2 - + c2 - + c2 - + c1 c1 v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c1 c1 c2 - + c2 - + c2 - + c2 - + c2 - + c1 c1 ra rb vss ? when using internal regulator resistors ? when not using internal regulator resistors
KS0713 65com/132seg driver & controller for 30 figure 13. when using some lcd power circuits (v/c: off, v/r: on, v/f: on) ? when using internal regulator resistors ? when not using internal regulator resistors external power supply v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + ra rb vss v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + external power supply
65com/132seg driver & controller for stn lcd KS0713 31 figure 14. when using some lcd power circuits (v/c: off, v/r: off, v/f: on) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss c2 - + c2 - + c2 - + c2 - + c2 - + external power supply
KS0713 65com/132seg driver & controller for 32 figure 15. when not using any internal lcd power circuits (v/c: off, v/r: off, v/f: off) v dd ms intrs vout c3+ c3 - c2+ c2 - c1+ c1 - vr v0 v1 v2 v3 v4 vss external power supply value of external capacitance item value unit c1 1.0 - 4.7 m f c2 0.47 - 1.0
65com/132seg driver & controller for stn lcd KS0713 33 reset circuit internal function can be initialized by setting resetb to low or reset instruction. when resetb becomes low, following procedure occurs. ? display on/off:off ? entire display on/off: off (normal) ? adc select: off (normal) ? reverse display on/off : off (normal) ? power control register (vc, vr, vf) = (0, 0, 0) ? lcd bias ratio: 1/7 (1/65 duty), 1/6 (1/49 duty), 1/5 (1/33) duty ? read-modify-write: off ? shl select: 0 ? static indicator mode: off static indicator register: (s1, s0) = (0, 0) ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? regulator resistor select register: (r2, r1, r0) = (0, 0, 0) ? reference voltage set: off, reference voltage control register: (sv5, sv4, sv3, sv2, sv1, sv0) = (1, 0, 0, 0, 0, 0) when reset instruction is issued, following procedure occurs. ? read-modify-write: off ? static indicator mode: off static indicator register: (s1, s0) = (0, 0) ? shl select: 0 ? display start line: 0 (first) ? column address: 0 ? page address: 0 ? regulator resistor select register: (r2, r1, r0) = (0, 0, 0) ? reference voltage set: off reference voltage control register (sv5, sv4, sv3, sv2, sv1, sv0) = (1, 0, 0, 0, 0, 0) while resetb is low or reset instruction is executed, no instruction other than read status can be accepted. reset status appears at db4. after db4 becomes low, any instruction can be accepted. resetb pin must be connected to the reset pin of mpu. then initialize the mpu and this lsi at the same time. the initialization by resetb pin is essential before use.
KS0713 65com/132seg driver & controller for 34 instruction description note : ? ? = don ? t care table 15. instruction table instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 function read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on/ off resetb 0 0 0 0 read the internal status display on/off 0 0 1 0 1 0 1 1 1 don turn on/off lcd panel when don=0, display is off when don=0, display is on initial display line 0 0 0 1 st5 st4 st3 st2 st1 st0 specify ddram line for com1 set reference voltage mode 0 0 1 0 0 0 0 0 0 1 set reference voltage mode set reference voltage register 0 0 sv5 sv4 sv3 sv2 sv1 sv0 set reference voltage register set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y7 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc=0 normal direction (seg1 ? seg132) when adc=1 reverse direction (seg132 ? seg1) reverse display on/ off 0 0 1 0 1 0 0 1 1 rev select normal/reverse display when rev=0 normal when rev=1 reverse entire display on/off 0 0 1 0 1 0 0 1 0 eon select normal display / entire display on when eon=0, normal display when eon=1, entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode reset 0 0 1 1 1 0 0 0 1 0 initialize internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl=0 normal direction (com1 ? com64) when shl=1 reverse direction (com64 ? com1) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select resistance ratio of the regulator resistor set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode set static indicator register 0 0 s1 s0 set static indicator register power save - - - - - - - - - - compound instruction of display off and entire display on test instruction 0 0 1 1 1 1 don't use this instruction.
65com/132seg driver & controller for stn lcd KS0713 35 read display data 8-bit data from display data ram specified by the column address and page address can be read by this instruction. as the column address is increased by 1 automatically after each instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. write display data 8-bit display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. read status indicates the internal status conditions. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on/off resetb 0 0 0 0 flag description busy the device is busy when carrying out internal operation or reset. all instructions are rejected until busy goes to low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg132 ? seg1), 1: normal direction (seg1 ? seg132) on/off indicates display on / off status. 0: display on, 1: display off resetb indicates initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset.
KS0713 65com/132seg driver & controller for 36 display on/off turns the display on or off initial display line sets the line address of display ram to determine the initial display line. the ram display data is displayed at the top row (com1 when shl = l, com64 when shl = h) of the lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 don don 1 display on 0 display off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 st5 st4 st3 st2 st1 st0 st5 st4 st3 st2 st1 st0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
65com/132seg driver & controller for stn lcd KS0713 37 reference voltage select set reference voltage mode set reference voltage register consists of two bytes instruction. the first byte sets reference voltage mode, the second one updates the contents of reference voltage register. after second instruction reference voltage mode is released. set page address sets the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the page address defines the address of the display ram to write or read display data. changing the page address doesn't affect the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 sv5 sv4 sv3 sv2 sv1 sv0 sv5 sv4 sv3 sv2 sv1 sv0 reference voltage 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
KS0713 65com/132seg driver & controller for 38 set column address set column address msb set column address lsb sets the column address of the display ram from the microprocessor into the column address register. the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, column addresses are automatically increased, starting with the address stored in the column address register and continuously rotating right. adc select changes the relationship between the ram column address and segment driver. the direction of the segment driver output pins can be reversed by software. this makes the ic layout flexible in the lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y7 y6 y5 y4 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc 0 normal direction (seg1 ? seg132) 1 reverse direction (seg132 ? seg1)
65com/132seg driver & controller for stn lcd KS0713 39 normal / reverse display reverses the display status on the lcd panel without rewriting the contents of the display data ram. entire display on / off forces all lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are put on hold. this instruction has priority over the reverse display on / off instruction. lcd bias select selects the lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon 0 normal display 1 entire display on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias duty ratio duty 1 duty 0 lcd bias bias = 0 bias = 1 1/33 0 0 1/5 1/6 1/49 0 1 1/6 1/8 1/65 1 0/1 1/7 1/9
KS0713 65com/132seg driver & controller for 40 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data. it reduces the load of the microprocessor when the data of a specific area is repeatedly changed during cursor blinking. this mode is cancelled by the reset modify-read instruction. reset modify-read this instruction cancels the modify read mode, and makes the column address return to its initial value just before the set modify read instruction starts. reset this instruction resets the initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of display data ram. this instruction cannot initialize the lcd power supply which is initialized by the resetb pin. shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl 0 normal direction (com1 ? com64) 1 reverse direction (com64 ? com1)
65com/132seg driver & controller for stn lcd KS0713 41 power control selects one out of eight power circuit functions by using a 3-bit register. an external power supply and a part of internal power supply functions can be used simultaneously. regulator resistor select se lects resistance ratio of the resistor used in the voltage regulator. see voltage regulator section in power supply cir cuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc, vr, vf indicates whether the voltage converter / regulator / follower turns on or not 0 off 1 on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb/ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
KS0713 65com/132seg driver & controller for 42 set static indicator state set static indicator mode (on / off) set static indicator register this instruction sets the static indicator on / off. when it is on, the static indicator operates and blinks at an interval of approximately one second. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm static indicator 0 static indicator off 1 static indicator on rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 1 second blinking) 1 0 on (about 0.5 second blinking) 1 1 on (always on)
65com/132seg driver & controller for stn lcd KS0713 43 power save (compound instruction) if the entire display on/off instruction is issued during the display off state, KS0713 enters the power save status to reduce the power consumption to the static power consumption value. according to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. when static indicator mode is on, standby mode is issued. when off, sleep mode is issued. power save mode is released by the display on & entire display off instruction. figure 16. power save (compound instruction) release standby mode power save off ( compound instruction ) [ entire display off ] [ display on ] release sleep mode power save off ( compound instruction ) [ entire display off ] [ static indicator on ] [ display on ] standby mode [ oscillator circuit : on] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 10 m a ] sleep mode [ oscillator circuit : off ] [ lcd power supply circuit : off ] [ all com/seg outputs : vss ] [ consumption current : < 2 m a ] power save ( compound instruction ) [ display off ] [ entire display on ] static indicator off static indicator on
KS0713 65com/132seg driver & controller for 44 referential instruction setup flow ? initializing with the built-in power supply circuits figure 17. initializing with the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels user lcd power setup by internal instructions [ power control ] [ regulator resistor select ] [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ? h ? user system setup by external pins waiting for stabilizing the power power on ( vdd - vss ) keeping the resetb pin = ? l ? user system setup by external pins
65com/132seg driver & controller for stn lcd KS0713 45 ? initializing without the built-in power supply circuits figure 18. initializing without the built-in power supply circuits end of initialization waiting for stabilizing the lcd power levels release power save user lcd power setup by internal instructions [ regulator resistor select ] [reference voltage register set ] user application setup by internal instructions [ adc select ] [ shl select ] [lcd bias select ] start of initialization resetb pin = ? h ? set power save waiting for stabilizing the power power on ( vdd - vss ) keeping the resetb pin = ? l ? user system setup by external pins
KS0713 65com/132seg driver & controller for 46 ? data displaying ? power off figure 19. data displaying figure 20. power off end of initialization write display on/off by instruction [ display on/off ] display data ram addressing by instruction [ initial display line ] [ set page address ] [ set column address ] end of data display turn display on/off by instruction [ display on/off ] power off ( vdd - vss ) set power save by instruction optional status
65com/132seg driver & controller for stn lcd KS0713 47 specifications absolute maximum ratings notes: 1. v dd and v lcd are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied ( v lcd = v0 - v ss ). 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result. dc characteristics table 16. absolute maximum ratings parameter symbol rating unit supply voltage range v dd - 0.3 to + 7.0 v v lcd + 0.3 to + 17.0 input voltage range v in - 0.3 to v dd + 0.3 operating temperature range t opr - 40 to + 85 c storage temperature range t str - 55 to +125 table 17. dc characteristics (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 5.5 v v dd (1) operating voltage (2) v 0 4.0 - 15.0 v 0 (2) input voltage high v ih 0.8v d d - v dd (3) low v il v ss - 0.2v d d output voltage high v oh i oh = - 0.5ma 0.8v d d - v dd (4) low v ol i ol = 0.5ma v ss - 0.2v d d input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a (5) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 (6) lcd driver on resistance r on ta= 25 ? c,v0 = 8v - 2.0 3.0 k w segn comn (7) oscillator frequency (1) internal f osc ta = 25 ? c, duty ratio = 1/33 or 1/65 17 22 27 khz cl (8) external f cl 4.25 5.50 6.75 oscillator frequency (2) internal f osc ta = 25 ? c, duty ratio = 1/49 20 25 30 cl (8) external f cl 3.33 4.17 5.00
KS0713 65com/132seg driver & controller for 48 notes: voltage converter / regulator / follower voltage converter input voltage v dd 2 2.4 - 5.5 v v dd 3 2.4 - 5.0 4 2.4 - 3.75 5 2.4 - 3.0 voltage converter output voltage vout 2/ 3/ 4/ 5 voltage conversion (no-load) 95 99 - % vout voltage regulator operating voltage vout - 4.0 - 15.0 v vout voltage follower operating voltage v0 - 4.0 - 15.0 v0 (9) reference voltage v ref0 t a = 25 ? c - 0.05%/ ? c 1.94 2.0 2.06 (10) v ref1 - 0.2%/ ? c 1.94 2.0 2.06 (10) dynamic current consumption (1): when the built-in circuits is off (at operate mode). dynamic current consumption (1) i dd1 vdd = 3.0v, v0 - vss = 11.0v, 1/65 duty ratio, display pattern off - - 50 m a (11) dynamic current consumption (2): when the built-in circuits is on (at operate mode). dynamic current consumption (2) i dd2 vdd = 3.0v, quad boosting, v0 - vss = 11.0v, 1/65 duty ratio, display pattern off, normal power mode - 80 100 m a (11) vdd = 3.0v, quad boosting, v0 - vss = 11.0v, 1/65 duty ratio, display pattern checker, normal power mode - 95 160 m a (11) dynamic current consumption (3): when the built-in power is off (at access mode). dynamic current consumption (3) i dd3 vdd = 3.0v, v0 - vss = 11.0v, f cyc = 1mhz - - 1 ma current consumption during power save mode sleep mode current i dds1 during sleep - - 2.0 m a standby mode current i dds2 during standby - - 10.0 m a table 17. dc characteristics (continued) (v ss = 0v, v dd = 2.4v to 5.5v, ta = - 40 to 85 c) item symbol condition min. typ. max. unit pin used
65com/132seg driver & controller for stn lcd KS0713 49 1. though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from mpu. 2. in case of external power supply is applied. 3. cs1b, cs2, rs, db0 - db7, e_rd, rw_wr, resetb, ms, mi, ps, intrs, hpm, temps, bsts, dcdc5b, cls, cl, m, disp pins 4. db0 - db7, m, frs, disp, cl pins 5. cs1b, cs2, rs, db0 - db7, e_rd, rw_wr, resetb, ms, mi, ps, intrs, hpm, temps, bsts, dcdc5b, cls, cl, m, disp pins 6. applies when the db0 - db7, m, disp, and cl pins are in high impedance. 7. resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. r on = d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) 8. see table 18 for the relationship between oscillation frequency and frame frequency. 9. the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. 10. on-chip reference voltage source of the voltage regulator circuit to adjust v0. 11. applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current flowing through voltage regulation resistors (rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc. table 18. the relationship between oscillation frequency and frame frequency duty ratio item f cl f m remark 1/65 on-chip oscillator circuit is used f osc / 4 f osc / ( 8 65 ) ? f osc = oscillation frequency on-chip oscillator circuit is not used external input (f cl ) f cl / ( 2 65 ) ? f cl = display clock frequency 1/49 on-chip oscillator circuit is used f osc / 6 f osc / ( 12 49 ) ? f m = lcd ac signal frequency on-chip oscillator circuit is not used external input (f cl ) f cl / ( 2 49 ) 1/34 on-chip oscillator circuit is used f osc / 8 f osc / ( 16 33 ) on-chip oscillator circuit is not used external input (f cl ) f cl / ( 2 33 )
KS0713 65com/132seg driver & controller for 50 ac characteristics (v dd = 2.4v - 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v - 5.5v, ta = - 40 to + 85 c) figure 21. read/write characteristics (8080-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 13 17 - - ns system cycle time rs t cy80 400 - - ns pulse width (wr) rw_wr t pw80(w) 55 - - ns pulse width (rd) e_rd t pw80(r) 125 - - ns data setup time data hold time db0 - db7 t ds80 t dh80 35 13 - - ns read access time output disable time t acc80 t od80 - 10 - - 125 90 ns ns c l = 100pf item signal symbol min. typ. max. unit remark address setup time address hold time rs t as80 t ah80 10 10 - - ns system cycle time rs t cy80 150 - - ns pulse width (wr) rw_wr t pw80(w) 25 - - ns pulse width (rd) e_rd t pw80(r) 65 - - ns data setup time data hold time db0~db7 t ds80 t dh80 18 10 - - ns read access time output disable time t acc80 t od80 - 10 - - 65 45 ns ns c l = 100pf t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw80(r) , t pw80(w) t cy80 t ah80 t as80 db0-db7 ( write ) db0-db7 ( read) rd, wr cs1b (cs2=1) rs
65com/132seg driver & controller for stn lcd KS0713 51 (v dd = 2.4v - 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v - 5.5v, ta = - 40 to + 85 c) figure 22. read/write characteristics (6800-series microprocessor) item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 13 17 - - ns system cycle time rs t cy68 400 - - ns data setup time data hold time db0 - db7 t ds68 t dh68 35 13 - - ns access time output disable time t acc68 t od68 - 10 - - 125 90 ns c l = 100pf enable pulse width read write e_rd t pw68(r) t pw68(w) 125 55 - - - item signal symbol min. typ. max. unit remark address setup time address hold time rs t as68 t ah68 10 10 - - ns system cycle time rs t cy68 150 - - ns data setup time data hold time db0 - db7 t ds68 t dh68 18 10 - - ns access time output disable time t acc68 t od68 - 10 - - 65 45 ns ns c l = 100pf enable pulse width read write e_rd t pw68( r ) t pw68( w) 65 25 - - - t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw68(r) , t pw68(w) t cy68 t ah68 t as68 db0-db7 ( write ) db0-db7 ( read) e cs1b (cs2=1) rs
KS0713 65com/132seg driver & controller for 52 (v dd = 2.4v - 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v - 5.5v, ta = - 40 to + 85 c) figure 23. serial interface characteristics item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 450 180 135 - - ns address setup time address hold time rs t ass t ahs 90 360 - - ns data setup time data hold time db7(sid) t dss t dhs 90 90 - - ns cs1b setup time cs1b hold time cs1b t css t chs 55 180 - - ns item signal symbol min. typ. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 225 90 70 - - ns address setup time address hold time rs t ass t ahs 45 180 - - ns data setup time data hold time db7 (sid) t dss t dhs 45 45 - - ns cs1b setup time cs1b hold time cs1b t css t chs 25 90 - - ns t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = 1 )
65com/132seg driver & controller for stn lcd KS0713 53 (v dd = 2.4v - 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v - 5.5v, ta = - 40 to + 85 c) (v dd = 2.4v - 3.3v, ta = - 40 to + 85 c) (v dd = 4.5v - 5.5v, ta = - 40 to + 85 c) figure 24. serial interface characteristics item signal symbol min. typ. max. unit reset low pulse width resetb t rw 900 - - ns item signal symbol min. typ. max. unit reset low pulse width resetb t rw 450 - - ns figure 25. display control output timing item signal symbol min. typ. max. unit m delay time m t dm - 13 70 ns item signal symbol min. typ. max. unit m delay time m t dm - 10 35 ns t rw resetb t dm cl m
KS0713 65com/132seg driver & controller for 54 reference applications microprocessor interface figure 26. interfacing with the 6800-series (ps = ? h ? , mi = ? h ? ) figure 27. interfacing with the 8080-series (ps = ? h ? , mi = ? l ? ) figure 28. serial interface (ps = ? l ? , mi = ? h/l ? ) db7~db0 resetb v dd v dd rw e rs cs2 cs1b 6800-series microprocessor KS0713 cs1b cs2 rs e_rd rw_wr db7~db0 resetb mi ps db7~db0 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series microprocessor KS0713 cs1b cs2 rs e_rd rw_wr db7~db0 resetb mi ps resetb open v ss v ss or v dd sclk sid rs cs2 cs1b microprocessor KS0713 cs1b cs2 rs db7(sid) db6(sclk) resetb db5~db0 mi ps
65com/132seg driver & controller for stn lcd KS0713 55 connections between KS0713 and lcd panel single-chip structure (1/65 duty configurations) figure 29. single-chip structure (1/65 duty configurations) shl = 0, adc = 1 shl = 0, adc = 0 shl = 1, adc = 1 shl = 1, adc = 0 coms com64 : com33 com32 : com1 coms seg1 ........... seg132 KS0713 ( bottom view ) ? d ? ? ? a ? * 64 132 pixels com32 : com1 coms coms com64 : com33 seg132 ........... seg1 KS0713 ( top view ) ? d ? ? ? a ? * 64 132 pixels com33 : com64 coms coms com1 : com32 seg1 ........... seg132 KS0713 ( top view ) com33 : com64 coms coms com1 : com32 seg132 ............ seg1 KS0713 ( bottom view ) ? d ? ? ? a ? * 64 132 pixels ? d ? ? ? a ? * 64 132 pixels
KS0713 65com/132seg driver & controller for 56 single-chip structure (1/49 duty configurations) figure 30. single-chip structure (1/49 duty configurations) shl = 0, adc = 1 shl = 0, adc = 0 shl = 1, adc = 1 shl = 1, adc = 0 coms com64 : com41 com24 : com1 coms seg1 ........... seg132 KS0713 ( bottom view ) ? d ? ? ? a ? * 48 132 pixels com24 : com1 coms coms com64 : com41 seg132 ........... seg1 KS0713 ( top view ) ? d ? ? ? a ? * 48 132 pixels com41 : com64 coms coms com1 : com24 seg1 ............ seg132 KS0713 ( top view ) com41 : com64 coms coms com1 : com24 seg132 ............ seg1 KS0713 ( bottom view ) ? d ? ? ? a ? * 48 132 pixels ? d ? ? ? a ? * 48 132 pixels
65com/132seg driver & controller for stn lcd KS0713 57 single-chip structure (1/33 duty configurations) figure 31. single-chip structure (1/33 duty configurations) shl = 0, adc = 1 shl = 0, adc = 0 shl = 1, adc = 1 shl = 1, adc = 0 coms com64 : com49 com16 : com1 coms seg1 ........... seg132 KS0713 ( bottom view ) ? d ? ? ? a ? * 32 132 pixels com16 : com1 coms coms com64 : com49 seg132 ........... seg1 KS0713 ( top view ) ? d ? ? ? a ? * 32 132 pixels com49 : com64 coms coms com1 : com16 seg1 ............ seg132 KS0713 ( top view ) com49 : com64 coms coms com1 : com16 seg132 ............ seg1 KS0713 ( bottom view ) ? d ? ? ? a ? * 32 132 pixels ? d ? ? ? a ? * 32 132 pixels
KS0713 65com/132seg driver & controller for 58 multi-chip structure (1/65 duty configurations) figure 32. multi-chip structure shl = 0, adc = 1 shl = 0, adc = 0 shl = 1, adc = 1 shl = 1, adc = 0 coms com64 : com49 com16 : com1 coms seg1 ........... seg132 KS0713 ( bottom view ) ? d ? ? ? a ? * 32 132 pixels com16 : com1 coms coms com64 : com49 seg132 ........... seg1 KS0713 ( top view ) ? d ? ? ? a ? * 32 132 pixels com49 : com64 coms coms com1 : com16 seg1 ............ seg132 KS0713 ( top view ) com49 : com64 coms coms com1 : com16 seg132 ............ seg1 KS0713 ( bottom view ) ? d ? ? ? a ? * 32 132 pixels ? d ? ? ? a ? * 32 132 pixels
65com/132seg driver & controller for stn lcd KS0713 59 KS0713 tcp pin layout (sample) frs m cl disp cs1b cs2 resetb rs rw_wr e_rd db0 db1 db2 db3 db4 db5 db6 db7 duty0 duty1 ms cls mi ps v ss v dd vout c3+ c3- c1+ c1- c2+ c2- vr v0 v1 v2 v3 v4 bsts dcdc5b hpm intrs temps m frs com33 com34 com35 : : : com46 com47 com48 : : : com62 com63 com64 coms seg132 seg131 seg130 seg129 : : : : seg66 seg65 seg64 seg63 : : : : seg4 seg3 seg2 seg1 com32 com31 com30 : : : com17 com16 com15 : : : com3 com2 com1 coms KS0713 (top view)

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