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2.7 v to 5.5 v, seria l-input, voltage-output, 16-/12-bit nano dacs in lfcsp preliminary technical data ad5541a/ad5542a/AD5512A rev. pr a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features low power, 1 lsb inl nano dacs ad5541a: 16 bits ad5542a: 16 bits AD5512A: 12 bits 2.7 v to 5.5 v single-supply operation low glitch: 0.5 nv-s unbuffered voltage output capable of driving 60 k? loads directly v logic pin provides 1.8 v digital interface capability hardware clr and ldac functions 50 mhz spi-/qspi-/microwire-/dsp-compatible interface standards power-on reset clears dac output to zeroscale and midscale schmitt trigger inputs available in 3 mm 3 mm 16-lfcsp, 10-lfcsp, and 8-lfcsp also available in10-msop and 16-tssop applications automatic test equipment precision source-measure instruments data acquisition systems medical instrumentation aerospace instrumentation communications infrastructure equipment industrial control general description the ad5541a/ad5542a/AD5512A 1 are single, 16-/ 16-/ 12-bit, serial input, unbuffered voltage output digital-to-analog conver- ters (dacs) that operate from a single 2.7 v to 5.5 v supply. the ad5541a/ad5542a/AD5512A utilize a versatile 3-wire interface that is compatible with a 50 mhz spi, qspi?, microwire?, and dsp interface standards. these dacs provide 16-/12-bit performance without any adjust- ments. the dac output is unbuffered, which reduces power consumption and offset errors contributed to by an output buffer. the ad5542a/AD5512A can be operated in bipolar mode, which generates a v ref output swing. the ad5542a/AD5512A also includes kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. the ad5541a is available in 10-lead 3 mm 3 mm lfcsp and 10-lead mssop. the ad5541a-1 is available in 8-lead 3 mm 3 mm lfcsp. the ad5542a/AD5512A are available in 16-lead 3 mm 3 mm lfcsp and the ad5542a is also available in 16-lead tssop. the ad5542a-1 is available in 10-lead lfcsp. the ad5541a and ad5542a are specified over a temperature range of ?40c to 105c. functional block diagrams figure 1. ad5541a figure 2. ad5541a-1 figure 3. ad5542a
ad5541a/ad5542a/AD5512A preliminary technical data rev. p ra | page 2 of 24 figure 4. 1 all references to the ad5541a/a d5542a/AD5512A incorporate all models (see ordering guide) in cluding the ad5541a-1/ad5542a-1 un less specified.
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. p ra | page 3 of 24 table of contents features ............................................................................................... 1 ? applications ....................................................................................... 1 ? general description .......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ................................................................................ 3 ? specifications ..................................................................................... 4 ? timing characteristics ................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ............................ 7 ? typical performance characteristics .............................................. 9 ? terminology ..................................................................................... 12 ? theory of operation ....................................................................... 13 ? digital-to-analog section .......................................................... 13 ? serial interface ............................................................................. 13 ? unipolar output operation ....................................................... 13 ? bipolar output operation ......................................................... 14 ? output amplifier selection ....................................................... 14 ? force sense amplifier selection ............................................... 14 ? reference and ground ............................................................... 14 ? power-on reset ........................................................................... 15 ? power supply and reference bypassing ................................... 15 ? microprocessor interfacing ........................................................... 16 ? ad5541/ad5542 to adsp-2101/adsp-2103 interface ........ 16 ? ad5541/ad5542 to 68hc11/68l11 interface ....................... 16 ? ad5541/ad5542 to microwire interface ......................... 16 ? ad5541/ad5542 to 80c51/80l51 interface ........................... 16 ? applications information ............................................................... 17 ? optocoupler interface ................................................................ 17 ? decoding multiple ad5541/ad5542s..................................... 17 ? outline dimensions ........................................................................ 18 ? ordering guide ........................................................................... 21 ? revision history
ad5541a/ad5542a/AD5512A preliminary technical data rev. p ra | page 4 of 24 specifications v dd = 2.7 v to 5.5v, v ref = 2.5 v, agnd = dgnd = 0 v. ?40c < t a < +105c, unless otherwise noted. table 1. parameter min typ max unit test condition static performance ad5541a/ad5542a resolution 16 bits relative accuracy (inl) 0.5 1.0 lsb l, c grades 0.5 2.0 lsb b, j grades 0.5 4.0 lsb a grade differential nonlinearity (dnl) 0.5 1.0 lsb guaranteed monotonic 1.5 lsb j grade AD5512A resolution 12 bits relative accuracy (inl) 1.0 lsb differential nonlinearity (dnl) 1.0 lsb gain error ?1.5 5 lsb t a = 25c 7 lsb gain error temperature coefficient 0.1 ppm/c zero code error 0.3 1 lsb t a = 25c 2 lsb zero code temperature coefficient 0.05 ppm/c ad5542a/AD5512A bipolar resistor matching 1.000 ?/? r fb /r inv , typically r fb = r inv = 28 k? 0.0015 tbd % ratio error bipolar zero offset error 1 5 lsb t a = 25c 7 lsb bipolar zero temperature coefficient 0.2 ppm/c output characteristics output voltage range 0 v ref ? 1 lsb v unipolar operation ?v ref +v ref ? 1 lsb v ad5542 bipolar operation output voltage settling time 1 s to 1/2 lsb of fs, c l = 10 pf slew rate 25 v/s c l = 10 pf, measured from 0% to 63% digital-to-analog glitch impulse 0.5 nv-sec 1 lsb change around the major carry digital feedthrough 0.2 nv-sec all 1s loaded to dac, v ref = 2.5 v dac output impedance 6.25 k? tolerance typically 20% power supply rejection ratio 1.0 lsb ?v dd 10% dac reference input reference input range 2.0 v dd v reference input resistance 1 9 k? unipolar operation 7.5 k? ad5542, bipolar operation logic inputs input current 1 a input low voltage, v inl 0.8 v v dd = 2.7 v to 5.5 v input high voltage, v inh 2.0 v v dd = 4.5 v to 5.5 v input high voltage, v inh 1.8 v v dd = 2.7 v to 3.6 v input capacitance 2 10 pf hysteresis voltage 2 0.15 v reference reference ?3 db bandwidth 1.3 mhz all 1s loaded reference feedthrough 1 mv p-p all 0s loaded, v ref = 1 v p-p at 100 khz thd tbd db signal-to-noise ratio 92 db reference input capacitance 75 pf code 0x0000 120 pf code 0xffff
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. p ra | page 5 of 24 parameter min typ max unit test condition power requirements v dd 2.7 5.5 v i dd 200 tbd a v logic 1.8 5.5 v i logic 200 tbd a power dissipation 1.5 tbd mw 1 reference input resistance is code-dependent, minimum at 0x8555. 2 guaranteed by design, not subject to production test. timing characteristics v logic = 1.8 v to 5.5 v v, v dd = 5v, v ref = 2.5 v, v inh = 90% of v logic , v inl = 10% of v logic , agnd = dgnd = 0 v; ?40c < t a < +105c, unless otherwise noted. table 2. parameter 1, 2 limit unit description f sclk 50 mhz max sclk cycle frequency t 1 20 ns min sclk cycle time t 2 10 ns min sclk high time t 3 10 ns min sclk low time t 4 5 ns min cs low to sclk high setup t 5 7 ns min cs high to sclk high setup t 6 15 ns min sclk high to cs low hold time t 7 10 ns min sclk high to cs high hold time t 8 7 ns min data setup time t 9 5 ns min data hold time (v inh = 90% of v dd , v inl = 10% of v dd ) t 9 5 ns min data hold time (v inh = 3v, v inl = 0 v) t 10 15 ns min ldac pulsewidth t 11 15 ns min cs high to ldac low setup t 12 15 ns min cs high time between active periods t 13 15 ns min clr pulsewidth 1 guaranteed by design and characterization. not production tested 2 all input signals are specified with t r = t f = 1 ns/v and timed from a voltage level of (v inl + v inh )/2. figure 5. timing diagram
ad5541a/ad5542a/AD5512A preliminary technical data rev. p ra | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +6 v digital input voltage to dgnd ?0.3 v to v dd + 0.3 v v out to agnd ?0.3 v to v dd + 0.3 v agnd, agndf, agnds to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 10 ma operating temperature range industrial (a, b, c versions) ?40c to +85c commercial (j, l versions) 0c to 70c storage temperature range ?65c to +150c maximum junction temperature (t j max) 150c package power dissipation (t j max ? t a )/ ja thermal impedance, ja soic (r-8) 149.5c/w soic (r-14) 104.5c/w lead temperature, soldering peak temperature 1 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 as per jedec standard 20.
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. p ra | page 7 of 24 pin configurations and function descriptions nc = no connect top view 3 sclk 4 din 1 ref 2 cs 6vout 5clr 8gnd 7vdd 00000-000 ad5541a-1 (not to scale) figure 6. ad5541a-1 8-lead lfcsp pin configuration v out 1 a gnd 2 ref 3 cs 4 v dd 8 dgnd 7 din 6 sclk 5 ad5541a top view (not to scale) 07557-004 figure 7. ad5541a 8-lead soic pin configuration nc = no connect 1v dd 2v out 3a gnd 4 ref 5 cs 10 vlo g ic 9dgnd 8ldac 7din 6sclk top view 00000-000 ad5541a (not to scale) figure 8. ad5541a 10-lead lfcsp pin configuration nc = no connect vdd 1 vout 2 agnd 3 ref 4 cs 5 vlogic 10 dgnd 9 ldac 8 din 7 sclk 6 ad5541a top view (not to scale) figure 9. ad5541a 10-lead msop pin configuration table 4. ad5541a pin fu nction descriptions pin no. 8-lead lfcsp 8-lead soic 10-lead lfcsp 10-lead msop mnemonic description 6 1 2 2 vout analog output voltage from the dac. 2 3 3 agnd ground reference point for analog circuitry. 1 3 4 4 ref voltage reference input for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 2 4 5 5 cs logic input signal. the chip select signal is used to frame the serial data input. 3 5 6 6 sclk clock input. data is clocked into the inp ut register on the rising edge of sclk. duty cycle must be between 40% and 60%. 4 6 7 7 din serial data input. this device accepts 16-bit words. data is clocked into the input register on the rising edge of sclk. 7 9 9 dgnd digital ground. ground reference for digital circuitry. 7 8 1 1 vdd analog supply voltage, 5 v 10%. 5 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are cleared to the model selectable midscale or zeroscale . 10 10 vlogic logic power supply. 8 8 ldac ldac input. when this input is taken low, the dac register is simultaneously updated with the contents of the input register.
ad5541a/ad5542a/AD5512A preliminary technical data rev. p ra | page 8 of 24 figure 10. ad5542a-1 10-lead lfcsp pin configuration 07557-005 rfb 1 v out 2 agndf 3 agnds 4 v dd 14 inv 13 dgnd 12 ldac 11 refs 5 din 10 reff 6 nc 9 cs 7 sclk 8 nc = no connect ad5542a top view (not to scale) figure 11. ad5542 14-lead soic pin configuration nc = no connect 1 2 3 4 5 6 7 8 vout agndf agnds nc reff refs rfb cs 16 15 14 13 12 11 10 9 vlogic inv dgnd din sclk clr ldac vdd a d 5542a top view (not to scale) figure 12. ad5542a 16-lead tssop pin configuration 00000-000 12 11 10 1 3 4 dgnd ldac clr 9 din vout agnds 2 agndf refs 6 cs 5 reff 7 nc 8 sc lk 16 rfb 15 vdd 14 vlogic 13 in v top view ad5542a AD5512A nc = no connect (not to scale) figure 13. ad5542a 16-lead lfcsp pin configuration table 5. ad5542a/AD5512A pi n function descriptions pin no. 10-lead lfcsp 14-lead soic 16-lead tssop 16-lead lfcsp mnemonic description 8 1 1 16 rfb feedback resistor pin. in bipolar mode, connect this pin to the external op amp output. 6 2 2 1 vout analog output voltage from the dac. 3 3 2 agndf ground reference point for analog circuitry (force). 4 4 3 agnds ground reference point for analog circuitry (sense). 5 5 4 refs voltage reference input (sense) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 6 6 5 reff voltage reference input (force) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 2 7 8 6 cs logic input signal. the chip select sign al is used to frame the serial data input. 3 8 9 8 sclk clock input. data is clocked into the inp ut register on the rising edge of sclk. duty cycle must be between 40% and 60%. 5 11 10 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are cleared to the model selectable midscale or zeroscale . 4 10 10 9 din serial data input. this device accepts 16-bit words. data is clocked into the input register on the rising edge of sclk. 11 12 11 ldac ldac input. when this input is taken low, the dac register is simultaneously updated with the contents of the input register. 12 13 12 dgnd digital ground. ground reference for digital circuitry. 7 13 14 13 inv connected to the internal scaling resistors of the dac. connect the inv pin to external op amps inverting input in bipolar mode. 9 14 16 15 vdd analog supply voltage, 5 v 10%. 15 14 vlogic logic power supply.
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. p ra | page 9 of 24 typical performance characteristics figure 14. integral nonlinearity vs. code figure 15. integral nonlinearity vs. temperature figure 16. linearity error vs. supply voltage figure 17. differential nonlinearity vs. code figure 18. differential nonlinearity vs. temperature figure 19. linearity error vs. reference voltage
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 10 of 24 figure 20. gain error vs. temperature figure 21. supply current vs. temperature figure 22. supply current vs. digital input voltage figure 23. zero-code error vs. temperature figure 24. supply current vs. reference voltage or supply voltage figure 25. reference current vs. code
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. pra | page 11 of 24 figure 26. digital feedthrough figure 27. digital-to-analog glitch impulse figure 28. large signal settling time figure 29. small signal settling time
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 12 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or inl is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 14. differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures mono- tonicity. a typical dnl vs. code plot is shown in figure 17. gain error gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. it is the deviation in slope of the dac transfer characteristic from ideal. gain error temperature coefficient gain error temperature coefficient is a measure of the change in gain error with changes in temperature. it is expressed in ppm/c. zero code error zero code error is a measure of the output error when zero code is loaded to the dac register. zero code temperature coefficient this is a measure of the change in zero code error with a change in temperature. it is expressed in mv/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by 1 lsb at the major carry transition. a digital-to-analog glitch impulse plot is shown in figure 27. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but it is measured when the dac output is not updated. cs is held high while the clk and din signals are toggled. it is specified in nv-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. a typical digital feedthrough plot is shown in figure 26. power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the power supply voltage. power-supply rejection ratio is quoted in terms of percent change in output per percent change in v dd for full-scale output of the dac. v dd is varied by 10%. reference feedthrough reference feedthrough is a measure of the feedthrough from the v ref input to the dac output when the dac is loaded with all 0s. a 100 khz, 1 v p-p is applied to v ref . reference feedthrough is expressed in mv p-p.
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. pra | page 13 of 24 theory of operation the ad5541a/ad5542a/AD5512A are single, 16-bit, serial input, voltage output dacs. they operate from a single supply ranging from 2.7 v to 5 v and consume typically 300 a with a supply of 5 v. data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. to ensure a known power-up state, these parts are designed with a power-on reset function. in unipolar mode, the output is reset to 0 v; in bipolar mode, the ad5542 output is set to ?v ref . kelvin sense connections for the reference and analog ground are included on the ad5542. digital-to-analog section the dac architecture consists of two matched dac sections. a simplified circuit diagram is shown in figure 30. the dac architecture of the ad5541/ad5542 is segmented. the four msbs of the 16-bit data-word are decoded to drive 15 switches, e1 to e15. each switch connects one of 15 matched resistors to either agnd or v ref . the remaining 12 bits of the data-word drive switches s0 to s11 of a 12-bit voltage mode r-2r ladder network. 2r . . . . . s1 . . . . . 2r s11 2r e1 2r . . . . . e2 . . . . . 2r 2r s0 2r e15 r r v ref v out 12-bit r-2r ladder four msbs decoded into 15 equal segments 07557-022 figure 30. dac architecture with this type of dac configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. the output voltage is dependent on the reference voltage, as shown in the following equation: n ref out dv v 2 = where: d is the decimal data-word loaded to the dac register. n is the resolution of the dac. for a reference of 2.5 v, the equation simplifies to the following: 536,65 5.2 d v out = this gives a v out of 1.25 v with midscale loaded, and 2.5 v with full-scale loaded to the dac. the lsb size is v ref /65,536. serial interface the ad5541/ad5542 are controlled by a versatile 3- or 4-wire serial interface that operates at clock rates up to 25 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. the timing diagram is shown in figure 5. input data is framed by the chip select input, cs . after a high-to-low transition on cs , data is shifted synchronously and latched into the input register on the rising edge of the serial clock, sclk. data is loaded msb first in 16-bit words. after 16 data bits have been loaded into the serial input register, a low-to-high transition on cs transfers the contents of the shift register to the dac. data can be loaded to the part only while cs is low. the ad5542 has an ldac function that allows the dac latch to be updated asynchronously by bringing ldac low after cs goes high. ldac should be maintained high while data is written to the shift register. alternatively, ldac can be tied perma- nently low to update the dac synchronously. with ldac tied permanently low, the rising edge of cs loads the data to the dac. unipolar output operation these dacs are capable of driving unbuffered loads of 60 k?. unbuffered operation results in low supply current, typically 300 a, and a low offset error. the ad5541 provides a unipolar output swing ranging from 0 v to v ref . the ad5542 can be configured to output both unipolar and bipolar voltages. figure 31 shows a typical unipolar output voltage circuit. the code table for this mode of operation is shown in table 6. 07557-023 out refs* ref(reff*) dgnd agnd v dd din sclk ldac* cs ad5541/ad5542 ad820/ op196 + 0.1f 0.1f 10f unipolar output external op amp 2.5 v 5v serial interface *ad5542 only. figure 31. unipolar output tale 6. unipolar code tale dac latch contents msb lsb analog output 1111 1111 1111 1111 v ref (65,535/65,536) 1000 0000 0000 0000 v ref (32,768/65,536) = ? v ref 0000 0000 0000 0001 v ref (1/65,536) 0000 0000 0000 0000 0 v
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 14 of 24 assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation: ( ) inlvvv d v zse ge ref uniout +++= ? 16 2 where: v out?uni is unipolar mode worst-case output. d is code loaded to dac. v ref is reference voltage applied to the part. v ge is gain error in volts. v zse is zero scale error in volts. inl is integral nonlinearity in volts. bipolar output operation with the aid of an external op amp, the ad5542 can be confi- gured to provide a bipolar voltage output. a typical circuit of such operation is shown in figure 32. the matched bipolar offset resistors, r fb and r inv , are connected to an external op amp to achieve this bipolar output swing, typically r fb = r inv = 28 k?. table 7 shows the transfer function for this output operating mode. also provided on the ad5542 are a set of kelvin connections to the analog ground inputs. 07557-024 out refs reff inv r fb r inv dgnd agndf v dd din sclk ldac cs ad5541/ad5542 agnds + 0.1f 0.1f 10f unipolar output external op amp +2.5 v +5 v +5v ?5v serial interface rfb figure 32. bipolar output (ad5542 only) tale 7. bipolar code tale dac latch contents msb lsb analog output 1111 1111 1111 1111 +v ref (32,767/32,768) 1000 0000 0000 0001 +v ref (1/32,768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 ?v ref (1/32,768) 0000 0000 0000 0000 ?v ref (32,768/32,768) = ?v ref assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation: ( ) ( ) ( ) [ ] () a rd rdvrdv v v ref os uniout bipout ++ +?++ = ? ? 21 1 2 where: v out-bip is the bipolar mode worst-case output v out?uni is the unipolar mode worst-case output. v os is the external op amp input offset voltage. rd is the r fb and r inv resistor matching error. a is the op amp open-loop gain. output amplifier selection for bipolar mode, a precision amplifier should be used and supplied from a dual power supply. this provides the v ref output. in a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case, agnd. this can result in some degradation of the specified performance unless the application does not use codes near zero. the selected op amp needs to have a very low-offset voltage (the dac lsb is 38 v with a 2.5 v reference) to eliminate the need for output offset trims. input bias current should also be very low because the bias current, multiplied by the dac output impedance (approximately 6 k), adds to the zero code error. rail-to-rail input and output performance is required. for fast settling, the slew rate of the op amp should not impede the settling time of the dac. output impedance of the dac is constant and code-independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. the amplifier should also have a 3 db bandwidth of 1 mhz or greater. the amplifier adds another time constant to the system, thus increasing the settling time of the output. a higher 3 db amplifier bandwidth results in a shorter effective settling time of the combined dac and amplifier. force sense amplifier selection use single-supply, low-noise amplifiers. a low-output impedance at high frequencies is preferred because the amplifiers need to be able to handle dynamic currents of up to 20 ma. reference and ground because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. the ad5541/ ad5542 operate with a voltage reference ranging from 2 v to v dd . references below 2 v result in reduced accuracy. the full- scale output voltage of the dac is determined by the reference. table 6 and table 7 outline the analog output voltage or partic- ular digital codes. for optimum performance, kelvin sense connections are provided on the ad5542. if the application doesnt require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die.
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. pra | page 15 of 24 power-on reset the ad5541/ad5542 have a power-on reset function to ensure that the output is at a known state on power-up. on power-up, the dac register contains all 0s until the data is loaded from the serial register. however, the serial register is not cleared on power-up, so its contents are undefined. when loading data initially to the dac, 16 bits or more should be loaded to prevent erroneous data appearing on the output. if more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. if the ad5541/ ad5542 need to be interfaced with data shorter than 16 bits, the data should be padded with 0s at the lsbs. power supply and reference bypassing for accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor.
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 16 of 24 microprocessor interfacing microprocessor interfacing to the ad5541/ad5542 is via a serial bus that uses standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal and a synchronization signal. the ad5541/ad5542 require a 16-bit data-word with data valid on the rising edge of sclk. the dac update can be done automatically when all the data is clocked in or it can be done under control of the ldac (ad5542 only). ad5541/ad5542 to adsp-2101/adsp-2103 interface figure 33 shows a serial interface between the ad5541/ad5542 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 are programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. as the data is clocked out on each rising edge of the serial clock, an inverter is required between the dsp and the dac, because the ad5541/ad5542 clock data in on the falling edge of the sclk. ldac** cs din sclk fo tfs dt sclk ad5541/ ad5542* adsp-2101/ adsp-2103* *additional pins omitted for clarity. **ad5542 on ly. 07557-025 figure 33. ad5541/ad5542 to adsp-2101/adsp-2103 interface ad5541/ad5542 to 68hc11/68l11 interface figure 34 shows a serial interface between the ad5541/ad5542 and the 68hc11/68l11 microcontroller. sck of the 68hc11/ 68l11 drives the sclk of the dac, and the mosi output drives the serial data line serial din. the cs signal is driven from one of the port lines. the 68hc11/68l11 is configured for master mode: mstr = 1, cpol = 0, and cpha = 0. data appearing on the mosi output is valid on the rising edge of sck. ldac** cs din sclk pc6 pc7 mosi sck ad5541/ ad5542* 68hc11/ 68l11* *additional pins omitted for clarity. **ad5542 on ly. 07557-026 figure 34. ad5541/ad5542 to 68hc11/68l11 interface ad5541/ad5542 to microwire interface figure 35 shows an interface between the ad5541/ad5542 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and into the ad5541/ ad5542 on the rising edge of the serial clock. no glue logic is required because the dac clocks data into the input shift register on the rising edge. din sclk so sclk ad5541/ ad5542* microwire* * addition a l pins omitted for clarity. 07557-027 cs cs figure 35. ad5541/ad5542 to microwire interface ad5541/ad5542 to 80c51/80l51 interface a serial interface between the ad5541/ad5542 and the 80c51/ 80l51 microcontroller is shown in figure 36. txd of the micro- controller drives the sclk of the ad5541/ad5542, and rxd drives the serial data line of the dac. p3.3 is a bit programmable pin on the serial port that is used to drive cs . the 80c51/80l51 provide the lsb first, whereas the ad5541/ ad5542 expects the msb of the 16-bit word first. care should be taken to ensure the transmit routine takes this into account. when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is valid on the falling edge of txd, so the clock must be inverted as the dac clocks data into the input shift register on the rising edge of the serial clock. the 80c51/80l51 transmit data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. as the dac requires a 16-bit word, p3.3 must be left low after the first eight bits are transferred, and brought high after the second byte is transferred. ldac on the ad5542 can also be controlled by the 80c51/ 80l51 serial port output by using another bit programmable pin, p3.4. ldac** cs din sclk p3.4 p3.3 rxd txd ad5541/ ad5542* 80c51/ 80l51* *additional pins omitted for clarity. **ad5542 on ly. 07557-028 figure 36. ad5541/ad5542 to 80c51/80l51 interface
preliminary technical data ad5541a/ad5542a/AD5512Aa rev. pra | page 17 of 24 applications information optocoupler interface the digital inputs of the ad5541a/ad5542a/AD5512A are schmitt-triggered so that they can accept slow transitions on the digital input lines. this makes these parts ideal for industrial applications where it may be necessary to isolate the dac from the controller via optocouplers. figure 37 illustrates such an interface. 10k ? 10f 0.1f v dd v out v dd sclk power 10k ? v dd cs cs din gnd sclk 10k ? v dd din 5v regulator ad5541/ad5542 07557-029 figure 37. ad5541/ad5542 in an optocoupler interface decoding multiple ad5541/ad5542s the cs pin of the ad5541/ad5542 can be used to select one of a number of dacs. all devices receive the same serial clock and serial data, but only one device receives the cs signal at any one time. the dac addressed is determined by the decoder. there is some digital feedthrough from the digital input lines. using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. figure 38 shows a typical circuit. ad5541/ad5542 cs din sclk v out ad5541/ad5542 cs din sclk v out ad5541/ad5542 cs din sclk v out ad5541/ad5542 cs din sclk v out v dd dgnd en coded address sclk din enable decoder 07557-030 figure 38. addressing multiple ad5541/ad5542s
rev. pra | page 18 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 39. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters. 101207-b top view 10 1 6 5 0.30 0.23 0.18 exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 1 9 ) figure 40. 10-lead lead frame chip scale package [lfcsp] (cp-10-9) dimensions shown in millimeters.
rev. pra | page 19 of 24 041608-b top view 8 1 5 4 0.35 0.30 0.25 exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.65 bsc p i n 1 i n d i c a t o r ( r 0 . 2 ) figure 41. 8-lead lead frame chip scale package [lfcsp] (cp-8-3) dimensions shown in millimeters. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 42. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters.
rev. pra | page 20 of 24 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.55 020509-b 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator 0.80 0.75 0.70 compliant to jedec standards mo-220-weed. figure 43. 16-lead lead frame chip scale package [lfcsp] (cp-16-22) dimensions shown in millimeters.
rev. pra | page 21 of 24 ordering guide model inl dnl clear to code temperature range package description package option ad5541abrmz 1 lsb 1 lsb midscale ?40c to +105c 10-lead msop rm-10 ad5541aarmz 2 lsb 1 lsb midscale ?40c to +105c 10-lead msop rm-10 ad5541abcpz 1 lsb 1 lsb midscale ?40c to +105c 10-lead lfcsp cp-10-9 ad5541aacpz 2 lsb 1 lsb midscale ?40c to +105c 10-lead lfcsp cp-10-9 ad5541abcpz-1 1 lsb 1 lsb zero-scale ?40c to +105c 8-lead lfcsp cp_8-3 ad5542abruz 1 lsb 1 lsb midscale ?40c to +105c 16-lead tssop ru-16 ad5542aaruz 2 lsb 1 lsb midscale ?40c to +105c 16-lead tssop ru-16 ad5542asruz 1 lsb 1 lsb midscale ?55c to +125c 16-lead tssop ru-16 ad5542abcpz 1 lsb 1 lsb midscale ?40c to +105c 16-lead lfcsp cp-16-22 ad5542aacpz 2 lsb 1 lsb midscale ?40c to +105c 16-lead lfcsp cp-16-22 ad5442abcpz-1 1 lsb 1 lsb midscale ?40c to +105c 10-lead lfcsp cp-10-9 AD5512Aacpz 1 lsb 1 lsb midscale ?40c to +105c 16-lead lfcsp cp-16-22
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 22 of 24 notes
preliminary technical data ad5541a/ad5542a/AD5512A rev. pra | page 23 of 24 notes
ad5541a/ad5542a/AD5512A preliminary technical data rev. pra | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr08516-0-12/09(pra)

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