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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. february 2006 rev1 1/55 1 STW8009 stw8019 mobile video denc features two analog outputs (10 bits dac) with: ? cvbs (composite) output or y/c (s-vhs) ? ntsc-m & 4.43 & pal-bdghi, n, m support ? 35 ma current driver 8-bit digital interface input supporting both embedded and external synchro ? ccir 601 / ycbcr 4:2:2 format ? ccir 656: 27 mhz pixel input clock latest macrovision (7.1.l1) (stw8019 only) 2-wire serial mpu interface (i2c compatible) master and slave modes tv / vcr plug insertion detection supply voltages ? 2.8v/3.3v analog ? 1.8 v digital i/o ?1.2v for core power consumption ? sleep mode: 5 w ? standby mode: 150 w maximum ? cvbs: 125 mw ? y/c: 245 mw package ? tfbga 4x4x1.2 mm height, 0.5 mm pitch, ? vfbga 3x3x1 mm height, 0.4 mm pitch ? tqfp64 also available full matrix: 7 x 7 description STW8009/stw8019 is aimed at mobile video digital encoder (denc). this device converts digital video signals into high quality analog signal compliant with tv standards, it is able to encode interlaced (in all standards) and non-interlaced (in pal and ntsc). featuring ultra low power consumption, it suits perfectly mobile appliances that interface occasionally with tv sets or vcrs. it is also the ideal companion for digital application processors such as st?s nomadik family. to minimize pcb space usage, STW8009/stw8019 features a high level of integration. STW8009/stw8019 drives directly the video input, cvbs of a tv set or the y/c video input of a vcr through optional esd protection devices. the 27 mhz clock and the device power management are controlled through the digital processor interface [porn, suspend and 2-wire i2c compatible serial mpu]. this digital processor interface also controls the STW8009/stw8019 operating modes (off, sleep, standby and active). applications mobile video digital encoder (denc) order codes part number package STW8009a tfbga49 stw8019a tfbga49 STW8009bs3 vfbga49 stw8019bs3 vfbga49 STW8009 tfbga 4 mm x 4 mm x 1.2 mm vfbga 3 mm x 3 mm x 1.0 mm www.st.com
contents STW8009/stw8019 2/55 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 ball/pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 master & slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 auto test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 input demultiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 sub-carrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 luminance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7 chrominance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.8 composite video signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.9 macrovisiontm copy protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10 tv/vcr plug insertion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.11 dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12.2 mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.13 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 denc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.2 control & power management unit registers . . . . . . . . . . . . . . . . . . . . . 40 6 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 2 wire serial mpu control interface (i2c compatible) . . . . . . . . . . . . . . . . 42 7-bit address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 bits address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STW8009/stw8019 contents 3/55 6.2 ycbcr bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1 tfbga 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2 vfbga 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
list of tables STW8009/stw8019 4/55 list of tables table 1. product name ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. std1, std0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. sync2, sync1, sync0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. valrst1 and valrst0 selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. syncin_ad[1:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. syncout_ad[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. jump, dec_ninc, free_jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. cfc[1:0]: colour frequency control via cfc line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. ph_rst_mode[1:0]:sub-carrier phase reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. dac1_mult[5:0]: multiplying factor on dac1_y digital signal . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. c_mult[3:0]: multiplying factor of c digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. chroma main_coef_[8:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. main_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. luma_coef_[0:9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. dac12_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. dac2_multi[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. main_chr_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. STW8009/stw8019 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 21. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. 2 wire serial mpu control interface timing ( figure 15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 24. digital i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 25. ycbcr data bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. power consumption/r load = 37.5 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. dac & video output characteristics / rload = 37.5 ohms ? f = 27 mhz ? rext = 2.4 k ? . 48 table 28. tfbga 4x4x1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. vfbga 3x3x1.0 mm - 49 balls - pitch 0.4 ball 0.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
STW8009/stw8019 list of figures 5/55 list of figures figure 1. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. STW8009 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. stw8019 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. ball layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. luma filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. luma filtering with 3.58 mhz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. luma filtering with 4.43 mhz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. 1.1 mhz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. 1.3 mhz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. 1.6 mhz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. 1.9 mhz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. 2-wire serial mpu control interface format (i2c compatible) / 7-bit addresses. . . . . . . . . . 43 figure 14. 2-wire serial mpu control interface format (i2c compatible) / 10-bit addresses. . . . . . . . . 44 figure 15. 2-wire serial mpu control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. ycbcr bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18. tfbga 49 balls 4 x 4 x 1.2 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19. vfbga 49 balls 3 x 3 x 1.0 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
overview STW8009/stw8019 6/55 1 overview STW8009/stw8019 is aimed at mobile video digital encoder (denc). this device converts digital video signals into high quality analog signal compliant with tv standards, it is able to encode interlaced (in all standards) and non-interlaced (in pal and ntsc). featuring ultra low power consumption, it suits perfectly mobile appliances that interface occasionally with tv sets or vcrs. it is also the ideal companion for digital application processors such as st?s nomadik family. to minimize pcb space usage, the device features a high level of integration. the 35 ma high performance dac allows direct drive of 37.5 ? load. STW8009/stw8019 drives directly the video input, cvbs of a tv set or the y/c video input of a vcr through optional esd protection devices. it is powered by three voltage supplies, 2.8/3.3 v, 1.8 v and 1.2 v (vcca, vi/o, vdd). the 27 mhz clock and the device power management are controlled through the digital processor interface [porn, suspend and 2-wire i2c compatible serial mpu]. this digital processor interface also controls the operating modes (off, sleep, standby and active). figure 1. application diagram naming convention unless clearly specified in the document, STW8009/stw8019 stands for both STW8009 and stw8019. video digital processor stw80x9 clk tv set or vcr supply vdd vo vcca ycbcr porn i2c suspend vdd vo vcca c/cvbs y esd protection 75 ? 75 ?
STW8009/stw8019 functional block diagram 7/55 2 functional block diagram figure 2. STW8009 block diagram figure 3. stw8019 block diagram
ball/pin information STW8009/stw8019 8/55 3 ball/pin information table 1. product name ball functions ball name type voltage description e1 vdd power 1.2 v digital core chip supply d2 gndd gnd 0 v digital core chip ground c1 vdd_io1 power 1.8 v digital i/o supply d1 vss_io1 gnd 0 v digital i/o ground g4 vdd_io2 power 1.8 v digital i/o supply e4 vss_io2 gnd 0 v digital i/o ground a3 vcca1 power 2.8 /3.3v dac1 matrix analog power supply a5 vcca2 power 2.8 /3.3 v dac2 matrix analog power supply a7 vcca3 power 2.8 /3.3 v 2.8/3.3 v digital feature supply b7 vcca4 power 2.8 /3.3 v 2.8 /3.3 v digital feature supply b3 gnda1 gnd 0 v dac1 ground b5 gnda2 gnd 0 v dac2 ground c5 gnda3 gnd 0 v 2.8 /3.3 v digital feature ground b4 gnda4 gnd 0 v rext ground connection b6 gnda5 gnd 0 v analog ground a4 rext analog dac current reference setting g2 clk digital input 1.8 v 27 mhz master pixel clock (pixclk) g7, g6, f7, f6, e7, e6, d7, d6 ycbcr[0:7] digital input 1.8 v time multiplexed 4:2:2 luminance and chrominance data as defined in ccir 601 and ccir 656 (excepted for ttl input signals) g5 hsync digital i/o 1.8 v horizontal synchronization signal: - input in slave mode, except when sync is extracted from ycbcr data - output in master mode and when sync is extracted from ycbcr signal. f5 vsync odd/even digital i/o 1.8 v vertical synchronization ? odd/even signal: - input in slave mode, except when sync is extracted from ycbcr data - output in master mode and when sync is extracted from ycbcr signal. f3 sda digital i/o 1.8 v 2 wire serial mpu data line g3 scl digital input 1.8 v 2 wire serial mpu clock e3 add digital input 1.8 v device address selection c7 porn digital input 1.8 v power on reset (active low) f2 suspend digital input 1.8 v suspend input
STW8009/stw8019 ball/pin information 9/55 figure 4. ball layout a2 c/cvbs analog output the output can be selected to be composite video or chroma signal for s-video. a6 y analog output luminance signal for s-video b1 tdi digital input 1.8 v jtag test data in b2 tdo digital output 1.8 v jtag test data out c2 tck digital input 1.8 v jtag test clock c3 tms digital input 1.8 v jtag test mode select d4 test digital input 1.8 v put the device in test mode d3, f1, e2 tst_ana[0:2] digital output 1.8 v denc test f4 plugdet digital input 1.8 v tv / vcr plug connection detection / cmos input table 1. product name ball functions gnda3 rext vcca4 a b c e f d g 1234567 vcca2 y gnda2 c/cvbs gnda4 vcca3 gnda5 suspend clk vdd_io1 vcca1 gnda1 test ycbcr[7] ycbcr[6] ycbcr[4] ycbcr[2] ycbcr[3] ycbcr[0] ycbcr[1] ycbcr[5] vss_io1 tdi tck tdo vdd tms tst_ana[0] tst_ana[2] tst_ana[1] sda gndd add hsync scl vdd_io2 vss_io2 vsync porn plugdet gnda3 rext vcca4 a b c e f d g 1234567 vcca2 y gnda2 c/cvbs gnda4 vcca3 gnda5 suspend clk vdd_io1 vcca1 gnda1 test ycbcr[7] ycbcr[6] ycbcr[4] ycbcr[2] ycbcr[3] ycbcr[0] ycbcr[1] ycbcr[5] vss_io1 tdi tck tdo vdd tms tst_ana[0] tst_ana[2] tst_ana[1] sda gndd add hsync scl vdd_io2 vss_io2 vsync porn plugdet
functional description STW8009/stw8019 10/55 4 functional description 4.1 general STW8009/stw8019 operates either in master mode where it supplies all sync signal or in slave mode. the digital input is an 8-bit bus carrying y, cb and cr at 13.5 mhz. input samples are latched in on the rising edge of the clock input signal. STW8009/stw8019 is able to encode interlaced (in all standards) and non interlaced (in pal and ntsc) video. STW8009/stw8019 outputs interlaced or non-interlaced video in pal-b,d,g,h,i,pal-n,pal- m or ntsc-m standards (?ntsc-4.43? is also possible). the burst sequences are internally generated, subcarrier generation being performed numerically with the 27 mhz as reference. 4-frame bursts are generated for pal or 2-frame bursts for ntsc. rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant itu_r and smpte recommendations. 4.2 master & slave modes in master mode, STW8009/stw8019 supplies hsync and odd/even sync signals (with independently programmable polarities) to drive other blocks. STW8009/stw8019 starts encoding and counting clock cycles as soon as the master mode has been loaded into the control register (reg 0). configuration bits ?syncout_ad[1:0]? (reg 4) allow to shift the relative position of the sync signals by up to 3 clock cycles to cope with any ycbcr phasing. in slave modes, several modes are available, odd/even+hsync based, vsync+hsync based, odd/even-only based, vsync-only based or sync-in-data based. 4.3 auto test mode an auto test mode is available, which causes STW8009/stw8019 to produce a color bar pattern, in the appropriate standard, independently from the video input. 4.4 input demultiplexor the incoming ycbcr 4:2:2 data are demultiplexed into chroma information stream, a ?blue- difference? and a ?red-difference?, and a luma information stream. incoming data bits are treated as blue, red or luma samples according to their relative position with respect to the sync signals. brightness, saturation and contrast are then performed on demultiplexed data. the itu-r601 recommendation defines the black luma level as y=16dec and the maximum white luma level as y=235dec. similarly it defines 255 quantification levels for the color difference components (cr, cb) centered around 128. accordingly, incoming ycbcr samples can be saturated. in this case STW8009/stw8019 provides a saturation limitation feature to avoid having heavily saturated signal before digital to analog conversion and to avoid generating a distorted signal at STW8009/stw8019 cvbs or y/c outputs.
STW8009/stw8019 functional description 11/55 4.5 sub-carrier generation a direct digital frequency synthesizer (ddfs) generates the required color sub-carrier frequency using a 24-bit phase accumulator. sub-carrier frequency is programmable with a 1.6 hz step. 4.6 luminance encoding the luminance that is added to the chrominance to create the composite cvbs signal can be trap-filtered at 3.58 mhz (ntsc) or 4.43 mhz (pal). this supports application oriented towards low-end tv sets which are subject to cross-color. a 7.5 ire pedestal can be programmed if needed with all standards. this allows in particular to encode argentinian and non-argentinian pal-n, or japanese ntsc. a programmable delay can be inserted on the luminance path to offset any chroma/luma delay introduced by off-chip filtering. STW8009/stw8019 output signals are if modulated in ntsc m standard so that a sound notch filter is required. the notch filter which is on the luma path is defined by a set of coefficients and is implemented in the STW8009/stw8019 as default values. the set is also programmable. figure 5. luma filtering amplitude (db) frequency (mhz)
functional description STW8009/stw8019 12/55 figure 6. luma filtering with 3.58 mhz trap figure 7. luma filtering with 4.43 mhz trap 4.7 chrominance encoding chroma components are computed from demultiplexed cb, cr samples. before modulating the subcarrier, the chroma components are band-limited and interpolated at pixel clock rate. a set of 4 different filters is available for chroma filtering to suit a wide variety of applications in the different standards and filters recommended by itu-r 624-4 and smpte170-m. the available ?3db bandwidths are 1.1, 1.3, 1.6 and 1.9 mhz. narrow bandwidths are useful against cross-luminance artifacts while wide bandwidths allow to keep higher chroma contents. frequency (mhz) frequency (mhz)
STW8009/stw8019 functional description 13/55 figure 8. 1.1 mhz chroma filter figure 9. 1.3 mhz chroma filter figure 10. 1.6 mhz chroma filter amplitude (db) frequency (mhz) amplitude (db) frequency (mhz) amplitude (db) frequency (mhz)
functional description STW8009/stw8019 14/55 figure 11. 1.9 mhz chroma filter 4.8 composite video signal generation the composite video signal is created by adding the luminance and the chrominance components. a saturation function is included in the adder to avoid overflow errors. 4.9 macrovision tm copy protection stw8019 provides macrovision tm copy protection rev 7.1.l1 feature. 4.10 tv/vcr plug insertion detection plugdet ball is used to detect the connection of a tv or a vcr. the host can read the status in a dedicated register in standby and active modes. 4.11 dac STW8009/stw8019 outputs generate composite video signal on one output or y/c video signals on two outputs. two embedded 10-bit dacs allow the STW8009/stw8019 to directly drive 37.5 ohms loads on each output. 4.12 power management power management includes power supplies, reset signals, clock gating and a set of dedicated pins and registers. power management is used to set the STW8009/stw8019 in different operating modes. amplitude (db) frequency (mhz)
STW8009/stw8019 functional description 15/55 4.12.1 operating modes STW8009/stw8019 can be in the following operating modes. off ? 1.2 v, 1.8 v, 2.8 /3.3 v are not present. ? all values from STW8009/stw8019 registers are lost. sleep ? 1.2 v, 1.8 v, 2.8 /3.3 v are present. ? the suspend signal is active. ? the dacs are in their minimum power consumption mode. ? all values from the STW8009/stw8019 registers are lost. standby ? all power supplies are present: 1.2 v, 1.8 v, 2.8 /3.3 v. ? the 27 mhz pixel clock must be activated. ? the suspend signal is inactive. ? STW8009/stw8019 is set in standby mode by programming the control and power management unit registers (reg 128 to 132) through the 2 wire serial mpu interface. STW8009/stw8019 saves the register values. ? the other registers (reg 00 to 109) are not accessible in this mode. ? the dacs are in their minimum power consumption mode. ? this mode is a low power state that enables a fast switching to active mode. active ? all power supplies are present: 1.2 v, 1.8 v, 2.8 /3.3 v. ? STW8009/stw8019 receives the 27 mhz pixel clock. ? the suspend signal is inactive. ? STW8009/stw8019 is placed in active mode by programming the control and power management unit registers (reg 128 to 132), through the 2 wire serial mpu interface. STW8009/stw8019 saves the register values. ? the 27 mhz pixel clock is distributed in all STW8009/stw8019. the dacs are supplied by the 2.8 /3.3 v and can be individually activated or deactivated. for example only one dac in cvbs output and both dacs in y/c output.
functional description STW8009/stw8019 16/55 4.12.2 mode transition diagram the following mode transition diagram shows the main possible transitions between the modes and the actions. figure 12. mode transition diagram transitions to off mode the possible transitions are indicated in figure 12: mode transition diagram 10 in dotted lines. no internal data needs to be saved and the STW8009/stw8019 can be turned off from any mode. the only restriction is to comply with the power supply rules described here after. transition from off mode to sleep mode then to active mode power up must be done by starting from off to sleep mode and then from sleep to active mode. sleep to standby is not possible. following the transition from off to sleep mode, STW8009/stw8019 must receive porn signal (power on reset) to initialize the control and power management unit registers (reg 128 to 132). the host sends the order for the STW8009/stw8019 to switch from sleep to active mode by releasing suspend ball and enabling pixel clock (27 mhz). the device then generates a reset sequence to the denc part. off sleep standby active registers maintained power consumption reduced denc clock gated dacs in low power normal operation all functions available dacs dynamically used on demand no power supply applied registers values lost all supplies are applied but STW8009 suspend is asserted register values lost dac in low power mode STW8009 looses all its registers and configuration when entering sleep mode a porn reset occurs after the 1.2 v & 1.8 v have been applied no need to reset or reconfigure denc in either direction suspend = ? 0 ? by sw suspend = ? 1 ? off sleep standby active registers maintained power consumption reduced denc clock gated dacs in low power normal operation all functions available dacs dynamically used on demand no power supply applied registers values lost all supplies are applied but STW8009 suspend is asserted register values lost dac in low power mode STW8009 looses all its registers and configuration when entering sleep mode STW8009 looses all its registers and configuration when entering sleep mode a porn reset occurs after the 1.2 v & 1.8 v have been applied no need to reset or reconfigure denc in either direction no need to reset or reconfigure denc in either direction suspend = ? 0 ? by sw suspend = ? 1 ?
STW8009/stw8019 functional description 17/55 transition from active mode to sleep mode in sleep mode, denc is not powered on. when suspend signal changes from ? 0 ? to ? 1 ?, the device goes from active to sleep mode and an internal reset signal is generated by the control power unit management to the denc part. this signal has a 6 pixclk duration (pixclk = 27 mhz). transition between standby and active modes transitions between these two modes are applied by software configuration through i2c interface. supply management at power up, supplies must be applied according to the following sequence: vddio1, vddio2 (1.8 v) then, vdd (1.2 v) then, vcca1, vcca2, vcca3, vcca4 (2.8 /3.3 v) and removed according to the following sequence: vcca1, vcca2, vcca3, vcca4 (2.8 /3.3 v) then, vdd (1.2 v) then, vddio1, vddio2 (1.8 v) 4.13 jtag interface to ease the integration of STW8009/stw8019 in its system application, a jtag interface is available.
control registers STW8009/stw8019 18/55 5 control registers 5.1 register addresses table 2. register addresses name type n bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 denc registers configuration0 r/w 00 std1 std0 sync2 sync1 sync0 polh polv freerun configuration1 r/w 01 blkli flt1 flt0 sync_ok coki setup_main [0] [0] configuration2 r/w 02 nintrl enrst bursten xxx selrst rstosc_buf valrst1 valrst0 configuration3 r/w 03 main_entra p trap_4.43 [0] [0] main_del_e n val_422_ck _mux xxx [0] configuration4 r/w 04 syncin_ad1 syncin_ad0 syncout_ad 1 syncout_ad 0 aline hue_en xxx xxx configuration5 r/w 05 selrst_inc bkdac1 bkdac2 [0] [0] [0] [0] dacinv configuration6 r/w 06 softreset jump dec_ninc free_jump cfc1 cfc0 [0] maxdyn configuration7 r/w 07 [0] [0] [0] xxx [0] bypass_ sync_corr [0] [0] configuration8 r/w 08 ph_rst_ mode1 ph_rst_ mode0 xxx val_422_ m ux blk_all xxx xxx xxx status r 09 hok atfr fldct2 flsct1 fldct0 jump increment_dfs r/w 10 d23 d22 d21 d20 d19 d18 d17 d16 increment_dfs r/w 11 d15 d14 d13 d12 d11 d10 d9 d8 increment_dfsr/w12d7d6d5d4d3d2d1 d0 phase_dfs r/w 13 xxx xxx xxx xxx xxx xxx o23 o22 phase_dfs r/w 14 o21 o20 o19 o18 o17 o16 o15 o14 dac1mult r/w 17 dac1_mult5 dac1_mult4 dac1_mult3 dac1_mult2 dac1_mult1 dac1_mult0 [1] [0] reserved r/w 20 xxx xxx xxx xxx xxx xxx xxx xxx line_reg r/w 21 ltarg8 ltarg7 ltarg6 ltarg5 ltarg4 ltarg3 ltarg2 ltarg1 line_reg r/w 22 ltarg0 lref8 lref7 lref6 lref5 lref4 lref3 lref2 line_reg r/w 23 lref1 lref0 - - - - - - reserved r 24 - - - - - - - - reserved xxx 45 xxx xxx xxx xxx xxx xxx xxx xxx ... ... ... ... ... ... ... ... ... ... ... reserved xxx 63 xxx xxx xxx xxx xxx xxx xxx xxx c_mult & ttx r/w 65 c_mult3 c_mult2 c_mult1 c_mult0 [0] xxx [0] bcs_en_main brightnessr/w69b7b6b5b4b3b2b1 b0 contrast r/w70c7c6c5c4c3c2c1 c0 saturationr/w71s7s6s5s4s3s2s1 s0 chroma_coef_0 r/w 72 flt_s plg_div1 plg_div0 c0(4) c0(3) c0(2) c0(1) c0(0) chroma_coef_1 r/w 73 xxx c8(8) c1(5) c1(4) c1(3) c1(2) c1(1) c1(0) chroma_coef_2 r/w 74 xxx c2(6) c2(5) c2(4) c2(3) c2(2) c2(1) c2(0)
STW8009/stw8019 control registers 19/55 chroma_coef_3 r/w 75 xxx c3(6) c3(5) c3(4) c3(3) c3(2) c3(1) c3(0) chroma_coef_4 r/w 76 c4(7) c4(6) c4(5) c4(4) c4(3) c4(2) c4(1) c4(0) chroma_coef_5 r/w 77 c5(7) c5(6) c5(5) c5(4) c5(3) c5(2) c5(1) c5(0) chroma_coef_6 r/w 78 c6(7) c6(6) c6(5) c6(4) c6(3) c6(2) c6(1) c6(0) chroma_coef_7 r/w 79 c7(7) c7(6) c7(5) c7(4) c7(3) c7(2) c7(1) c7(0) chroma_coef_8 r/w 80 c8(7) c8(6) c8(5) c8(4) c8(3) c8(2) c8(1) c8(0) configuration9 r/w 81 main_del3 main_del2 main_del1 main_del0 xxx plg_div_y1 plg_div_y0 flt_ys luma_coef_0 r/w 82 xxx xxx l8(8) l0(4) l0(3) l0(2) l0(1) l0(0) luma_coef_1 r/w 83 l9(9) l9(8) l1(5) l1(4) l1(3) l1(2) l1(1) l1(0) luma_coef_2 r/w 84 l6(8) l2(6) l2(5) l2(4) l2(3) l2(2) l2(1) l2(0) luma_coef_3 r/w 85 l7(8) l3(6) l3(5) l3(4) l3(3) l3(2) l3(1) l3(0) luma_coef_4 r/w 86 l4(7) l4(6) l4(5) l4(4) l4(3) l4(2) l4(1) l4(0) luma_coef_5 r/w 87 l5(7) l5(6) l5(5) l5(4) l5(3) l5(2) l5(1) l5(0) luma_coef_6 r/w 88 l6(7) l6(6) l6(5) l6(4) l6(3) l6(2) l6(1) l6(0) luma_coef_7 r/w 89 l7(7) l7(6) l7(5) l7(4) l7(3) l7(2) l7(1) l7(0) luma_coef_8 r/w 90 l8(7) l8(6) l8(5) l8(4) l8(3) l8(2) l8(1) l8(0) luma_coef_9 r/w 91 l9(7) l9(6) l9(5) l9(4) l9(3) l9(2) l9(1) l9(0) configuration11 r/w 93 [0] [0] [1] [0] xxx main_if_del xxx xxx configuration12 r/w 94 [0] [0] [0] [0] [0] ennotch [0] xxx configuration13 r/w 95 [0] [0] dac12_conf [0] [0] [0] [0] [1] hue_control r/w 105 hue_cont(7 ) hue_cont(6 ) hue_cont(5 ) hue_cont(4 ) hue_cont(3 ) hue_cont(2 ) hue_cont(1 ) hue_cont(0) dac2_mult r/w 106 - - dac2_mult5 dac2_mult4 dac2_mult3 dac2_mult2 dac2_mult1 dac2_mult0 chroma_delay r/w 108 [0] [0] [0] [0] main_chr_ del3 main_chr_ del2 main_chr_ del1 main_chr_del 0 chroma_delay_e n r/w 109 - - - - - [0] [0] main_chr_del _en control & power management unit registers cpmu_conf0 r/w 128 - - - - - - - standby cpmu_conf1 r/w 129 - - - - - - - cpmuswrst dac1ctrl r/w 130 - - - - - poff1 notzero-d1 pedestalond 1 dac2ctrl r/w 131 - - - - - poff2 notzerod2 pedestalond 2 plugdet r 132 - - - - - - - loadd i_test0 r/w 133 - - - - - - - - table 2. register addresses name type n bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
control registers STW8009/stw8019 20/55 5.2 description (*) = default mode when not_reset pin is active (low level) caution: all binary values quoted should be understood as msb........lsb 5.2.1 denc registers polh : synchro: active edge of hsync selection (when input) or polarity of hsync (when output) (*) 0 = hsync is a negative pulse (128 tpix_clk wide) or falling edge is active 1 = hsync is a positive pulse (128 tpix_clk wide) or rising edge is active polv : synchro: active edge of oddev/vsync selection (when input) 0 = falling edge of oddev flags start of field1 (odd field) or vsync is active low (*) 1 = rising edge of oddev flags start of field1 (odd field) or vsync is active high register 0 configuration0 address: 0x0000 type: r/w content std1 std0 sync2 sync1 sync0 polh polv freerun default 10010010 table 3. std1, std0 std1 std0 standard selected 00pal bdghi 0 1 pal n (see bit set-up) (*) 1 0 ntsc m (1) 1. standard on hardware reset is ntsc; any standard modification selects automatically the right parameters for correct subcarrier generation. 11pal m table 4. sync2, sync1, sync0 sync2 sync1 sync0 configuration 0 0 0 oddev-only based slave mode (frame locked) 0 0 1 ?f? based slave mode (frame locked) (*) 0 1 0 oddev+hsync based slave mode (line locked) 1 0 0 vsync-only based slave mode (frame locked) (1) 1. in vsync-only based slave mode (sync[2:0]=?100? ), hsync is nevertheless needed as an input. 1 0 1 vsync+hsync based slave mode (line locked) 1 1 0 master mode 1 1 1 autotest mode (colour bar pattern)
STW8009/stw8019 control registers 21/55 freerun : (*) 0 = disabled 1 = enabled note: this bit is taken into account in oddev-only or vsync-only based slave modes and is irrelevant for other synchronization modes. blkli: vertical blanking interval selection for active video lines area (*) 0 = (?partial blanking?) only the following lines inside vertical interval are blanked 1 = ?full blanking? all lines inside vbi are blanked flt[1:0] : u/v chroma filter bandwidth selection sync_ok : availability of sync signals (analog and digital) in case of input synchronization loss with no free-run active (i.e. freerun=0) (*) 0 = no synchro output signals 1 = output synchro signals available on ys, cvbs and, when applicable, hsync (if output port), oddev (if output port): i.e same behavior as free-run except that video outputs are blanked in the active portion of the line. coki : colour killer (*) 0 = color on 1 = color suppressed on cvbs output signal (cvbs=ys) but colour still present on c output. for color suppression on chroma dac ?c?, see register 5 bit bkdac2. register 1 configuration1 address: 0x0001 type: r/w content blkli flt1 flt0 sync_ok coki setup_ main default 010001[0][0] ntsc-m: lines [1; 9], [263(half); 272] (525-smpte) pal-m: lines [523; 6], [260(half); 269] (525-ccir) other pal: lines [623(half); 5], [311; 318] (625-ccir) ntsc-m: lines [1; 19], [263(half); 282] (525-smpte) pal-m: lines [523; 16], [260(half); 279] (525-ccir) other pal: ines [623(half); 22], [311; 335] (625-ccir) table 5. register 1 flt1 flt0 3db bandwidth typical application 00 f -3db =1.1mhz low def ntsc filter 01 f -3db =1.3mhz low def pal filter (*) 1 0 f -3db =1.6mhz high def. ntsc filter (atsc compliant) & pal m/n (itu-r 624.4 compliant) 11 f -3db =1.9mhz high def. pal filter: rec 624 - 4 for pal bdg/i compliant.
control registers STW8009/stw8019 22/55 setup_main : pedestal 0 = blanking level and black level are identical on all lines. (e.g.: argentinian pal-n, japan ntsc-m, pal-bdghi) (*) 1 = black level is 7.5 ire above blanking level on all lines outside vbi (e.g. paraguayan and uruguayan pal-n). in all cases, gain factor is adjusted to obtain the required levels for chrominance. note: depending on the different output configurations chosen by programming bit from dac12_conf, pedestal is automatically selected on it. nintrl : non-interlaced mode select (*) 0 = interlaced mode (625/50 or 525/60 system) 1 = non-interlaced mode(2x312/50 or 2x262/60 system) enrst : cyclic update of ddfs phase (*) 0 = no cyclic subcarrier phase reset 1 = cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below) bursten : chrominance burst control 0 = burst is turned off on cvbs, chrominance output is not affected (*) 1 = burst is enabled selrst : selects set of reset values for direct digital frequency synthesizer accumulator (*) 0 = hardware reset values for phase of subcarrier oscillator (see description of registers 13 and14 for values) 1 = loaded reset values selected (see contents of registers 13 and 14) rstosc_buf : software phase reset of ddfs (direct digital frequency synthesizer) buffer (*) 0 1 = when a 0-to-1 transition occurs either the hard-wired default phase value or the value loaded in reg. 13-14 (according to bit ?selrst?) is put to the phase buffer. this value is then loaded into accumulator (phase of sub-carrier) when the bits ?ph_rst_mode? from register 8 are programmed or when standard changes or when a soft reset occur. note: bit ?rstosc_buf? is automatically set back to ?0? after the buffer is loaded. valrst [1:0] note: valrst[1:0] is taken into account only if bit ?enrst? is set. register 2 configuration2 address: 0x0002 type: r/w content nintrl enrst bursten xxx selrst rstosc_b uf valrst1 valrst0 default 00100000
STW8009/stw8019 control registers 23/55 resetting the oscillator means forcing the value of the phase accumulator to its nominal value to avoid accumulating errors due to the finite number of bits used internally. the value at which the accumulator is reset is either the hard-wired default phase value or the value loaded in reg. 13-14 (according to bit ?selrst?) at which a 0 0 , 90 0 , 180 0 , or 270 0 correction is applied according to the field and line at which the reset is performed. main_entrap : enable trap filter (*) 0 = trap filter disabled 1 = trap filter enabled trap_4.43 : trap filter centered frequency value selection (*) 0 = trap filter centered around 3.58 mhz 1 = trap filter centered around 4.43 mhz note: ?trap_4.43? is taken into account only if bit ?main_entrap? is set. main_del_en : enable chroma to luma delay programming on cvbs output: (*) 0 = disabled (denc automatically set this delay) 1 = enabled (chroma to luma delay is programmed by del(3:0) bits from register 81. note: this delay affects only the cvbs output. the component outputs y/c remain unaffected. refer to register 109 to program chroma to luma delay on y/c output. val_422_ck_mux: should be programmed to ?0? only. table 6. valrst1 and valrst0 selection valrst1 valrst0 selection (*) 0 0 automatic reset of the oscillator every line 0 1 automatic reset of the oscillator every 2 nd field 1 0 automatic reset of the oscillator every 4 th field 1 1 automatic reset of the oscillator every 8 th field register 3 configuration3 address: 0x0003 type: r/w content main_ entrap trap_4.43 main_del_ en val_422_ ck_ mux xxx default 00[0][0]000[0]
control registers STW8009/stw8019 24/55 syncin_ad[1:0] : adjustment of incoming sync signals. used to insure correct interpretation of incoming video samples as y, cr or cb when the encoder is slaved to incoming sync signals (inc. ?f/h? flags stripped off itu-r656/d1 data). syncout_ad[1:0] : adjustment of outgoing sync signals. used to ensure correct interpretation of incoming video samples as y, cr or cb when the encoder is master and supplies sync signals. aline : video active line duration control (*) 0 = full digital video line encoding (720 pixels - 1440 clock cycles) 1 = active line duration follows itu-r/smpte ?analog? standard requirements hue_en : enables variance in phase of the subcarrier, as programmed in register_105, during active video with respect to the phase of the subcarrier during the color burst. once set, this bit is automatically reset to ?0?. (*) 0 = disabled 1 = enabled register 4 configuration4 address: 0x0004 type: r/w content syncin_ ad1 syncin_ ad0 syncout_ ad1 syncout_ ad0 aline hue_en xxx xxx default 00000000 table 7. syncin_ad[1:0] syncin_ad1 syncin_ad0 internal delay undergone by incoming sync (*) 0 0 nominal* 0 1 +1 pix_clk 1 0 +2 pix_clk 1 1 +3 pix_clk table 8. syncout_ad[1:0] syncout_ad1 syncout_ad0 delay added to sync signals before they are output (*) 0 0 nominal* 0 1 +1 pix_clk 1 0 +2 pix_clk 1 1 +3 pix_clk
STW8009/stw8019 control registers 25/55 selrst_inc : choice of digital frequency synthesizer increment after soft reset or when ph_rst_mode = ?01? . see register 8. (*) 0 = hard wired value (depending on tv standard) 1 = soft (value from registers 10 to 12) bkdacn : blanking of dacs (n = 1 or 2) (*) 0 = dac n in normal operation 1 = dac n input code forced to black level for c output or blanking level for y or cvbs output depending of dac12_conf bit of configuration13 register. dacinv : ?inverts? dac codes to compensate for an inverting output stage in the application (*) 0 = non inverted dac inputs (outputs) 1 = inverted dac inputs (outputs) softreset : software reset (*) 0 = no reset 1 = software reset note: bit ?softreset? is automatically reset after internal reset generation. software reset is active during 4 pix_clk periods. when softreset is activated, all the device is reset as with hardware reset except for the first nine user registers (registers 0 to 8: configurations).registers 10 up to 14 (increment and phase of oscillator), 25-30, 31-33 and 39-42 are never reset (hard/soft). register 5 configuration5 address: 0x0005 type: r/w content selrst_ inc bkdac1 bkdac2 dacinv default 000[0][0][0][0]0 register 6 configuration6 address: 0x0006 type: r/w content softreset jump dec_ninc free_ jump cfc1 cfc0 maxdyn default 000100[0]0 table 9. jump, dec_ninc, free_jump jump dec_nin c free_ju mp update mode 000 normal mode (no line skip/insert capability) itu-r (ccir): 313/312 or 263/262 non-interlaced: 312/312 or 262/262 (*) 0 x 1 manual mode for line insert (?dec_ninc?=0) or skip (?dec_ninc?=1) capability. both fields of all the frames following the writing of this value are modified according to ?lref? and ?ltar? bits of registers 21- 22-23 (by default, ?lref?=0 and ?ltar?=1 which leads to normal mode above).
control registers STW8009/stw8019 26/55 note: bit ?jump? is automatically reset after use. maxdyn : max dynamic magnitude allowed on ycrcb inputs for encoding. (*) 0 = 10hex to ebhex for y, 10hex to f0hex for chrominance (cr,cb) 1= 01hex to fehex for y, cr and cb note: in any case, eav and sav words are replaced by blanking values before being fed to the luminance and chrominance processing. bypass_sync_corr : tst_dac bypass mode with sync correction. this is a test mode in which data coming from port tst_dac can be output with or without sync correction and given to the dacs. (*) 0 = there is no sync correction applicable to the data coming from tst_dac. 1 = sync correction takes place before setting the dacs provided tst_ana(0) is set to ?1?. please note that in this case only 8 msbs are used to generate a 10-bit sync corrected output from the filter. 100 automatic line insert mode. the 2 nd field of the frame following the writing of this value is increased. line insertion is done after line 245 in 525/60 and after line 290 in 625/50. ?lref? and ?ltar? are ignored. (1) 110 automatic line skip mode. the 2 nd field of the frame following the writing of this value is decreased. line suppression is done after line 245 in 525/60 and after line 290 in 625/50. ?lref? and ?ltar? are ignored. (1) 1 x 1 not to be used. 1. two lines are skipped (inserted) in 525/60 and four lines in 625/50 standards table 9. jump, dec_ninc, free_jump jump dec_nin c free_ju mp update mode table 10. cfc[1:0]: colour frequency control via cfc line cfc1 cfc0 update mode (*) 0 0 disabled (update is done by loading of registers 10,11 and12) 0 1 update of increment for ddfs just after serial loading via cfc 1 0 update of increment for ddfs on next active edge of hsync 1 1 update of increment for ddfs just before next color burst register 7 configuration7 address: 0x0007 type: r/w content xxx bypass_ sync_ corr default [0] [0] [0] 0 [0] 0 [0] [0]
STW8009/stw8019 control registers 27/55 note: bits ?ph_rst_mode(1:0)? are automatically set back to ?00? following the oscillator reset in modes ?01? and ?10?. val_422_mux: should be programmed to ?1? only after each reset. blk_all : blanking of all video lines (*) 0 = disabled 1 = enabled (all inputs are ignored - 80hex instead of cr and cb and 10hex instead of y and y4) (*) = default mode when not_reset pin is active (low level) hok : hamming decoding of frame sync flag embedded within itu-r656 / d1 compliant ycrcb streams 0 = consecutive errors (*) 1 = a single or no error note: signal quality detector is issued from hamming decoding of eav, sav from ycrcb atfr : frame synchronization flag (*) 0 = encoder not synchronized 1 = in slave mode: encoder synchronized register 8 configuration8 address: 0x0008 type: r/w content ph_rst_ mode1 ph_rst_ mode0 xxx val_422_ mux blk_all xxx xxx xxx default 00100000 table 11. ph_rst_mode[1:0] :sub-carrier phase reset ph_rst_mode 1 ph_rst_mode 0 update mode (*) 0 0 disabled 01 enabled - phase is updated with value from phase buffer register (see reg2 bit rstosc_buf) at the beginning of the next video line. in the mean time, the increment is updated with hard or soft values depending on selreg_inc value (see register 5) 10 enabled - phase is updated with values from registers 10 and 11, based on the next increment update from cfc (depending on cfc loading moment and register6 cfc(1:0) bits. 11 enabled - phase is reset following the detection of rst bit on cfc line, up to 9 pix_clk after loading of cfc?s lsb. register 9 address: 0x0009 type: read only content hok atfr fieldct2 fieldct1 fieldct0 jump
control registers STW8009/stw8019 28/55 fieldct[2:0] : digital field identification number 000 = indicates field 1 ... 111 = indicates field 8 fieldct[0] also represents the odd/even information (odd=?0?, even=?1?) jump : indicates whether a frame length modification has been programmed at ?1? from programming of bit? jump? to end of frame(s) concerned. (*)default = 0 refer to register 6 and registers 21-22-23 these registers contain the 24-bit increment used by the ddfs if bit ?selrst_inc? equals ?1? to generate the subcarrier phase i.e. the address that is supplied to the sine rom. it therefore allows to customize the subcarrier synthesized frequency. 1 lsb ~ 1.609325 hz the procedure to validate the usage of these registers rather than the hard-wired values is the following: - load the registers with the required value - set bit ?selrst_inc? to 1 (reg 5) - perform a software reset (reg 6) note: 1 the values loaded in reg10-12 are taken into account after a software reset, and only if bit ?selrst_inc?=?1? (reg. 5). 2 these registers are never reset and must be explicitly written into to contain sensible information. 3 on hardware or on software reset with selrst_inc=?0?, the ddfs is initialized with a hardwired increment, independent of registers 10-12 . these hardwired values being out of any user register cannot be read. these values are: registers 10, 11, 12 increment_dfs address: 0x000a to 0x000c type: r/w register_10 d23 d22 d21 d20 d19 d18 d17 d16 register_11 d15 d14 d13 d12 d11 d10 d9 d8 register_12 d7 d6 d5 d4 d3 d2 d1 d0 value frequency synthesized d(23:0): 21f07c hexa for ntsc m f=3.5795452 mhz d(23:0): 2a098b hexa for pal b,g,h,i,n f =4.43361875mhz d(23:0): 21f694 hexa for pal n f=3.5820558 mhz d(23:0): 21e6f0 hexa for pal m f=3.57561149 mhz
STW8009/stw8019 control registers 29/55 static phase offset for digital fr equency synthesizer (10 bits only) under certain circumstances (detailed below), these registers contain the 10 msbs of the value with which the phase accumulator of the ddfs is initialized after a 0-to-1 transition of bit ?rstosc_buf? of reg 2, or after a standard change, or when cyclic phase readjustment has been programmed (see bits valrst[1:0] of reg 2). the 14 remaining lsbs loaded into the accumulator in these cases are all ?0?s (this allows to define the phase reset value with a 0.35 o accuracy). the procedure to validate the usage of these registers rather than the hard-wired values is the following: - load the registers with the required value - set bit ?selrst? to 1 (reg 2) - perform a software reset or set ?rstosc_buf? to 1 (reg 2) (to put soft phase value into a tampon register) and ph_rst_mode[1:0] note: 1 registers 13-14 are never reset and must be explicitly written into to contain sensible information. 2 if bit ?selrst?=0 (e.g. after a hardware reset) the phase offset used every time the ddfs is re initialized is a hard-wired value. the hard-wired values being out of any register, they cannot be read out . reset values: d9c000hex for pal bdghi, n, m, 1fc000hex for ntsc-m, 000000hex (blue lines) registers 13, 14 phase_dfs address: 0x000d to 0x000e type: r/w register_13 xxx xxx xxx xxx xxx xxx o23 o22 register_14 o21 o20 o19 o18 o17 o16 o15 o14
control registers STW8009/stw8019 30/55 dac1_mult[5:0]: multiplying factor on dac1_y digital signal before the d/a converters with 0.78% step. these registers may be used to jump from a reference line (end of that line) to a target line of the same field. however, not all lines can be skipped or repeated with no problems and, if needed, this functionality should be used with caution. lref[8:0] contains, in binary format, the reference line from which a jump is required. ltarg[8:0] contains the target line as a binary number. default values: lref[8:0]:= 000000000 and ltarg[8:0]:= 000000001. register 17 dac1 multiplying factors address: 0x0011 type: r/w content dac1_m ult5 dac1_m ult4 dac1_m ult3 dac1_m ult2 dac1_m ult1 dac1_m ult0 default 100000[1][0] table 12. dac1_mult[5:0]: multiplying factor on dac1_y digital signal dac1_mult[5:0] 000000 75.00% 000001 75.78% 000010 76.56% 000011 77.34% ... ... ... ... ... (*)100000 100% ... ... ... ... ... 1 1 1 1 1 1 124.22% registers 21, 22, 23 clig_i_reg = ltarg[8:0] and lref[8:0] address: 0x0015 to 0x0017 type: r/w register 21 ltarg8 ltarg7 ltarg6 ltarg5 ltarg4 ltarg3 ltarg2 ltarg1 register 22 ltarg0 lref8 lref7 lref6 lref5 lref4 lref3 lref2 register 23 lref1lref0------
STW8009/stw8019 control registers 31/55 c_mult[3:0] : multiplying factor of c digital output (before d/a convertors) and of color part of cvbs signal. bcs_en_main : brightness, contrast and saturation control by registers 69 to 71 on 4:4:4 video input 0 = disable (*) 1 = enable to adjust the luminance intensity of the display video image, the following formula is used: y out = y in + b ?128 y in is the 8-bit input luminance y out is the result of ?brightness? operation (still on 8 bits) this value is saturated at 235 (16) or 254 (1) according to register6 bit ?maxdyn?, b: brightness (unsigned value with center at 128, default 128) register 65 c_mult&ttxs address: 0x0041 type: r/w content c_mult3 c_mult2 c_mult1 c_mult0 xxx bcs_en_ main default 0000[0]0[0]1 table 13. c_mult[3:0]: multiplying factor of c digital output c_mult3 c_mult2 c_mult1 c_mult0 factor value (c_mult) (*) 0 0 0 0 1.000000 (1.000000 dec.) 0 0 0 1 1.000001 (1.015625 dec.) 0 0 1 0 1.000010 (1.031250 dec.) 0 0 1 1 1.000011 (1.046875 dec.) ... ... ... ... ... 1 1 1 1 1.001111 (1.234375 dec.) register 69 brightness address: 0x0045 type: r/w content b7 b6 b5 b4 b3 b2 b1 b0 default 10000000
control registers STW8009/stw8019 32/55 adjustment of the relative difference between high and low intensity luminance values of the displayed image is made according to the following formula: y in is the 8-bit input luminance, y out is the result of ?contrast? operation (still on 8 bits) this value is saturated at 235 (16) or 254 (1) according to register6 bit ?maxdyn?, c: contrast (2?s complement value from -128 to 127, default 0) to adjust the colour intensity of the displayed video image, the following formula is used: cr in, cb in 8-bit input chroma, cr out , cb out the result of ?saturation? operation (still on 8 bits) this value is saturated at 240 (16) or 254 (1) according to bit ?maxdyn? (reg 6), s: saturation value (unsigned value with centre at 128, default 128) register 70 contrast address: 0x0046 type: r/w content c7 c6 c5 c4 c3 c2 c1 c0 default 00000000 register 71 saturation address: 0x0047 type: r/w content s7 s6 s5 s4 s3 s2 s1 s0 default 10000000 yo u t yin 128 ? () c 128 + () 128 ------------------------------------------------- 1 2 8 + = cbout scbin 128 ? () 128 ---------------------------------- - 128 + = crout scrin 128 ? () 128 ---------------------------------- 1 2 8 + =
STW8009/stw8019 control registers 33/55 : values from these registers are used only when bit main_flt_s (reg 72) is set to 1. bit main_flt_s has the highest priority over the rest. with main_flt_s bit set to 1, all bits from main_plg_div[1:0] need to be programmed to the chroma coefficients. alternatively, the coefficients default values are loaded depending on the selected mode or the selected filter type in a particular mode with flt(1:0) bits from register 1. the values are soft loaded when main_flt_s = 1. the value to be loaded in the register should be the actual coefficient value + an offset. the hardware will internally subtract this offset to get the actual coefficient value. main_flt-s default value: 0 the main_plg_div value is chosen according to the sum of all the coefficients. offset change before loading to user register: registers 72 to 80 chroma filter coefficients address: 0x0048 to 0x0050 type: r/w table 14. chroma main_coef_[8:0] chroma_main_coef_0 reg_ 72 main_flt_s main_plg _div1 main_plg _div0 coef0(4) coef0(3) coef0(2) coef0(1) coef0(0) chroma_main_coef_1 reg_ 73 xxx coef8(8) coef1(5) coef1(4) coef1(3) coef1(2) coef1(1) coef1(0) chroma_main_coef_2 reg_ 74 xxx coef2(6) coef2(5) coef2(4) coef2(3) coef2(2) coef2(1) coef2(0) chroma_main_coef_3 reg_ 75 xxx coef3(6) coef3(5) coef3(4) coef3(3) coef3(2) coef3(1) coef3(0) chroma_main_coef_4 reg_ 76 coef4(7) coef4(6) coef4(5) coef4(4) coef4(3) coef4(2) coef4(1) coef4(0) chroma_main_coef_5 reg_ 77 coef5(7) coef5(6) coef5(5) coef5(4) coef5(3) coef5(2) coef5(1) coef5(0) chroma_main_coef_6 reg_ 78 coef6(7) coef6(6) coef6(5) coef6(4) coef6(3) coef6(2) coef6(1) coef6(0) chroma_main_coef_7 reg_ 79 coef7(7) coef7(6) coef7(5) coef7(4) coef7(3) coef7(2) coef7(1) coef7(0) chroma_main_coef_8 reg_ 80 coef8(7) coef8(6) coef8(5) coef8(4) coef8(3) coef8(2) coef8(1) coef8(0) main_plg_div = 11 when sum of coeffs = 4096 main_plg_div = 10 when sum of coeffs = 2048 main_plg_div = 01 when sum of coeffs = 1024, (default) main_plg_div = 00 when sum of coeffs = 512 chroma_main_coef0 = actual value + 16; chroma_main_coef1 = actual value + 32; chroma_main_coef2 = actual value + 64; chroma_main_coef3 = actual value + 32;
control registers STW8009/stw8019 34/55 default values: the fir symmetrical filter has the following response: the filter working frequency is comprised in the range [pix_clk, 27 mhz] and the filtering is done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros). chroma_main_coef4 = actual value + 32; chroma_main_coef5 = actual value + 32; chroma_main_coef6 = actual value chroma_main_coef7 = actual value chroma_main_coef8 = actual value chroma_main_coef0[4:0] = 10001 means c0 = 1. chroma_main_coef1[5:0] = 100111 means c1 = 7; chroma_main_coef2[6:0] = 1010100 means c2= 20; chroma_main_coef3[6:0] = 1000111 means c3 = 39; chroma_main_coef4[7:0] = 01011111 means c4 = 63; chroma_main_coef5[7:0] = 01110111 means c5 = 87; chroma_main_coef6[7:0] = 01101100 means c6 = 108; chroma_main_coef7[7:0] = 01111011 means c7 = 123; chroma_main_coef8[8:0] = 010000000 means c8 = 128. hz () c 0 c 1 z 1 ? c 2 z 2 ? c + 7 z 7 ? c 8 z 8 ? c 7 z 9 ? c + 2 z 14 ? c 1 z 15 ? c 0 z 16 ? +++ +++ + + =
STW8009/stw8019 control registers 35/55 main_del[3:0] : delay on chroma path with reference to luma path, on the encoded signal coming from the main outputs. the delay value varies with modes, delays are hardwired to have different delays in different modes. if the delays are to be made programmable, set bit main_del_en to 1 (reg 03) to enable soft delay from main_del[3:0]. if main_del_en = 0 then the delays used are: bit flt_ys enables the software loading capability of luma coefficients. values from registers 82 to 91 are used only when bit ?flt_ys? of this register is set to 1. bit ?flt_ys? has the highest priority. with this bit set to 1, all bits from plg_div_y[1:0] must be programmed as luma coefficients. alternatively, the default values of the coefficients are loaded. the luma coefficients are mode and standard independent. flt_ys default value is ?0?. register 81 configuration 9 address: 0x0051 type: r/w content main_de l3 main_de l2 main_de l1 main_de l0 xxx plg_div_ y1 plg_div_ y0 flt_ys default 00100010 table 15. main_del[3:0] main_ del3 main_ del2 main_ del1 main_ del0 delay on chroma path with reference to luma path encoding [one pixel corresponds to 2/ f pix_clk ] (*)0010- 0.5 pixel delay on chroma 0011- 1 pixel delay on chroma 0100- 1.5 pixel delay on chroma 0101- 2 pixel delay on chroma 1100+ 2.5 pixel delay on chroma 1101+ 2 pixel delay on chroma 1110+ 1.5 pixel delay on chroma 1111+ 1 pixel delay on chroma others 1 0 pixel delay on chroma ( reference delay ) others 0 + 0.5 pixel delay on chroma main_del [3:0] = 0010 when mode = pal/ntsc in 4:2:2 format on cvbs main_del [3:0] = 0001 when mode = pal/ntsc in 4:4:4. plg_div_y = 00 when sum of coefficients = 256 plg_div_y = 01 when sum of coefficients = 512 (default) plg_div_y = 10 when sum of coefficients = 1024 plg_div_y = 11 when sum of coefficients = 2048
control registers STW8009/stw8019 36/55 values from these registers are used only when bit flt_ys of register 81 is set to 1. the coefficient values of luma_coef_0 to luma_coef_7 should be entered as 2?s complement, and the rest as normal positive values. the hardware will internally generate normal positive values. default values: the fir filter is symmetrical with the following response: working frequency of this filter is the one of pix_clk (27, 24.545454 or 29.5 mhz), and the filtering is done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros). registers 82 to 91: luma filter coefficients address: 0x0052 to 0x005b type: r/w table 16. luma_coef_[0:9] luma_coef_0 reg_82 xxx xxx l8(8) l0(4) l0(3) l0(2) l0(1) l0(0) luma_coef_1 reg_83 l9(9) l9(8) l1(5) l1(4) l1(3) l1(2) l1(1) l1(0) luma_coef_2 reg_84 l6(8) l2(6) l2(5) l2(4) l2(3) l2(2) l2(1) l2(0) luma_coef_3 reg_85 l7(8) l3(6) l3(5) l3(4) l3(3) l3(2) l3(1) l3(0) luma_coef_4 reg_86 l4(7) l4(6) l4(5) l4(4) l4(3) l4(2) l4(1) l4(0) luma_coef_5 reg_87 l5(7) l5(6) l5(5) l5(4) l5(3) l5(2) l5(1) l5(0) luma_coef_6 reg_88 l6(7) l6(6) l6(5) l6(4) l6(3) l6(2) l6(1) l6(0) luma_coef_7 reg_89 l7(7) l7(6) l7(5) l7(4) l7(3) l7(2) l7(1) l7(0) luma_coef_8 reg_90 l8(7) l8(6) l8(5) l8(4) l8(3) l8(2) l8(1) l8(0) luma_coef_9 reg_91 l9(7) l9(6) l9(5) l9(4) l9(3) l9(2) l9(1) l9(0) a 0 = luma_coef_0[4:0] = 00001 means +1; a 1 = luma_coef_1[5:0] = 111111 means -1; a 2 = luma_coef_2[6:0] = 1110111 means -9; a 3 = luma_coef_3[6:0] = 0000011 means +3; a 4 = luma_coef_4[7:0] = 00011111 means +31; a 5 = luma_coef_5[7:0] = 11111011 means -5; a 6 = luma_coef_6[8:0] = 110101100 means -84; a 7 = luma_coef_7[8:0] = 000000111 means +7; a 8 = luma_coef_8[8:0] = 100111101 means +317; a 9 = luma_coef_9[9:0] = 0111111000 means +504; hz () a 0 a 1 z 1 ? a 2 z 2 ? a + 8 z 8 ? a 9 z 9 ? a 8 z 10 ? a + 2 z 16 ? a 1 z 17 ? a +++ ++ + + + =
STW8009/stw8019 control registers 37/55 main_if_del: the delay on the luma comparing to chroma in cvbs and s-vhs outputs. this delay is 5 clock cycles (27 mhz clock). (*) 0 = enabled 1 = disabled ennotch: notch filtering on the cvbs output (*) 0 = disabled 1 = enabled dac12_conf: please refer to the table below for all combinations to be observed at dacs. defines the phase shift in the subcarrier during active video with respect to the subcarrier phase during the color burst. once enabled by register_4(2) ?hue_en?, phase variation would be in a range of +/- 22.324 degrees with increments of 0.17578127. note: pulse the register_4(2) ?hue_en? to make sure that a value programmed in this register is effective immediately after programming hue_control. once enabled, to disable any phase shift in active subcarrier wrt burst, write the default value into the hue_control register followed by a pulse on register_4(2) ?hue_en?. register 93 configuration 11 address: 0x005d type: r/w content xxx main_if_ del xxx xxx default [0][0][1][0]1000 register 94 configuration 12 address: 0x005e type: r/w content xxx xxx xxx ennotch xxx default [0]0 0 0[0]0[0]0 register 95 configuration 13 address: 0x005f type: r/w content dac12_ conf default [0] [0] 0 [0] [0] [0] [0] [1] table 17. dac12_conf dac12_conf dac1 dac2 (*)0 c y 1 cvbs register 105 hue control address: 0x0069 type: r/w content hue_con t (7) hue_con t (6) hue_con t (5) hue_con t (4) hue_con t (3) hue_con t (2) hue_con t (1) hue_con t (0) default 00000000
control registers STW8009/stw8019 38/55 hue_control [6:0] : absolute value of phase adjustment, range 1 to 127. lsb (0x01) implies 0.17578127 degrees, 0x7f imply 22.324 degrees hue_control [7] : sign of phase 1 = +ve; (*) 0 = -ve (*) dac2_mult(5:0) : multiplying factor on dac2_c digital signal before the d/a converters with 0.78% step. main_chr_del[3:0] : delay on chroma path with reference to luma path on encoded component outputs. the delay value varies with modes and the delays are hardwired to have different delays in different modes. if the delays are to be made programmable make bitmain_chr_del_en = 1 (reg 109). that way, soft delay from main_chr_del[3:0] is enabled. ?00000000? : no phase shift ?10000000? : no phase shift ?11111111? : +22.324 degrees phase ?01111111? : -22.324 degrees phase register 106 dac2 multiplying factor address: 0x006a type: r/w content xxx xxx dac2_m ult5 dac2_m ult4 dac2_m ult3 dac2_m ult2 dac2_m ult1 dac2_m ult0 default 00100000 table 18. dac2_multi[5:0] dac2_mult[5:0] 000000 75.00% 000001 75.78% 000010 76.56% 000011 77.34% ... ... ... ... ... (*)100000 100% ... ... ... ... ... 111111 124.22% register 108 chroma delay address: 0x006c type: r/w content main_chr_ del3 main_chr_ del2 main_chr_ del1 main_chr_ del0 default [0] [0] [0] [0] 0 0 1 0
STW8009/stw8019 control registers 39/55 if main_chr_del_en = 0 then the delays used are: main_chr_del[3:0] = 0010 when mode = pal/ntsc in 4:2:2 format on cvbs. main_chr_del[3:0] = 0001 when mode = pal/ntsc in 4:4:4 main_chr_del_en : enable of luma to chroma delay on the 4:4:4 component outputs. (*) 0 = disabled (denc automatically sets this delay) 1 = enabled (chroma to luma delay is programmed by main_chr_del[3:0] bits (reg 108). note: this delay affects only the component y/c. the cvbs output remains unaffected. refer to register 3 to program chroma to luma delay on cvbs output signal. table 19. main_chr_del[3:0] main_ chr_ del3 main_ chr_ del2 main_ chr_ del1 main_ chr_ del0 delay on chroma path with reference to luma path encoding [one pixel corresponds to /fpix_clk] (*)0010- 0.5 pixel delay on chroma 0011- 1 pixel delay on chroma 0100- 1.5 pixel delay on chroma 0101- 2 pixel delay on chroma 1100+ 2.5 pixel delay on chroma 1101+ 2 pixel delay on chroma 1110+ 1.5 pixel delay on chroma 1111+ 1 pixel delay on chroma others 1 0 pixel delay on chroma ( reference delay ) others 0 + 0.5 pixel delay on chroma register 109 chroma delay enable address: 0x006d type: r/w content main_chr _del_en default -----[0][0]0
control registers STW8009/stw8019 40/55 5.2.2 control & power ma nagement unit registers control and power management unit standby : in this mode the analog subsystem is supplied by the 1.2 v and the 2.8 /3.3 v, but the dacs are set in power down mode, via poff[1:2] bits (reg 130 & 131). digital to analog data conversion is disabled. (*) 0 = disabled (active mode) 1 = standby control and power management unit reset cpmuswrst : control and power management unit reset (*) 0 = disabled 1 = control and power management unit software reset note: bit cpmuswrst is automatically reset to its default value after internal reset generation and the i2c data transfer is stopped. this reset is kept available for a clk cycle. poff1 : dac1 power off, then turn off dac1 is in a low power consumption mode 0 = disabled (dac1 active) (*) 1 = turned off note: as default value is ?1?, digital processor must write ?0? when going from sleep or standby to active mode. notzerod1 : null digital data inputed on dac1 0 = independently of what is coming from the digital part, ?0000000000? is forced on dac1 input. (*) 1 = disabled, values issued from denc are transmitted to dac1. pedestalond1 : black level video pedestal active on dac1 (*) 0 = disabled 1 = video pedestal active register 128 configuration0 address: 0x0080 type: r/w content standby default 00000000 register 129 configuration 1 address: 0x0081 type: r/w content cpmuswrst default 0 0 000 0 0 0 register 130 dac1 control address: 0x0082 type: r/w content poff1 notzerod1 pedestal ond1 default 0 0 000 1 1 0
STW8009/stw8019 control registers 41/55 poff2 : dac2 power off, then turn off dac2 is in a low power consumption mode. 0 = disabled (dac2 active) (*)1 = turned off note: as default value is ?1?, digital processor must write ?0? when going from sleep or standby to active mode. notzerod2 : null digital data input on dac2 0 = independently of that is coming from the digital part, ?0000000000? is forced on dac2 input. (*)1 = disabled, values issued from denc are transmitted to dac2. pedestalond2 : black level video pedestal active on dac2 (*) 0 = disabled 1 = video pedestal active loadd : reports plugdet ball status. unless otherwise specified all voltages are referenced to gnd. 0 = plugdet ball voltage less than vil 1 = plugdet ball voltage higher than vih register 131 dac2 control address: 0x0083 type: r/w content poff2 notzerod2 pedestal ond2 default 0000 0 1 1 0 register 132 plugdet address: 0x0084 type: r content loadd default --------
bus interface STW8009/stw8019 42/55 6 bus interface 6.1 2 wire serial mpu control interface (i2c compatible) STW8009/stw8019 serial mpu control interface is compliant with i2c standard and acts only as a slave device. it supports 100 khz and 400 khz speeds. in addition to the basic definition of the i2c standard (sda & scl signals), STW8009/stw8019 serial mpu interface has an additional ?add? input used to select one out of two slave addresses. the device supports 7-bit and 10-bit addresses. 7-bit address mode in write mode, several data can be sent without re-initializing a transfer and data is written in successive registers. ( figure 13: 2-wire serial mpu control interface format (i2c compatible) / 7-bit addresses ). in read mode: ( figure 13 ). double transaction read: the operation is split into to transactions: the first one is a write that transmits the desired address. the i2c interface memorizes the address of the register. the second transfer is a read that can be repeated to read successive registers. after each read byte and except for the last one, the master issues an ?acknowledge?. the master indicates that it is reading the last byte by issuing a ?no acknowledge? instead of an ?acknowledge?. single transaction read: as opposed to the double transaction, instead of stopping the first transaction and starting the second one, the transactions are combined with a repeated start condition. table 20. STW8009/stw8019 addresses 7-bit addresses 10-bit addresses read write read write add pin = 0 01000001 01000000 00001000001 00001000000 add pin = 1 01000011 01000010 00001000011 00001000010
STW8009/stw8019 bus interface 43/55 figure 13. 2-wire serial mpu control interface format (i2c compatible) / 7-bit addresses 10 bits address mode in write mode, several data can be sent without re-initializing a transfer, in this case, data is written in successive registers. ( figure 14: 2-wire serial mpu control interface format (i2c compatible) / 10-bit addresses ) in read mode: ( figure 14 ) double transaction read: the operation is split into two transactions: the first one is a write that transmits the desired address. the i2c interface memorizes the address of the register. the second transfer is a read that can be repeated to read successive registers. after each read byte and except for the last one, the master issues an ?acknowledge?. the master indicates that it is reading the last byte by issuing a ?no acknowledge? instead of an ?acknowledge?. note: only the higher part of the address is sent again before sending the read indication. single transaction read: as opposed to the double transaction, instead of stopping the first transaction and starting the second one, the transactions are combined with a repeated start condition. s STW8009 slave address r/w a STW8009 register address a write (0) * write operation (7 bits addresses) s start condition p stop condition a/na acknowledge / no acknoledge p STW8009 register data a can be repeated n times to write in successive registers from master to slave from slave to master s STW8009 slave address r/w a STW8009 register address a p write (0) * double transaction read s STW8009 slave address r/w a STW8009 register data a/na p read (1) can be repeated n times to read in successive registers sr repeated start condition s STW8009 slave address r/w a STW8009 register address a write (0) * single transaction read STW8009 register data p can be repeated n times to read in successive registers sr STW8009 slave address r/w read (1) a/na s STW8009 slave address r/w a STW8009 register address a write (0) * write operation (7 bits addresses) s start condition p stop condition a/na acknowledge / no acknoledge p STW8009 register data a can be repeated n times to write in successive registers from master to slave from slave to master s STW8009 slave address r/w a STW8009 register address a p write (0) * double transaction read s STW8009 slave address r/w a STW8009 register data a/na p read (1) can be repeated n times to read in successive registers sr repeated start condition s STW8009 slave address r/w a STW8009 register address a write (0) * single transaction read STW8009 register data p can be repeated n times to read in successive registers sr STW8009 slave address r/w read (1) a/na
bus interface STW8009/stw8019 44/55 figure 14. 2-wire serial mpu control interface format (i2c compatible) / 10-bit addresses figure 15. 2-wire serial mpu control interface timing 8 lsbs a2 STW8009 register address a * write operation (10 bits addresses) p STW8009 register data a can be repeated n times to write in successive registers STW8009 register address a p * double transaction read sr r/w a3 STW8009 register data p read (1) can be repeated n times to read in successive registers STW8009 register address a3 * single transaction read STW8009 register data p can be repeated n times to read in successive registers sr r/w read (1) s 11110 r/w a1 write (0) 2msbs 8 lsbs a2 s 11110 r/w a1 2msbs STW8009 slave address write (0) STW8009 slave address 11110 2msbs 8 lsbs a2 s 11110 r/w a1 2msbs write (0) STW8009 slave address 8 lsbs a2 s 11110 r/w a1 2msbs write (0) STW8009 slave address 11110 2msbs a a/na a/na s start condition p stop condition a/na acknowledge / no acknoledge from master to slave from slave to master sr repeated start condition 8 lsbs a2 STW8009 register address a * write operation (10 bits addresses) p STW8009 register data a can be repeated n times to write in successive registers STW8009 register address a p * double transaction read sr r/w a3 STW8009 register data p read (1) can be repeated n times to read in successive registers STW8009 register address a3 * single transaction read STW8009 register data p can be repeated n times to read in successive registers sr r/w read (1) s 11110 r/w a1 write (0) 2msbs 8 lsbs a2 s 11110 r/w a1 2msbs STW8009 slave address write (0) STW8009 slave address 11110 2msbs 8 lsbs a2 s 11110 r/w a1 2msbs write (0) STW8009 slave address 8 lsbs a2 s 11110 r/w a1 2msbs write (0) STW8009 slave address 11110 2msbs a a/na a/na s start condition p stop condition a/na acknowledge / no acknoledge from master to slave from slave to master sr repeated start condition t buf t hd_sta t low t r s=st art p=st op sclk sda t f t hd_dat t hi gh t su_dat t su_sta t hd_sta sr=start repeated t su_sto p = stop
STW8009/stw8019 bus interface 45/55 6.2 ycbcr bus figure 16. ycbcr bus format cb4 y3 cr2 y2 cb2 y1 cr0 y0 cb0 clk ycbcr[7:0]
electrical characteristics STW8009/stw8019 46/55 7 electrical characteristics 7.1 absolute maximum rating unless otherwise specified: t a =+25c, all voltages are referenced to gnd. 7.2 operating conditions unless otherwise specified: t a =+25c, all voltages are referenced to gnd. table 21. absolute maximum ratings symbol parameter value unit vdd digital core supply voltage -0.3 to +1.4 v vdd_io i/o digital supply voltage -0.3 to +2.0 v vcca analog supply voltage -0.3 to +3.8 v vdcdig dc input voltage on any digital pin -0.3 to +2.0 v vdcana dc input voltage on any analog pin -0.3 to +3.8 v pmax maximum power dissipation 700 mw t stg storage temperature range -40 to 125 c vesd electrostatic discharge voltage (iec61000-4-2, level 4) human body model -4 to +4 kv contact discharge -2 to +2 kv table 22. operating conditions symbol parameter min. typ. max. unit vdd digital core supply voltage 1.08 1.2 1.32 v vdd_io i/o digital supply voltage 1.65 1.8 1.95 v vcca analog supply voltage 2.7 3.6 v t a operating temperature -30 +85 c
STW8009/stw8019 electrical characteristics 47/55 7.3 electrical and timing characteristics unless otherwise specified: t a =+25c, all voltages are referenced to gnd. ) table 23. 2 wire serial mpu control interface timing ( figure 15 ) symbol parameter test conditions min. typ. max. unit f scl clock frequency 400 khz t buf bus free time 1300 ns t hd_sta start condition hold time 600 ns t f sda & sclk fall time 300 ns t low sclk pulse width low 1300 ns t r sda & sclk rise time 300 ns t high sclk pulse width high 600 ns t hd_dat data input hold time 0 ns t su_dat data input set up time 250 ns t su_sta start condition set up time 600 ns t su_sto stop condition set up time 600 ns table 24. digital i/o interface symbol parameter test conditions min. typ. max. unit v il input low voltage all digital inputs 0.4 v v ih input high voltage all digital inputs 1.3 v v ol output low level all digital outputs 0.2 v v oh output high level all digital outputs 1.6 v i il input low current all digital inputs / 0v < vin < v il -10 10 a i ih input high current all digital inputs / vccio < vin < v ih -10 10 a table 25. ycbcr data bus timing symbol parameter test conditions min. typ. max. unit fclk clock frequency 27 mhz tclk high clock pulse width high 15 ns tclk low clock pulse width low 15 ns dat hd data input hold time tbd ns dat su data input set up time tbd ns
electrical characteristics STW8009/stw8019 48/55 table 26. power consumption/r load = 37.5 ? symbol parameter test conditions min. typ. max. unit psl vdd sleep mode / on vdd vdd = 1.2 v no 27 mhz clock 3w pst vdd stand by mode / on vdd vdd = 1.2 v 150 w pst vcca stand by mode / on vcca vcca = 2.8 v 1 w pac vdd active mode / on vdd vdd = 1.2 v 0, 1 or 2 dac enabled 5mw pac 0 vcca active mode / on vcca vcca = 2.8 v no dac enabled 2w pac 1 vcca active mode / on vcca vcca = 2.8 v 1 dac enabled 120 mw pac 2 vcca active mode / on vcca vcca = 2.8 v 2 dac enabled 240 mw table 27. dac & video output characteristics / rload = 37.5 ohms ? f = 27 mhz ? rext = 2.4 k ? symbol parameter test conditions min. typ. max. unit r dac resolution 10 bits inl dac integral non linearity -1 +1 lsb dnl dac differential non linearity -0.5 +0.5 lsb vfr1 full range output voltage pedestal on low 1.14 1.21 1.27 v vfr2 full range output voltage pedestal on high 1.24 1.31 1.38 v sfdr spurious free dynamic range f = 1 mhz / 1 vpp tbd 49 db snr signal to noise ratio with white level 55 62 db psrr power supply rejection ratio 2.8 v supply / f = 200 hz 65 db
STW8009/stw8019 application information 49/55 8 application information figure 17. typical application schematic 75 w optional l.p. filter 75 w optional l.p. filter esd protection 75 w 75 w STW8009 digital processor c/cvbs y vdd vio vcca rext 2.4 k clk ycbcr[0:7] porn 2 wire mpu bus suspend tv set or vcr video interface only for s-vhs vdd vio vcca cvd cio cca supply 100 nf / one capacitor connected on each ball supply gnd 75 w optional l.p. filter 75 w optional l.p. filter esd protection 75 w 75 w STW8009 digital processor c/cvbs y vdd vio vcca rext 2.4 k clk ycbcr[0:7] porn 2 wire mpu bus suspend tv set or vcr video interface only for s-vhs vdd vio vcca cvd cio cca supply 100 nf / one capacitor connected on each ball supply gnd
package mechanical data STW8009/stw8019 50/55 9 package mechanical data 9.1 tfbga 49 balls table 28. tfbga 4x4x1.2 mm dimensions (mm) reference min typ max a 1.2 a1 0.15 a2 0.8 a3 0.2 a4 0.6 b 0.25 0.3 0.35 d 3.85 4.00 4.15 d1 3.00 e 3.85 4.00 4.15 e1 3.00 e0.50 f0.5 ddd 0.08 eee 0.15 fff 0.05
STW8009/stw8019 package mechanical data 51/55 figure 18. tfbga 49 balls 4 x 4 x 1.2 mm body size
package mechanical data STW8009/stw8019 52/55 9.2 vfbga 49 balls table 29. vfbga 3x3x1.0 mm - 49 balls - pitch 0.4 ball 0.25 dimensions (mm) reference min typ max a (1) 1. vfbga stands for v ery thin profile f ine pitch b all g rid a rray. very thin profile: 0.80mm STW8009/stw8019 package mechanical data 53/55 figure 19. vfbga 49 balls 3 x 3 x 1.0 mm body size note: the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. see note note:
revision history STW8009/stw8019 54/55 10 revision history table 30. document revision history date revision changes 2-feb-2006 1 initial release.
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