all trademarks mentioned in this document are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2007 dcd ? digital core design. all rights reserved. http://www.digitalcoredesign.com communication systems d d i i 2 2 c c s s b b ? ? ? ? ? ? ? i 2 c bus interface slave - base version ver 1.15 overview i 2 c is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance be- tween many devices. the DI2CSB provides an interface between a passive target device e.g. memory, lcd display, pressure sensors etc. and an i2c bus. it can works as a slave receiver or transmitter depending on working mode determined by a master device. very simple interface, composed with the read, write and data signals, allows easy connec- tion to the target devices. the core doesn?t required programming and is ready to work after power up/reset. the read, write, burst read, burst write and repeated start transmis- sions are automatically recognized by the core. the core incorporates all features re- quired by i 2 c specification. the DI2CSB sup- ports the following transmission modes: standard, fast and high speed. key features conforms to v.2.1 of the i 2 c specification slave operation slave transmitter slave receiver supports 3 transmission speed modes standard (up to 100 kb/s) fast (up to 400 kb/s) high speed (up to 3,4 mb/s) allows operation from a wide range of input clock frequencies support for reads, writes, burst reads, burst writes, and repeated start 7-bit addressing no programming required simple interface allows easy connection to target device e.g. memory, lcd dis- play, pressure sensors etc. fully synthesizable static synchronous design with positive edge clocking and synchronous reset no internal tri-states scan test ready applications embedded microprocessor boards consumer and professional audio/video home and automotive radio low-power applications cost-effective reliable automotive sys- tems deliverables source code: vhdl source code or/and verilog source code or/and encrypted, or plain text edif netlist vhdl & verilog test bench environ- ment active-hdl automatic simulation mac- ros modelsim automatic simulation macros
all trademarks mentioned in this document are trademarks of their respective owners. copyright 1999-2007 dcd ? digital core design. all rights reserved. ? ? ? ? ? ? ? ? ? ? http://www.digitalcoredesign.com http://www.dcd.pl tests with reference responses technical documentation installation notes hdl core specification datasheet synthesis scripts example application technical support ip core implementation support 3 months maintenance delivery the ip core updates, minor and major versions changes delivery the documentation updates phone & email support licensing comprehensible and clearly defined licensing methods without royalty fees make using of ip core easy and simply. single design license allows use ip core in single fpga bitstream and asic implemen- tation. unlimited designs , one year licenses allow use ip core in unlimited number of fpga bitstreams and asic implementations. in all cases number of ip core instantiations within a design, and number of manufactured chips are unlimited. there is no time restric- tion except one year license where time of use is limited to 12 months. single design license for vhdl, verilog source code called hdl source encrypted, or plain text edif called netlist one year license for encrypted netlist only unlimited designs license for hdl source netlist upgrade from hdl source to netlist single design to unlimited designs symbol datai(7:0) rd wr clk rst scli sdai sdao datao(7:0) pins description pin type description clk input global clock rst input global reset datai(7:0) input data bus from target device scli input i 2 c bus clock line (input) sdai input i 2 c bus data line (input) datao(7:0) output data bus to target device wr output write strobe for target device rd output read strobe for target device sdao output i 2 c bus data line (output) block diagram figure below shows the DI2CSB ip core block diagram. target device interface ? performs the inter- face functions between DI2CSB internal blocks and target device. allows easy con- nection of the core to a passive devices e.g. memory, lcd display, pressure sensors, i/o devices etc.. datai ( 7:0 ) datao ( 7:0 ) rd we rst clk target device interface sdai sdao scli input filter output register shift register input filter control logic synchronization logic send data receive data receive data own address detection
all trademarks mentioned in this document are trademarks of their respective owners. copyright 1999-2007 dcd ? digital core design. all rights reserved. http://www.digitalcoredesign.com http://www.dcd.pl control logic ? manages execution of all commands sent via interface. synchronizes internal data flow. shift register ? controls sda line, performs data and address shifts during the data transmission and reception. input filter ? performs spike filtering. synchronization logic ? synchronizes data and address shifts during the data transmis- sion and reception. scli spikes are filtered by this unit. performance the following table gives a survey about the core area and performance in the altera? devices after place & route (all key features have been included): device speed grade logic cells f max mercury -5 95 220 mhz stratix -5 95 230 mhz cyclone -6 95 195 mhz apex ii -7 95 220 mhz apex20kc -7 95 170 mhz apex20ke -1 95 130 mhz apex20k -1 95 94 mhz acex1k -1 95 99 mhz flex10ke -1 95 95 mhz max 7000ae -4 50 107 mhz max 3000a -4 50 107 mhz max ii -3 75 154 mhz core performance in altera? devices the main features of each digital core design i 2 c compliant cores have been summarized in table below. it gives a briefly member characterization helping user to select the most suitable ip core for its application. design i 2 c specification version master operation slave operation cpu interface passive device interface interrupt genera- tion clock synchroni- zation arbitration 7-bit addressing 10-bit addressing standard mode fast mode high-speed mode user defined tim- ing spike filtering di2cm 2.1 - - di2cs 2.1 - - - - DI2CSB 2.1 - - - - - - - i 2 c cores summary table
all trademarks mentioned in this document are trademarks of their respective owners. copyright 1999-2007 dcd ? digital core design. all rights reserved. http://www.digitalcoredesign.com http://www.dcd.pl contacts for any modification or special request please contact to digital core design or local distributors. headquarters: wroclawska 94 41-902 bytom, poland e-mail: info@dcd.pl i i n n f f o o @ @ d d c c d d . . p p l l tel. : +48 32 282 82 66 fax : +48 32 282 74 37 distributors: please check http://www.dcd.pl/apartn.php h h t t t t p p : : / / / / w w w w w w . . d d c c d d . . p p l l / / a a p p a a r r t t n n . . p p h h p p
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