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TDC1049
High-Speed A/D Converter
9-Bit, 30 Msps Features
* * * * * * * * * 30 Msps conversion rate, 15 MHz analog bandwidth 9-Bit resolution and linearity Sample-and-hold circuit not required Differential phase 0.5 degrees Differential gain 1.0% Overflow flag Single -5.2V power supply Differential ECL outputs Available in a 64-pin DIP, 68-contact LCC and 68-pin ceramic pin grid array
Description
The TDC1049 is a flash (full-parallel) analog-to-digital converter capable of converting analog signals with fullpower frequency components up to 15 MHz into 9-bit words at rates up to 30 Msps (Megasamples Per Second). A sample-and-hold circuit is not required. All digital inputs and outputs are differential ECL. The TDC1049 consists of 512 latching comparators, encoding logic and an output register. A differential convert signal controls the conversion operation. The outputs can be connected to give either true or inverted binary or offset two's complement fommats.
Applications
* Video data conversion * Radar data conversion * High-speed data acquisition
Block Diagram
CONV CONV VIN RT OFS R1 R3 R5 RTS R/2 R
2 1
R/2 R/2
0
2
512 TO 9 ENCODER
OVF, OVF D1-9 D1-9
18
LATCH
R RMID RM R/2 R/2
255
256
R R4 R2 R/2
511
RBS RB
DIFFERENTIAL COMPARATORS (512)
65-1049-01
Rev. 1.0.0
TDC1049
PRODUCT SPECIFICATION
Functional Description
General Information
The TDC1049 has three functional sections: a comparator array, encoding logic and output register. The comparator array compares the input signal with 512 reference voltages to produce an N-of-512 code or "thermometer" code. The comparators referenced to voltages less than the input signal will be on and those referenced to voltages greater than the input signal will be off. The encoding logic converts the N-of-512 code into 9-bit binary data. The output register holds the output between updates.
A midpoint tap, RM, allows the converter to be adjusted for optimum integral linearity. It can also be used to achieve a nonlinear transfer function, but adjustment of RM is not required to meet 9-bit linearity. If this node is driven by external circuitry, it should be driven from a low-impedance source; if not used, it must be left open. Parasitic resistances, R1 and R2, introduce offset errors at the top and bottom of the reference resistor chain. Sense points, RTS, RBS and OFS, may be used to reduce the effect of these offset errors. Overflow Sense (OFS) may be used to reduce the effect of the offset at the overflow (most positive) comparator whenever the Overflow (OVF, OVF) flags are used. Sense points are not required for 9-bit linearity and, if not used, they must be left open.
Power
For optimum performance, separate analog and digital power, VEEA and VEED should be supplied to the TDC1049. Separate analog and digital power supplies or a common supply with separate analog and digital paths and highfrequency decoupling can be used. The return path for the current drawn from VEEA and VEED is AGND and DGND, respectively. The returns AGND and DGND should also be kept separate and connected together at the power supply terminals. It is recommended that provisions be made on the printed circuit board for shorting jumpers between analog and digital ground as close to the A/D converter as possible. The installation of the jumpers depends upon the printed circuit board layout and overall system performance once the system is in operation. The voltage difference between VEEA and VEED must be less than +0.1V. The same voltage difference limit applies to the difference between AGND and DGND. All power and ground inputs to the converter must be connected.
Convert
The TDC1049 requires a differential ECL clock (CONV and CONV) signal. The conversion occurs (the comparators are latched) within tSTO (Sampling Time Offset) of the rising edge of CONV. The 512 to 9 encoding is performed on the falling edge of the CONV signal. The coded result is transferred to the output register on the next rising edge of CONV. Data for sample N is available at the output tD (Output Delay Time) after the rising edge of sample N+1.
Analog Input
The TDC1049 uses latching comparators which are connected to the analog inputs VIN. For optimal performance, the source impedance of the driver amplifier should be less than 25. The input signal will not damage the TDC1049 if it remains within the range of VEEA to +0.5V. If the input signal is between the VRT and VRB, the output will be a binary number between 0 and 511 inclusive. All five analog inputs must be connected.
Reference
The TDC1049 converts analog signals in the range VRB < VIN < VRT into digital form. VRB (the voltage applied to RB) at the bottom of the reference resistor chain, and VRT (the voltage applied to RT) at the top of the reference resistor chain, should both be between +0.1V and -2.1V. Within that range, VRT must be more positive than VRB. The linearity specification is based upon a 2.0V difference between VRT and VRB. The nominal voltages are VRT = 0.0V and VRB = -20V. To avoid damage to the converter, the voltage across VRT and VRB must not exceed 2.2V. A decoupling capacitor is recommended between RB and AGND. Noise introduced at this point, as well as the other reference inputs (RT, RTS, RM, RBS, OFS), may result in encoding errors.
Outputs
The outputs of the TDC1049 are differential ECL. The recommended pull-down resistance is 500 to -2V, or a 220/330 termination between DGND and VEED. The OVF signal indicates that the analog input has exceeded the threshold of the most positive comparator. Data is held valid at the output register for at least tHO (Output Hold Time) after the rising edge of CONV. New data becomes valid tD after the rising edge of CONV.
No Connects
There are several pins labeled NC (No Connect). These pins are not connected internally and may be either left open or connected to analog ground to aid heat transfer from the package and to reduce electrical noise.
2
PRODUCT SPECIFICATION
TDC1049
Pin Assignments
64 Lead Sidebrazed Ceramic DIP
Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D8 D7 D7 D6 D6 D5 D5 AGND NC NC VEED NC NC VEEA NC NC Pin Name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VEEA NC VEEA NC NC VEED NC NC AGND NC NC D4 D4 D3 D3 D2 Pin Name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D2 D1 (MSB) D1 (MSB) OVF OVF DGND DGND RBS RB NC VIN NC AGND AGND VIN RM Pin Name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VIN VIN AGND AGND VIN NC RT OFS RTS DGND CONV CONV DGND D9 (LSB) D9 (LSB) D8
65-1049-02
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64 Lead Bottombraze Ceramic DIP
Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D8 D9 (LSB) D9 (LSB) DGND CONV CONV DGND RTS OFS RT NC VIN AGND AGND VIN VIN Pin Name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RM VIN AGND AGND NC VIN NC RB RBS DGND DGND OVF OVF D1 (MSB) D1 (MSB) D2 Pin Name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D2 D3 D3 D4 D4 NC NC AGND NC NC VEED NC NC VEEA NC VEEA Pin Name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC VEEA NC NC VEED NC NC AGND D5 D5 D6 D6 D7 D7 D8
65-1049-03
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
3
TDC1049
PRODUCT SPECIFICATION
Pin Assignments (continued)
68 Lead LCC
Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 D8 D7 D7 D6 D6 D5 D5 NC AGND NC NC NC VEED VEEA NC VEEA NC Pin Name 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VEEA NC VEEA VEEA VEED NC NC NC NC AGND NC NC NC D4 D4 D3 D3 Pin Name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 D2 D2 D1 (MSB) D1 (MSB) OVF OVF DGND NC RBS RB NC VIN NC AGND AGND VIN NC Pin Name 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 RM VIN VIN AGND NC AGND VIN RT NC OFS RTS CONV CONV DGND D9 (LSB) D9 (LSB) D8
65-1049-04
61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
68 Lead Ceramic Pin Grid Array
Pin Name A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 NC VEED NC NC NC NC NC NC VEED NC AGND VEEA NC VEEA VEEA VEEA NC Pin Name B9 VEEA B10 NC B11 AGND C1 C2 NC NC Pin Name F10 D8 F11 D7 G1 D1 (MSB) G2 D1 (MSB) G10 D9 (LSB) G11 D8 H1 H2 H10 DGND H11 D9 (LSB) J1 NC J2 J10 J11 K1 K2 K3 DGND CONV DGND RBS RB VIN OVF OVF Pin Name K4 K5 K6 K7 K8 AGND VIN VIN NC AGND 11 10 9 8 BOTTOM VIEW Orientation Pin 7 6 5 4 3 2 1 L K J H GF E D CB A
C10 D5 C11 NC D1 D4 D2 D4 D10 D6 D11 D5 E1 E2 E10 E11 F1 F2 D3 D3 D7 D6 D2 D2
K9 VIN K10 RTS K11 CONV L2 NC L3 NC L4 AGND L5 L6 L7 L8 L9 RM NC VIN AGND RT
65-1049-05
L10 OFS
4
PRODUCT SPECIFICATION
TDC1049
Pin Definitions
Pin Number Pin Name VEEA VEED DGND AGND RT RTS RB RBS RM OFS CONV CONV VIN D1 MSB D2-D8 Bottombrazed DIP 46, 48, 51 43, 54 4, 7, 26, 27 Sidebrazed DIP 14,17,19 11, 22 38, 39, 58, 61 LCC PGA Value -5.2V -5.2V 0.0V 0.0V 0.0V 0.0V -2.0V -2 0V -1.0V 0.0V ECL ECL 0V to -2V ECL ECL Pin Function Description Analog Supply Voltage Digital Supply Voltage Digital Ground Analog Ground Reterence Resistor, Top Reference Resistor, Top Sense Reference Resistor, Bottom Reference Resistor, Bottom Sense Reference Resistor, Midpoint Overflow Sense Convert Convert, Complement Analog Signal Input Most Significant Bit
14, 16, 18, B9, B7, B6, 20, 21 B5 13, 22 41, 65 A3, A10 J2, J11, H10
13, 14, 19, 8, 25, 45, 46, 9, 27, 48, B2, K4, L4, 20, 40, 57 51, 52 49, 55, 57 K8, L8, 10 8 24 25 17 9 5 6 12, 15, 16, 18, 22 30 32, 34, 36, 58, 60, 62, 64 2 31 55 57 41 40 48 56 60 59 43, 47, 49, 50, 53 35 33, 31, 29, 7, 5, 3, 1 63 34 59 62 44 43 52 61 64 63 L9 K10 K2 K1 L5 L10 J10 K11
46, 50, 53, K3, K5, K6, 54, 58 L7, K9 38 G1 36, 34, 7, F1, E1, D1, 5, 3, 1 C10, D10, E10, F10 67 37 G10 G2
D9 LSB D1 MSB D2-D8
ECL ECL ECL
Least Significant Bit Most Significant Bit Complement
33, 35, 37, 32, 30, 28, 6, 35, 33, 31, F2, E2, D2, 59, 61, 63, 1 4, 2, 64 6, 4, 2, 68 D11, E11, F11, G11 3 28 29 11, 21, 23, 38, 39, 41, 42, 44, 45, 47, 49, 50, 52, 53, 55, 56 62 37 36 9, 10, 12, 13, 15,16, 18, 20, 21, 23, 24, 26, 27, 42, 44, 54 66 40 39 8, 10, 11, 12, 15, 17, 19, 23, 24, 25, 26, 28, 29, 30, 42, 45, 47, 51, 56, 60 H11 H2 H1 B1, C2, C1, J1, L2, L3, L6, K7, C11, B10, A9, B8, A8, A7, A6, A5, B4, A4, A2
D9 LSB OVF OVF NC
ECL ECL ECL Open
Least Significant Bit Complement Ovedlow Output Overflow Output Complement No Connect
5
TDC1049
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Supply Voltages VEED (measured to DGND) VEEA (measured to AGND) AGND (measured to DGND) VEEA (measured to VEED) Input Voltages
2
Min. -7.0 7.0 -1.0 -0.5 +0.5 +0.5 -2.5
Max. +0.5 +0.5 +1.0 +0.5 VEE VEE +2.5 Infinite
Unit V V V V V V V
CONV, CONV (measured to DGND) VIN, VRT, VRB (measured to AGND) VRT (measured to VRB) Output Short-circuit duration (single output in HIGH state to ground) Temperature Operating, case junction Lead, soldering (10 seconds) Storage
-60
+140 +175 300
C C C C
- 65
+150
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range.
Operating Conditions
Temperature Range Standard Parameter VEED VEEA VAGND VEEA-VEED tPWL tPWH VlCM VlDF VIN VRT VRB VRT-VRB TA TC Digital Supply Voltage (measured to DGND) Analog Supply Voltage (measured to AGND) Analog Ground Voltage (measured to DGND) Supply Voltage Differential CONV Pulse Width, LDW CONV Pulse Width, HIGH Input Voltage, Common Mode Input Voltage, Differential Input Voltage Range Most Positive Reference Inputs Most Negative Reference Voltage Reference Differential Ambient Temperature, Still Air Case Temperature
1
Extended Min. Nom. Max. Units -4.9 -4.9 -0.1 -0.1 12 15 -2.5 1.2 VRT -0.5 0.3 VRB -0.1 -1.9 1.8 -55 0.0 -2.0 2.0 -2.5 1.2 VRT +0.1 -2.1 2.2 125 -5.2 -5.2 0.0 0.0 -5.5 -5.5 +0.1 +0.1 V V V V ns ns V V V V V V C C -5.5 -5.5
Min. Nom. Max. -4.9 -4.9 -0.1 -0.1 12 15 -0.5 0.3 VRB -0.1 -1.9 1.8 0 0.0 -2.0 2.0 Input1 -5.2 -5.2 0.0 0.0
+0.1 +0.1
0.1 -2.1 2.2 70
Note: 1. VRT must be more postive than VRB, and the voltage reference differential must be within the specified range.
6
PRODUCT SPECIFICATION
TDC1049
DC Electrical Characteristics
Temperature Range Standard Parameter IEE Supply Current Test Conditions VEED, VEEA = Max TA = 0C to 70C TA = 70C IC = - 55C to 125 C TC = 125C IREF RREF RIN CIN ICB II VOL VOH Cl Reference Current Total Reference Resistance Input Equivalent Resistance Analog Input Capacitance Inpul Constant Bias Current Input Current, CONV, CONV Output Voltage, Logic Output Voltage, Logic LOW1 HIGH1 VRT, VRB = Nom, VIN = VRB VRT, VRB = Nom, VIN = VRB VEEA = Max, VIN = 0V VEED = Max, Vl = -0.7V VEED = Nom VEED = Nom TA = 25C, f = 1MHz -0.95 20 VRT, VRB = Nom 10 56 16 160 500 150 -1.6 -1.1 20 36 200 10 56 16 160 750 180 -1.5 -950 -750 -1090 -750 36 200 mA mA mA mA mA K pF A A V V pF Min. Max. Extended Min. Max. Units
Digital Input Capacitance
Note: 1. Test Load = 500 to -2v on each output.
AC Electrical Characteristics
Temperature Range Standard Parameter FS tSTO tD tHO Maximum Conversion Rate Sampling Time Offset Output Delay1 Time1 Output Hold Test Conditions VEED, VEEA = Min VEED, VEEA = Min VEED, VEEA = Min VEED, VEEA = Min 3 Min. 30 -2 6 27 3 Max. Extended Min. 30 -2 6 27 Max. Units Msps ns ns ns
Note: 1. Test Load = 500 to -2V on each output, CLOAD = 20pF.
Timing Diagrams
CONV CONV ANALOG INPUT SAMPLE N SAMPLE N+1 SAMPLE N+2 1 FS tPWH tPWH
tSTO DIGITAL OUTPUT tHO tD DATA N-1 DATA N DATA N+1
65-1049-06
Figure 1. Timing Diagram
7
TDC1049
PRODUCT SPECIFICATION
Timing Diagrams (continued)
0.0V VICM MIN VIDF
-1.3V
CONV
VICM MAX
CONV
65-1049-07
Figure 2. CONVert, CONVert Switching Levels
System Performance Characteristics
Temperature Range Standard Parameter ELI ELD Q EOTS EOT EOBS EOB TCO tTR BW SNR Linearity Error Integral, Independent Linearity Error Differential Code Size Offset Error, Top Offset Error, Top Offset Error, Bottom Offset Error, Bottom Offset Error, Temperature Coefficient Transient Response, Full-Scale Bandwidth, Full Power Input Signal-to-Noise Ratio Peak Signal/RMS Noise RMS Signal/RMS Noise EAP DP DG Aperture Error Differential Phase Error Differential Gain Error FS = 4 x NTSC FS = 4 x NTSC 0.9dB Frequency Response 15 Test Conditions VRT, VRB = Nom VRT, VRB = Nom, VRM Adjusted VRT, VRB = Nom VRT, VRB = Nom VIN = VRT, RTS Connected VIN = VRT VIN = VRB, RBS Connected VIN = VRB 15 Min. Max. 0.15 0.10 0.1 185 4 30 4 -30 20 20 15 15 Extended Min. Max. 0.20 0.10 0.1 185 4 30 4 -30 20 20 Units % % % % Nominal mV mV mV mV V/C ns MHz
30Msps Conversion Rate, 10MHz Bandwidth 1.25MHz Input 5.0MHz Input 1.25MHz Input 5.0MHz Input 57 53 48 44 50 0.5 1.5 57 53 48 44 50 0.5 1.5 dB dB dB dB ps Degree %
8
PRODUCT SPECIFICATION
TDC1049
Typical Performance Curves
Power Supply Current vs. Temperature
60 POWER SUPPLY CURRENT (mA) RMS SIGNAL NOISE SNR (dB) -450 -500 -550 -600 -650 -700 -750
65-1049-08
SNR vs. Analog Input Frequency
50 40 30 20 10 0 1.248 2.438 3.58 5
65-1049-09
-800 -850 -55 -25 0 25 50 75 100
125
6
7
8
9
10
11 12 13
14 15
CASE TEMPERATURE (C)
ANALOG INPUT FREQUENCY (MHz)
Figure 3. Power Supply Current vs. Temperature
Figure 4. SNR vs. Analog Input Frequency
Equivalent Circuits
VIN CIN ICB RIN
VIN
VRB VEEA REFERENCE RESISTOR VEEA CHAIN VEEA CIN IS A NONLINEAR JUNCTION CAPACITANCE VRB IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN RB
65-1049-10
Figure 5. Simplified Analog Input Equivalent Circuits
DGND
D DGND 5K VEED OUTPUT EQUIVALENT CIRCUIT CONV CONV TO OUTPUT PIN 5K D
20pF
500
65-1049-11
VEED
LOAD 1 TEST LOAD FOR DELAY MEASUREMENTS
-2.0V
65-1049-12
Figure 6. Digital Input Equivalent Circuit
Figure 7. Output Circuits
9
TDC1049
PRODUCT SPECIFICATION
Output Coding Table1
D1 VIN +0.0039V 0.0000V -0.0039V * * * -0.9980V -1.0020V -1.0059V * * * -1.9961V -2.0000V OVF 1 0 0 * * * 0 0 0 * * * 0 0 MSB D9 LSB
Standard Military Drawing
These devices are also available as products manufactured, tested, and screened in compliance with Standard Military Drawings (SMDs). The nearest vendor equivalent product is shown on the back page of this document; however, the applicable SMD is the sole controlling document defining the SMD product.
000000000 000000000 000000001 * * * 011111111 100000000 100000001 * * * 111111110 111111111
Note: 1. Voltages are code midpoints.
10
PRODUCT SPECIFICATION
TDC1049
Notes:
11
PRODUCT SPECIFICATION
TDC1049
Mechanical Dimensions
64 Lead Sidebrazed Ceramic DIP
Inches Min. A B1 B2 C1 D E e eA L Q S1 S2 .120 .015 .040 .008 Max. .175 .023 .065 .015 Millimeters Min. 3.05 .38 1.02 .20 Max. 4.44 .58 1.65 .38 7 2 7 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 32, 33, and 64 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 64. 5. Applies to all four corners (leads number 1, 32, 33, and 64). 6. "eA" shall be measured at the centerline of the leads. 7. All leads - Increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. Sixty-two spaces.
Symbol
3.170 3.240 .880 .910 .100 BSC .900 BSC .125 .175 .025 .065 .005 -- .005 --
80.52 82.30 14.60 15.48 2.54 BSC 22.86 BSC 3.18 4.45 .63 1.65 .13 -- .13 --
4, 8 6 3 5
32
D
1
Note 1
E
S1 Q A
33
64 S2 eA
L b2 e b1 c1
12
PRODUCT SPECIFICATION
TDC1049
Mechanical Dimensions (continued)
64 Lead Bottombrazed Ceramic DIP
Inches Min. A B1 B2 C1 D E e eA L Q S1 S2 .125 .015 .040 .008 Max. .200 .023 .065 .015 Millimeters Min. 3.18 .38 1.02 .20 Max. 5.08 .58 1.65 .38 7 2 7 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 32, 33, and 64 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 64. 5. Applies to all four corners (leads number 1, 32, 33, and 64). 6. "eA" shall be measured at the centerline of the leads. 7. All leads - Increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. Sixty-two spaces.
Symbol
3.110 3.240 .790 .810 .100 BSC .900 BSC .125 .175 .050 .100 .005 -- .005 --
80.00 82.30 20.07 20.57 2.54 BSC 22.86 BSC 3.18 4.45 1.27 2.54 .13 -- .13 --
4, 8 6 3 5
32
D
1
Note 1
E
33 S1 Q A
64 eA S2 L
b2 e
b1
c1
13
PRODUCT SPECIFICATION
TDC1049
Mechanical Dimensions (continued)
68 Lead LCC
Inches Min. A A1 B1 B3 D/E D1/E1 D2/E2 e h j L1 L2 L3 ND/NE N Max. Millimeters Min. Max. 3, 6 3, 6 2 2,5 Notes: Notes 1. The index feature for terminal 1 identification, optical orientation or handling purposes, shall be within the shaded index areas shown on planes 1 and 2. Plane 1 terminal 1 identification may be an extension of the length of the metallized terminal which shall not be wider than the B1 dimension. 2. Unless otherwise specified, a minimum clearance of .015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). 3. Dimension "A" controls the overall package thickness. The maximum "A" dimension is the package height before being solder dipped. 4 4 4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. The index corner shall be clearly unique. 5. Dimension "B3" minimum and "L3" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. Dimension "B3" maximum and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dripping. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. LID See Note 1 E
Symbol
.082 .110 .071 .093 .022 .028 .006 .022 .938 .962 .800 BSC .400 BSC .050 BSC .040 BSC .020 BSC .045 .055 .075 .095 .003 17 68 .015
2.08 2.79 1.83 2.39 .560 .710 .150 .560 23.82 24.43 20.32 BSC 10.16 BSC 1.27 BSC 1.02 BSC .510 BSC 1.14 1.40 1.91 2.41 .080 17 68 .380
5
L3
D 1 (j) x 45 4 E3 INDEX CORNER (j) x 45 DETAIL "A"
B1
B3
DETAIL "A"
(h) x 45 3 plcs PLANE 2 4
PLANE 1 A1
D2 D3
e D1
L2 E1
E2 L1
A
14
PRODUCT SPECIFICATION
TDC1049
Mechanical Dimensions (continued)
68 Lead Plastic Grid Array
Inches Min. A A1 A2 oB oB2 D D1 e L M N P Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Dimension "M" defines matrix size. 3. Dimension "N" defines the maximum possible number of pins. 4. Controlling dimension: inch.
Symbol
.080 .125 .025 .060 .105 .180 .017 .020 .050 NOM. 1.140 1.180 1.000 BSC .100 BSC .120 .140 11 68 .003 --
2.03 3.18 0.64 1.52 2.67 4.57 0.43 0.51 1.27 NOM. 28.96 29.97 25.40 BSC 2.54 BSC 3.05 3.56 11 68 .076 --
2 3
A2 A1 L e oB oB2
A
D P
D1
Bottom View Pin 1 Identifier
Top View
Beveled Corner Vendor Option
15
PRODUCT SPECIFICATION
TDC1049
Ordering Information
Product Number TDC1049J0C TDC1049J0V 5962-8853201XA TDC1049C1C TDC1049C1V 5962-8853201ZA TDC1049G8C TDC1049G8V Temperature Range STD - TA = 0C to 70C EXT - TC = -55C to 125C EXT - TC = -55C to 125C STD - TA = 0C to 70C EXT - TC = -55C to 125C EXT - TC = -55C to 125C STD - TA = 0C to 70C EXT - TC = -55C to 125C Screening Commercial MIL-STD-883 Per Standard Mil Drawing Commercial MIL-STD-883 Per Standard Mil Drawing Commercial MIL-STD-B83 Package 64 Lead Sidebrazed Ceramic DIP 64 Lead Sidebrazed Ceramic DIP 64 Lead Sidebrazed Ceramic DIP 68-Lead LCC 68-Lead LCC 68-Lead LCC 68 Lead Ceramic PGA 68 Lead Ceramic PGA Package Marking 1049J0C 1049J0V 5962-8853201XA 1049C1C 1049C1V 5962-8853201ZA 1049G8C 1049G8V
Standard Military Drawing 5962-8853201XA 5962-8853201YA 5962-8853201ZA 5962-8853201UA
Nearest Equivalent Fairchild Product No. TDC1049J0V TDC1049J3V TDC1049C1V TDC1049L1V
Package 64 Lead Sidebrazed Ceramic DIP 64 Lead Bottombrazed Ceramic DIP 68-Lead LCC 68-Lead LCC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 1/14/99 0.0m 001 Stock# DS90001049 (c) 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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