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Engineering Specification
Engineering Specification
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Type 20.8 QXGA Monochrome TFT/LCD Module Model Name:ITQX21H Document Control Number : OEM I-921H-02
Note:Specification is subject to change without notice. Consequently it is better to contact to International Display Technology before proceeding with the design of your product incorporating this module.
Sales Support International Display Technology
(C) Copyright International Display Technology 2002 All Rights reserved. March 13,2002 OEM I-921H-02 1/34
Engineering Specification
i Contents
i Contents ii Record of Revision 1.0 Handling Precautions 2.0 General Description 2.1 Characteristics 2.2 Functional Block Diagram 2.2.1 Interface Summary 3.0 Absolute Maximum Ratings 4.0 Optical Characteristics 5.0 Signal Interface www..com 5.1 Connectors 5.2 Interface Signal Description 5.3 Interface Signal Electrical Characteristics 5.4 Inverter Connector Signal Description 5.5 DC/DC Connector Signal Description 6.0 Pixel format image 7.0 Interface Timings 7.1 Timing Characteristics 8.0 Power Consumption 9.0 Power ON/OFF Sequence 10.0 I2C specification 10.1 I2C Feature Summary 10.2 Electrical Specification 10.3 Timing Specification 11.0 Mechanical Characteristics 12.0 National Test Lab Requirement 13.0 Application Note 13.1 Luminance vs Temperature 13.2 Design Recommendation 13.2.1 Recommendations for cooling 13.2.2 Mechanical recommendation for monitor enclosure design 13.2.3 Recommendation of designing monitor which uses ITQX21H for EMC Compliance
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Engineering Specification
ii Record of Revision
Date November 10,2000 February 28,2002
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Document Revision OEM921H-01 OEM I-921H-01
Page All
Summary First Edition for customer. Based on Internal Spec. EC F79103. Updated by establishment of the New Company as "International Display Technology". To avoid using "inch" indication. To update Min. value of Backlight on signal. To update Note of Minimum White Luminance. To correct Figure of LVDS Data Order. To update Max. value of Temperature for X-Driver. To update value of Shock Test Criteria. To update J1/J2 Connector (X-cards). To correct the value of the following Timing Characteristics items. (There is no design changes.) (Min. value) : Total line (Max. value) : H-front porch H-active level H-back porch To udpate Reference Drawings.
1,5,6 8 9 15 32 OEM I-921H-02 8 10 23
March 13,2002
28,29
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Engineering Specification
1.0 Handling Precautions
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* * * *
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* * *
* * * * *
Damage to the panel or the panel electronics may result from any deviation from the recommended power on/off sequencing. The panel should not be hot plugged. Refer to the Power On/Off Sequence section in this Specification. Handle the panel with care. The LCD panel and CCFL (Cold Cathode Fluorescent Lamp)s are made of glass and may crack or break if dropped or subjected to excessive force. The CCFLs contain a small amount of Mercury so should not be disposed of to landfill. Dispose of as required by local ordinances or regulations. The LCD module contains small amounts of material having no flammability grade. The exemption conditions of the flammability requirements (4.4.3.3, IEC60950 or UL1950) should be applied. The panel may be damaged by the application of twisting or bending forces to the module assembly.Care should be taken in the design of the monitor housing and the assembly procedure to prevent stress damage to the panel especially the lamp cable and the lamp connector.. Use standard earthing/grounding procedures to prevent damage to the CMOS LSI while handling the module. Use earthing/grounding procedures, an ionic shower, or similar to prevent static damage while removing the protective front sheet. The front polarizer can be easily damaged. Take care not to scratch the front surface with any hard or abrasive material. Dust, finger marks, grease etc. can be removed with a soft damp cloth (a small amount of mild detergent can be used on the damp cloth). Do not apply water or datergent directly to the front surface as this may cause staining or damage the electronic components. Never use any solvent on the front polarizer or module as this may cause permanent damage. Do not open or modify the module assembly. Continuous operation of the panel with the same screen content may result in some image sticking. Over 10 hours operation with the same content is not recommended. Wipe off water drop immediately. Long contact with water may cause discoloration or spots. When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
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The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others. The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporating this product.
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Engineering Specification
2.0 General Description
This specification applies to the Type 20.8 Monochrome TFT/LCD Module 'ITQX21H'. This module is designed for a LCD monitor style display unit.This module includes an inverter card for backlight. The screen format and electrical interface are intended to support the QXGA (2048(H) x 1536(V)) screen. Supported gray scale is 8-bit per 1(one) sub-pixel. All input signals are LVDS(Low Voltage Differential Signaling) interface compatible.
2.1 Characteristics
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items are characteristics summary on the table under 25 degree C condition: SPECIFICATIONS 528 2048(x3) x 1536 423.9(H) x 318.0(V) 0.207 x 0.207 Sub-pixel Vertical Stripe 2,300 Typ. 457.0(W) x 350.0(H) x 45.0(D) Typ.(w/inverter) Normally Black 8-bit per 1(one) sub-pixel 800 Typ. 600 : 1 Typ.(In the Dark room) 50 Typ. +12 +/- 5% 64 max LVDS (5 Pairs) x 4 (Right x 2, Left x 2)
CHARACTERISTICS ITEMS Screen Diagonal [mm] Pixels H x V Active Area [mm] Pixel Pitch [mm] Pixel Arrangement Weight [grams] Physical Size [mm] Display Mode Supported Monochrome White Luminance [cd/m 2] Contrast Ratio Optical Rise Time/Fall Time [msec] Input Voltage [V] Power Consumption [W] Electrical Interface
Temperature Range [degree C] Operating 0 to +50 Note Storage (Shipping) -20 to +60 Note : Max. Operating Temperature 50 degree C in the Spec means the temperature measured for the point of the front surface of the LCD glass cell.
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Engineering Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 20.8 Monochrome TFT/LCD Module. Type 20.8 Monochrome TFT-LCD Module Functional Block Diagram
Front View
TFT-LCD module
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+12V/4.0A
Backlight unit + Inverter Card
TFT/LCD Y-card S12B-PH-SM3-TB Array/Cell 2048x1536
FI-TWE31P or FI-TWA31P LVDS Signals (Odd/Even) I2C Signals J1 *3 IFX- car d ASIC J2 Left(Master) *1 ASIC Right(Slave) *2 IFX- car d
DC/DC Card +12V/1.5A IL-Z-8PL-SMTY-J601 *1 : 15.6V 400mA 3.3V 350mA 27.0V 10mA (for Y-card) -8.5V 100mA (for Y-card) 3.3V 5mA (for Y-card) *2 : 15.6V 400mA 3.3V 350mA *3 27.0V 10mA -8.5V 100mA 3.3V 5mA
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Engineering Specification
2.2.1 Interface Summary
O 4 sets of LVDS interface for Video input ( 65MHz Typ per set, 24 bits total) O Voltage control or I2C interface ( 3.3V ) control for Brightness and Contrast Control O Power ( +12V ) for Logic O Power ( +12V ) for Backlight ITQX21H TFT-LCD module does not have any frame buffer. Image expansion ( Scaling ) should be managed by a device driving this module and the device should supply constant timings with the frame locked to this module.
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ITQX21H has 4 sets of LVDS interface and they are bundled to two channels. The screen is divided into two half-size screens ( Left and Right ) and each channel controls one of the half-size screens. Each LVDS interface is named as : O O O O LVDS-LE ( Left screen, even dot ) LVDS-LO ( Left screen, odd dot ) : Left channel : Left channel
LVDS-RE ( Right screen, even dot ) : Right channel LVDS-RO ( Right screen, odd dot ) : Right channel
The Left channel consists of LVDS-LE and LVDS-LO and the Right channel consists of LVDS-RE and LVDS-RO. Each channel has the following signals. O 4 pairs of Video and timing signals for Even dots ( 8 bits per pixel ) O O O 4 pairs of Video signals for Odd dots ( 8 bits per pixel ) 1 pair of Dot Clock for Even dots 1 pair of Dot Clock for Odd dots
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Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows : Item Logic/LCD Drive Voltage Backlight Voltage Brightness control Backlight on signal Operating Temperature
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Symbol Vin VBL VDIM BLON TOP HOP TST HST
Min -0.3 -0.3 -0.3 -1 0 8 -20 5
Max +13.2 +13.2 +5.3 +5.3 +50 80 +60 95 1.5 50 10-200 11
Unit V V V V deg.C %RH deg.C %RH G G Hz ms
Conditions
(Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) Half sine wave
Operating Humidity Storage Temperature Storage Humidity Vibration Shock
Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation. Note 2 : Vibration Specification - Sign Vibration:10-200-10Hz, 1.5G, 30 min, X, Y, Z Axis, Each One Time. Shock Specification - Half sine wave:50G 11msec. -X+/-, -Y+/-, -Z+/- (Total 6 directions), Each One Time Shock.
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Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition: Item Viewing Angle (Degrees) K:Contrast Ratio
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Conditions Horizontal K210 Vertical K210 Rising Falling White White
2
Specification Typ. Note 20 Max 85 85 85 85 600 25 25
(Right) (Left) (Upper) (Lower)
Contrast ratio Response Time (ms) White Balance
x y (*1)
0.294 0.309 800 10
Maximum White Luminance (cd/m ) VDIM-IN = 0V Minimum White Luminance (%) Note:Measure center of the screen. VDIM-IN = 3.0V
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Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.
J1/J2 Connector (On X-cards)
J1/J2 Connector Connector Name / Designation
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Signal Connector JAE FI-TWE31P-VF(Metal Shell) or FI-TWA31P-VF(Plastic Shell) FI-W31S, FI-WE31M (*1), FI-WE31MV(*1) FI-W31MV-A (*1)
Manufacturer Type / Part Number Mating connector
Important Notice: For the J1/J2 connector and there Mating connector, following combination is mandatory requirement. J1/J2 Connector Mating Connector (FPC side) FI-W31S FI-WE31MV(*1) FI-WE31M(*1) FI-TWA31P-VF(Plastic Shell) FI-W31S FI-W31MV-A (*1) Note : For pin assignment, please refer to '5.1.2 LCD Drive Connector Description'. (*1) If you use the FPC type plug, please connect the FPC GND plane to the GND pins instead of connecting to the shell Frame Ground. Because the connectors on the PCB side are going to be changed to Plastic Mold type(FI-TWA31P-VF) those do not have the metallic shell. FI-TWE31P-VF(Metal Shell)
Inverter Connector (CN-1 on Inverter Card)
Connector Name / Designation Manufacturer Type / Part Number Mating connector Signal Connector JST S12B-PH-SM3-TB PHR-12
DC/DC Connector Type (J601 on DC/DC Card)
Connector Name / Designation Manufacturer Type / Part Number Mating connector Signal Connector JAE IL-Z-8PL-SMTY IL-Z-8S-S125C3
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Engineering Specification
5.2 Interface Signal Description
The module uses a pair of LVDS receiver macro which is equivalent to THC63LVDF84A/R84A(THine Electronics, Inc.). LVDS is a differential signal transfer technology for LCD interface and high speed data transfer device. Transmitter shall be THC63LVDF83A/M83A(THine Electronics, Inc.) or equivalent. J1 (Master) : Left side (Front View) Signal Description (J1) PIN # 1 2 www..com 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SIGNAL NAME (RESERVED) (RESERVED) (RESERVED) (RESERVED) (RESERVED) DGND SDATA SCLK DGND LGND RxOIN3+ RxOIN3RxOCLKIN+ RxOCLKINRxOIN2+ RxOIN2RxOIN1+ RxOIN1RxOIN0+ RxOIN0RxEIN3+ RxEIN3RxECLKIN+ RxECLKINRxEIN2+ RxEIN2RxEIN1+ Digital Ground I2C Data for Contrast/Brightness (3.3V typ) I2C Clock (3.3V typ) Digital Ground LVDS GND Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential clock input (Odd Clock) Negative LVDS differential clock input (Odd Clock) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Even data) Negative LVDS differential data input (Even data) Positive LVDS differential clock input (Even Clock) Negative LVDS differential clock input (Even Clock) Positive LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) Negative LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) Positive LVDS differential data input (Even data) Description This pin must be kept 'OPEN'.
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Engineering Specification
28 29 30 31
RxEIN1RxEIN0+ RxEIN0LVDSGND
Negative LVDS differential data input (Even data) Positive LVDS differential data input (Even data) Negative LVDS differential data input (Even data) Ground for LVDS clock/data signals
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Note: I2C address for Brightness and Contrast is '0101101'b. DAC for them is DALLAS DS1803 or equivalent. Its port-0 is for Contrast and the Port-1 is for Brightness. Reserved address of I2C is from '0010000'b to '0011111'b, and from '0110000'b to '0111111'b for another reserved function.
J2 (Slave) : Right side (Front View) Signal Description (J2) PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SIGNAL NAME BLON VDIM-IN VDIM-OUT VCONT-IN VCONT-OUT DGND (RESERVED) (RESERVED) DGND LGND RxOIN3+ RxOIN3RxOCLKIN+ RxOCLKINRxOIN2+ RxOIN2RxOIN1+ RxOIN1RxOIN0+ RxOIN0RxEIN3+ Digital Ground LVDS GND Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential clock input (Odd Clock) Negative LVDS differential clock input (Odd Clock) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Odd data) Negative LVDS differential data input (Odd data) Positive LVDS differential data input (Even data) Description Backlight on/off signal(Hi:backlight ON, Low:backlight OFF) Brightness Dimming Control Voltage (0-3V, 0V:MaxBrightness) Brightness Dimming Control Voltage Output Generated by I2C command Contrast Control Voltage (0-1.6V, 1.0Vtyp for Gamma2.2, 0V:Brighter side) Contrast Control Voltage Output Generated by I2C command Digital Ground
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Engineering Specification
22 23 24 25 26 27 28 29 www..com 30 31
RxEIN3RxECLKIN+ RxECLKINRxEIN2+ RxEIN2RxEIN1+ RxEIN1RxEIN0+ RxEIN0LVDSGND
Negative LVDS differential data input (Even data) Positive LVDS differential clock input (Even Clock) Negative LVDS differential clock input (Even Clock) Positive LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) Negative LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) Positive LVDS differential data input (Even data) Negative LVDS differential data input (Even data) Positive LVDS differential data input (Even data) Negative LVDS differential data input (Even data) Ground for LVDS clock/data signals
Note: To use I2C digital control for Contrast/Brightness, connect VCONT-OUT to VCONT-IN, VDIM-OUT to VDIM-IN. To use analogue voltage control, set VCONT-OUT and VDIM-OUT open, then supply appropriate analogue voltage to VCONT-IN and VDIM-IN.
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Engineering Specification
The following is LVDS Signal description; SIGNAL NAME DTCLK Description Data Clock The typical frequency is 65 MHz. The signal is used to strobe the pixel data and DSPTMG signals. All pixel data shall be valid at the falling edge when the DSPTMG signal is high. When the signal is high, the pixel data shall be valid to be displayed. The signal is synchronized to DTCLK. The signal is synchronized to DTCLK. The signal is synchronized to DTCLK.
DSPTMG
Display Timing
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V-Sync H-Sync
Vertical Sync Horizontal Sync
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
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Engineering Specification
The following is LVDS Data Order;
RxECLKIN+ RxECLKIN1 cycle
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RxEIN0+ RxEIN0RxEIN1+ RxEIN1RxEIN2+ RxEIN2RxEIN3+ RxEIN3-
EA3
EA2
EB2
EA7
EA6
EA5
EA4
EA3
EA2
EB2
EB4
EB3
EC3
EC2
EB7
EB6
EB5
EB4
EB3
EC3
EC5
EC4
DSP
V-S
H-S
EC7
EC6
EC5
EC4
DSP
EA1
EA0
NA
EC1
EC0
EB1
EB0
EA1
EA0
NA
RxOCLKIN+ RxOCLKIN1 cycle
RxOIN0+ RxOIN0RxOIN1+ RxOIN1RxOIN2+ RxOIN2RxOIN3+ RxOIN3-
OA3
OA2
OB2
OA7
OA6
OA5
OA4
OA3
OA2
OB2
OB4
OB3
OC3
OC2
OB7
OB6
OB5
OB4
OB3
OC3
OC5
OC4
NA
NA
NA
OC7
OC6
OC5
OC4
NA
OA1
OA0
NA
OC1
OC0
OB1
OB0
OA1
OA0
NA
Note: A/B/C 7: MSB , A/B/C 0: LSB, DSP = DSPTMG, V-S = V-Sync, H-S = H-Sync 'NA' : Both high and low data are ignored.
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Engineering Specification
5.3 Interface Signal Electrical Characteristics
Each signal characteristics are as follows; Electrical Characteristics Parameter Vth Condition Differential Input High Voltage (Vcm=+1.2V) Differential Input High Voltage (Vcm=+1.2V) -100 Min Max 100 unit mV
Vtl
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mV
Note : It is recommended to refer to the specifications of THC63LVDF84A/R84A(THine Electronics, Inc.) for the detail.
LVDS Timing
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Engineering Specification
LVDS Macro AC characteristics Parameter Symbol LVDS Clock Cycle Trxc LVDS Data Cycle Trxd Sample Data Setup Time Trxss (Trxc=Typ.) Sample Data Hold Time Trxsh (Trxc=Typ.) Data Sample Time Trxs Data Sample Cycle Trxsc
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Min 15.15 600 600
Typ 15.38 Trxc/7
Max 16.66
Unit [ns] [ns] [ps] [ps]
Trxc/14 Trxc/7
[ns] [ns]
Inverter Input Signal Electrical Characteristics NAME BLON Description High voltage Low voltage Current Vcont-IN Input Voltage range Current VDIM-IN Input Voltage range Current Min 2.0 -0.1 -1.0 0.2 -1.0 0.0 -1.0 Typ 3.3 0.0 1.0 Max 5.25 0.8 1.0 1.6 1.0 3.0 1.0 Unit V V mA V mA V mA 0V:Brightness Max 3V:Brightness Min *1 Note
Note: *1) 0.2V : To pull the GAMMA curve toward darker side (ex. GAMMA 3.0) When x'00' is written by I2C, Vcont-OUT voltage is about 0.2V 1.0V : GAMMA 2.2 When x'50' is written by I2C, Vcont-OUT voltage is about 1.0V 1.6V : To pull the GAMMA curve toward brighter side (ex. GAMMA 1.5) When x'D0' is written by I2C, Vcont-OUT voltage is about 1.6V Those numbers are approximate values. *2) I2C address for Brightness and Contrast is '0101101'b and the port-0 is for Contrast and port-1 is for Brightness.
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Engineering Specification
5.4 Inverter Connector Signal Description
Inverter Connector Signal Description PIN # 1-5 6-10 11 12
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SIGNAL NAME VBL RTN (RESERVED) (RESERVED)
Description +12.0V Power Source for backlight Ground for VBL line
Inverter Input Signal Electrical Characteristics NAME VBL Description B/L Unit Drive Voltage Min 11.4 Typ 12 Max 12.6 Unit V Note
5.5 DC/DC Connector Singal Description
DC/DC Connector Signal Description PIN # 1-4 5-8 SIGNAL NAME RTN Vin Description Ground for Vin line +12.0V Power Supply for LCD Driver Cards (Except Inverter and Backlight)
DC/DC Input Signal Electrical Characteristics NAME Vin Description Logic/LCD Drive Voltage Min 11.4 Typ 12 Max 12.6 Unit V Note
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Engineering Specification
The following chart is the VDIM vs Dimming Range for your reference.
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Engineering Specification
6.0 Pixel format image
Screen Format
LVDS-LE LVDS-LO
LVDS-RE LVDS-RO
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0 1
0
1
2
1022102310241025
20462047
Left Screen
Right Screen
1534 1535
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Engineering Specification
Following figure shows the relationship between the input signals and the LCD pixel format image. Each sub-pixel data(A,B,C) of an Even and the right adjacent Odd pixel unit are sampled at the same time. Pixel Arrangement Even 0 0th Line
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Odd 1
C A B C
Even 2046
A B C A
Odd 2047
B C
A
B
1535th Line
A
B
C
A
B
C
A
B
C
A
B
C
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Engineering Specification
7.0 Interface Timings
Following is the Video timing diagrams per channel ( a half screen refresh ) to be converted to/from the LVDS interface signals.
7.1 Timing Characteristics
EVEN for LVDS-LE or LVDS-RE ODD for LVDS-LO or LVDS-RO. Interface www..com Timing Definition
Tv Tva V-Sync H-Sync DSPTMG Tvb 0 1 m-1 Vsync, Hsync and Display Timing Th Tha H-Sync Dot clock DSPTMG Video(Even) Video(Odd) Tck Thd Thb 0 1 2 3 n-2 n-1 Thf Tvf
Video signal, Hsync and Dot clock
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Engineering Specification
Timing Characteristics Signal DTCLK DTCLK V-Sync V-Sync V-Sync
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Item Dot Clock Freq. Dot Clock period Refresh Rate Frame period Total line V-front porch V-active level V-back porch V-Blank Display Lines H-Scan Rate H-Scan Rate Cycle H-front porch H-active level H-back porch H-Blank Display clocks Display Pixels
Symbol Fdck Tck 1/Tv Tv Tv Tvf Tva Tvb Tvf+Tva+Tvb m 1/Th Th Th Thf Tha Thb Thf+Tha+Thb Thd n
MIN. 60 15.15
TYP. 65 15.38 60 16.67
MAX. 66 16.66
Unit MHz ns Hz ms
1547 2 2 7 11 92.86 10.34 640 8 8 8 128 -
1612 6 12 58 76 1536 96.72 *1 672 12 68 80 160 512 1024
1628 14 14 64 92 96.72 10.77 700 172 172 172 188 -
lines lines lines lines lines lines KHz us Tck Tck Tck Tck Tck Tck pixels
V-Sync
V-Sync V-Sync V-Sync DSPTMG H-Sync H-Sync H-Sync H-Sync H-Sync H-Sync H-Sync DSPTMG DSPTMG
Note: Typical value is based on VESA STANDARD ( XGA 60Hz ). H/V-Sync Polarity can be both Positive and Negative. DSPTMG should be Active High. V-Sync should not be changed at H-Sync leading edge ( +/- 6 Tck ). Even Dot clock and Odd Dot clock in each channel should have completely the same clock source. The skew should be within +/- 2ns. Dot Clocks of the Left and Right channels should have completely the same clock source. But the skew between those clocks does not need to be cared. The skews of all the other signals ( H-Sync, V-Sync, DSPTMG and Video data ) should be synchronized between Left and Right channels and should be within +/- 4 dot clocks, respectively. *1 For this value, the smaller, the better.
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Engineering Specification
8.0 Power Consumption
Input power specifications are as follows; SYMBOL Vin Iin Pin
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PARAMETER Logic/LCD Drive Voltage Vin Current Vin Power Allowable Logic/LCD Drive Ripple Voltage Allowable Logic/LCD Drive Ripple Noise Backlight power Voltage Backlight Power consumption
Min 11.4
Typ 12 1.2 14.4
Max 12.6 1.4 16 100 100
UNITS V A W mVp-p mVp-p V W
CONDITION
Vin=12V Vin=12V All White Pattern
Vin rp Vin ns VBL PBL
11.4
12 44
12.6 48
Brightness=max
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Engineering Specification
9.0 Power ON/OFF Sequence
Vin power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when Vin is off. Vin/VBL/Signals Power On/Off Sequence Requirements
Vin
10%
90%
90%
10%
10%
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0V
30ms max. and 1ms min. 10ms min. 30ms min. 0 min.
Signals
0V
10%
10%
100ms min.
VBL
10%
90%
90%
10%
10%
0V
30ms max. and 1ms min. 5ms min. 0 min.
BLON
0V
10%
10%
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Engineering Specification
10.0 I2C Specification
Following describes the I2C specifications equipped in the LCD module. Since the DAC ( DALLAS DS1803 ) is used for Brightness and Contrast, please refer to its own specifications in detail. 2 signals ( SCLK and SDATA ) in the LCD module interface are used for the DAC. The address for DAC is '0101101'b. Its port-0 is for Contrast and its port-1 is for Brightness. Reserved addresses are from '0010000'b to '0011111'b and from '0110000'b to '0111111'b.
10.1 I2C Feature Summary
- Standard www..com mode ( 100KHz max ) support - 3.3V interface - Slave mode operation only
10.2 Electrical Specification
2 signals ( SCLK and SDATA ) are equipped at the LCD module interface. SCLK is the clock input as SCL and SDATA is the data input/output as SDA. These signals should be driven by Open-Drain or Open-Collector without any pull-up resister. Both signals are pulled up by 5.1K ohm resisters to 3.3V typ respectively in the LCD module. Electrical Specification of C/A Input Low voltage (*1) Input High voltage (*2) Input Hysteresis voltage Input leakage current @ Vil-Min or Vih-Max (*3) Output Low voltage Output High impedance current(*3) Input capacitance Symbol Vil Vih Vhys Ii Vol Ioh Ci Min -0.5 2.3 0.4 -30 -30 Max 0.5 3.6 30 0.5 30 35 Unit V V V uA V uA pF
leakage
NOTE : *1 : Vil (typ) = 0.9V *2 : Vih (typ) = 1.8V *3 : without pull up resisters ( 5.1K ohm )
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Engineering Specification
10.3 Timing Specification
In the following figure and table, Slave is the control ASICs in the LCD module and Master is the controller to drive the LCD module. "S" is the START condition and "P" is the STOP condition. I2C Bus timing
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Timing Specification of C/A Frequency of SCL Bus Free Time from STOP to START Setup time of START Hold time of START Low time of SCL High time of SCL Data hold time for Slave Data setup time for Slave Data change from SCL falling edge ( to Master ) Rise time Vil-Max --> Vih-Min Fall time Vil-Max <-- Vih-Min Setup time of STOP Spike suppression Symbol fSCL tBUF tSU:STA tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tCH:DAT tR tF tSU:STO tSP Min 0 4.7 4.7 4.0 4.7 4.0 0 250 300 4.0 Max 100 900 1000 300 50 Unit KHz us us us us us us ns ns ns ns us ns
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Engineering Specification
11.0 Mechanical Characteristics
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Engineering Specification
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Engineering Specification
12.0 National Test Lab Requirement
The display module is authorized to Apply the UL Recognized Mark.
Conditions of Acceptability
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This component has been judged on the basis of the required spacings in the Standard for Safety of Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95 *UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for Listing. The inverter output circuit supplied with this model is a limited Current Circuit. The units are intended to be supplied by SELV. The terminals and connectors are suitable for factory wiring only. The terminals and connectors have not been evaluated for field wiring. A suitable Electrical and Fire enclosure shall be provided.
(C) Copyright International Display Technology 2002 All Rights reserved. March 13,2002 OEM I-921H-02 30/34
Engineering Specification
13.0 Application Note
This section describes some outstanding characteristics of ITQX21H module and also describes some design recommendations.
13.1 Luminance vs Temperature
The following chart shows the initial luminace transition coming along with the module temperature.
ITQX21H Temperature Characteristics (Luminance)
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13.2 Design Recommendation
This chapter describes the recommendation when monitor frame is designed.
13.2.1 Recommendations for cooling
The ITQX21H is a high luminance and high resolution panel and produces some heat. Inadequate cooling can result in damage to the module or the monitor unit. COOLING FANS ARE STRONGLY RECOMMENDED TO ENSURE CORRECT TEMPERATURE OPERATION. Because of the large panel size the use of 2 fans is recommended. The recommended position of the fans is to supplement the normal convective flow. The optimum configuration would be to input cool air at the base of the panel and exhaust hot air at the top. The exact size, position, and flow rates are a function of the monitor enclosure design. Please refere to the maximum operating temperatures of the various components to verify the design.
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Engineering Specification
*** Reference *** See the rear side of module below;
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- ABSOLUTELY NECESSARY POINTS are next two components. (6) X-DRIVER (Will get very hot.) and (1) Choke Coil - Backlight Inverter (2) Transformer - DC/DC Card (3) Choke Coil - PCB-X (4), (5) Gate Array The table below shows the maximum component temperature Spec. Component Gate Array X-Driver Choke Coil(Inverter) Transformer(Inverter) Choke Coil(DC/DC) Polarizer(Cell) Max. Temperature Spec. (degree C) 100 85 105 100 105 60
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Engineering Specification
13.2.2 Mechanical recommendation for monitor enclosure design.
This TFT module uses IPS technology to enhance viewing angle, this technology is weak against twisting and bending forces. These forces cause bad FOS quality, such a un uniformity. In order to keep original FOS quality, please following instruction at manufacturing and designing. 1. After installation of the TFT Module into an enclosure, do not twist nor bent the TFT Module even momentary. 2. At designing the enclosure, it should be taken into below consideration. otherwise the TFT Module occur uniformity problem. 2-1. Material of chassis or bracket to mounting TFT module should be hard material, stainless or SECC or SPCC. Material thickness should be exceeded 1mm. 2-2. No bending/ twisting forces are applied to the TFT Module from out side. 2-3. No pushing force for EMI grounding using metal fingers or gasket TFT metal bezel, to push glass surface by TFT metal bezel opening edge, is applied to TFT module metal bezel wall. 2-4. At designing system front plastic bezel, do not touch and push glass surface to avoid un uniformity.
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13.2.3 Recommendation of designing monitor which uses ITQX21H for EMC Compliance
A. Chassis and Frame Ground of Monitor 1. LCD Module should be covered by metal chasis over all except front side. the chasis of the monitor's interface card should be designed as separate parts with the chasis of the LCD module. Holes on the partition wall between the two chasis shold be as small as possible to pass through the cables. The two chassis should be contacted each other with low impedance. 2. Monitor's chasis(equal chasis of LCD module)should have the contact with the frame ground of voltage source(Power FG) with low impedance. 3. The chasis of LCD module should have the contact with the surrounding of front bezel by finger or something at intervals of less than 1 inch. 4. The ground of the monitor's interface card should be contacted with its chasis with low impedance. 5. The holes for thermal radiation, on chasis of LCD module or monitor's interface card, should be less than 1 inch in diameter, at intervals of less than 1 inch. We recommend the holes are about 5mm in diameter, at intervals of about 10mm to 15mm.
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Engineering Specification
B. LVDS cabel(assumption as wire type, not FPC or FFC) 1. Signal pairs of the differential signals should be twisted each other with more than a turn per a centimeter. 2. The ground line would wind around the set of LVDS cables(1 channel). 3. The set of LVDS cables would be covered by shield mesh. To make the shield mesh contacted with the signal ground, it is possible to strip the cover of ground line wound around LVDS signals. 4. Ferrite Core would be added to LVDS cables at the point near signal source. We recommend the above works at that priority(1. is the highest).
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C. A ferrite core would be added to the power cable which supply +12volt to LCD module.
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