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GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
Gigabit Ethernet PHY Solutions
Users Manual
GIGAPHY-SD Gphysd_1b Gigabit Evaluation Board
GigaPHY(TM) -SD Device
Physical Layer 10-Bit Transceiver for Gigabit Ethernet
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 1 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
Features * * * * * * * Evaluation System for use in studying the GigaPHYTM Am79761. Switches for Driving Control Lines. LED' for Monitoring Control Lines. s On Board Generation of 3.3V from External 5V through 12V supply. Internal or External Clock Source. 10-bit Transmit Data Provided From Switches or onboard PAL or from a Pattern Generator. 10-bit Receive Data Monitored on LED' or Through a Logic Analyzer Pod. s
Block Diagram
SW Shutdown 3.3 Voltage Regulator
OSC INT. EXT. SW SEL[0] SW SEL[1] PAL Or Switch TXD[9:0]
SMA
SMA
AM79761 GigaPHYTM Ethernet PHY
RXD[9:0]
B U F F E R S
RXD[9:0]
L E D S
Logic Analyzer/Pattern Pod
SW EWRAP
SW EN_CDET
Logic Analyzer Pod
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 2 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
General Description The GigaPHYTM GPHYSD_1B Board, provides a low cost, easy-to-use tool to evaluate the Gigabit Transceiver, AM79761, with regard to signal quality and performance. It is intended that the GigaPHYTM board be a self-contained Evaluation Unit. In its simplest form, the switches on the GPHYSD_1B can be used to set the transmit data and control lines while monitoring received data and status lines with LED' s. A pre-programmed PAL in addition to the switch settings can generate simple word patterns. More in-depth evaluations can be implemented by connecting a Pattern Generator (10-bits at 125MHz) to pods on the board in order to generate transmit data and control signals. A logic analyzer can also be connected to pods on the board in order to monitor receive data and status signals. With this setup 8B/10B data can be sent to the transmitter on the Evaluation Unit to generate Gigabit data and monitored on the Logic Analyzer. Other useful features of the board include the presence of an on-board, removable oscillator with Tristate (normally at 125MHz) in a DIP, half DIP or Surface Mount form. An on-board voltage regulator is used to provide 3.3V to the board with a shutdown switch used to turn off power to all components. Scope of this Document It is intended that the AM79761 datasheet be used for reference in understanding the device function. Additionally, the following items are enclosed in this document: 1. 2. 3. 4. Schematics for the board Artwork for the board (copies of each layer) Fabrication drawing for the board Bill of materials for the board.
Operation and Switch Settings
HP1 HP2 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 P1 TXD Logic Analyzer/Pattern input RXD Logic Analyzer RXD[0] Status RXD[1] Status RXD[2] Status RXD[3] Status RXD[4] Status RXD[5] Status RXD[6] Status RXD[7] Status RXD[8] Status RXD[9] Status COMDET Comma Character Status +5POS External Power Supply Input indicator +3.3 Power Supply Input indicator /SHDN Status for Voltage Regulator if [ON] Shutdown [OFF] Enabled SEL[0] SEL[1] EWRAP EN_CDET /SHDN [H] Voltage Regulator is [ON] Power to DUT [L] Shuts down the Voltage Regulator[OFF] No power to DUT. SEL[0] SEL[1] P4 P5 PWR1 PWR2 SMA1 EWRAP EN_CDET Ext. Lab bench +5V DC supply Ext. Wallmount +5V DC supply External 125Mhz Clock Install [0]ohm resistor R2 and W1[to Tristate Clock Crystal]. SMA2 TX[+] Output SMA3 TX[-] Output SMA4 RX[+] Output SMA5 RX[-] Output SMA6 RCLKN Output SMA7 RCLK Output SW1 Manual Setting to TXD[0:9] U1 AM79761 U2 PAL for TXD[0:9] inputs U3 Buffer to LED' s U4 Buffer to LED' s VR1 +5POS to +3.3POS Voltage Regulator with Shutdown. W1 TRI-STATE Jumper to Tri-State Clock Crystal output. X1 125 MHz Clock Crystal. ZTP1 VDDIN [+5 volt power supply]. ZTP2 +5POS going to Voltage regulator. ZTP3,5,6,7 DVSS ZTP4 DVSS
P2 P3
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 3 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
Operation The GigaPHYTM eval board provides potential customers with a simple, easy-to-use evaluation tool for understanding the function and performance of the AM79761 10-bit Gigabit Transceiver. A 125MHz 3.3V crystal oscillator provides a reference clock (REFCLK) to the AM79761. The clock trace has been minimized to provide the best signal quality possible. Since REFCLK is used to latch data into the AM79761, the trace length between the REFCLK clock and the TXD[0-9] data should be kept somewhat similar (i.e. within 1" so as to maximize the timing margin for the chip generating the transmit ) data. The recovered clocks, RCLK and RCLKN, can be monitored through the SMA connectors. The TEST pins of the AM79761 are tied HIGH for manual switch operation. The EN_CDET pin, which is set by a switch, allows SYNC detection and framing. When EN_CDET is enabled, the detection of COMMA will generate a COM_DET, which is monitored by an LED. In order to select loopback mode, the EWRAP must be HIGH which will cause the parallel input data TXD[0-9] be wrapped around inside the AM79761 and outputed as RXD[0-9] and the TX[+/-] outputs will be held high. The on board 125 MHz oscillator generates the transmit clock for the AM79761 (REFCLK). TXD[0-9] is latched into the AM79761 on every rising edge of this clock. The AM79761 recovers the data with the word-oriented clock (RBC-) at 62.5MHz. An on-board diagnostic path is provided to allow testing of the board. The input parallel data can be generated by a 10-bit switch or by a pre-programmed PAL. The 10-bit switch only allows a static 10 bit word pattern but the PAL can be used to generate a longer repetitious word patterns. A more sophisticated word pattern can be generated from a Pattern Generator through the pod connector. If nonloopback mode is selected, the parallel, TXD[0-9], will be serialized by the AM79761 and pumped out through the TX[+/-]. Then, the high-speed serial data is received through the RX[+/-] into the AM79761 and is deserialized to a 10-bit parallel data bus, RXD[0-9]. LED' or a logic analyzer through the on-board s pod can monitor the RXD[0-9]. For a 50 ohm environment, the AM79761 transmitters PECL outputs drive 50 ohm traces with a 182 ohm current sinking resistor and an AC-coupled 0.01uF capacitor to the 50-ohm SMA connectors labeled TX[+] (SMA1) and TX[-] (SMA2). The resistor-capacitor termination circuit are needed to supply current and decouple the 3.3V-referenced PECL outputs of the AM79761 from the PECL-levels required on the coaxial cable. The AM79761 receives differential PECL serial data from the coax cable on the 50-ohm SMA connectors labeled RX+/-. This input is immediately AC-coupled through a 0.01uF capacitor and terminated with 182-ohm pull-down resistors. The AM79761 provides internal resistors to set the DC Bias to Vdd/2. The termination resistors and AC coupling caps are located as near as possible to the input pins on the AM79761 to maximize signal quality. The Evaluation board has voltage regulator that supplies the board with 3.3Volts. The input to the voltage regulator can be from 5 volts DC to 12 volts DC from either a lab bench supply through PWR1 or from a wall mounted supply through PWR2. The voltage regulator output can be shutdown with the shutdown a switch [P1]. When LED13 is ON the regulator output is OFF. PAL and Manual Switch Pattern Generator Settings SEL[0] L SEL[1] L Undetermined Undetermined SEL[0] L SEL[1] H Pseudorandom SEL[0] H SEL[1] L 00111100xx Repeating 00111100xx SEL[0] H SEL[1] H Alternating Alternating +/- K28.5 Note; for the PAL to output the right data the Manual switch setting SW1 all have to be off. Note; for the Manual Switch to work , the PAL has to be removed. Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 4 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
Layout Considerations The board has been designed in a simple, straightforward manner in which highest priority was given to properly routing of high-speed signals. This four layer, controlled impedance PCB contains signal layers on the top and bottom of the board with internal Power (Vdd=3.3V) and GND planes. Components are mounted on both sides of the board so that passives may be placed as close as possible to their ideal location regardless of which side of the board the part is placed. The PCB accommodates a special socket for the AM79761 so placement of passives on the topside near the pins was not possible. The 1Gb/s transmit and receive signals between the chipset and the connector were the first priority. Since they form a differential PECL pair these traces were of minimal and equal length and, in this example, have characteristic impedance of 50 ohm. The passive components should be packed as closely as possible to minimize stub lengths and maximize signal quality. On the receiver inputs, minimization of trace length between the AC Coupling Caps (C28/C29), the input pins (RX[+],RX[-]) and the 182 ohm termination resistors are very important since the terminator resistors act as the virtual end of the line. Stubs on these lines will cause degradation of signal quality into the receivers due to reflections. Diagonal corners were used so as to avoid the impedance mismatches found in right angle traces. The same considerations as other high-speed signals apply here. Transmit data jitter is generated through two main factors: Power Supply Noise and TBC jitter. Proper layout of the REFCLK traces is essential to minimize REFCLK jitter into the part. Curved traces are used to minimize reflections. Generous bypassing of the power supplies and separate isolation and decoupling for each sensitive supply type is one easy method to eliminate much of this noise. In general, common layout/placement techniques developed for lower speed PCBs apply here and should lead to first-pass success.
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 5 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board
Table 1: Bill of Materials
Item 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) 20) 21) 22) 23) 24) 25) 26) 27) 28) 29) 30) 31) 32) 33) 34) 35) 36) 37) 38) 39) 40) 41) 1 6 1 2 20 3 125 MHz Half-size Clock Crystal 3.3Volt with TRI_STATE Mini Spring Socket Empty do not stuff Low Voltage Octal Buffer/Line Driver 0.01MF X7R Ceramic Capacitor 33MF Tantalum Chip Capacitor 16WV H3390-125 50935-1 N/A 74LCX540WM ECU-V1H103KBG 293D336X9016D2T MF Electronics AMP N/A National Semiconductor Panasonic Sprague X1 X1 R2 U3-4 C4-5,C11-21,C23-29 C1,C3,C22 2 1 1 1 1 1 5 7 1 1 1 5 4 5 16 1 1 10 1 3 4 1 6 1 1 1 1 10 7 1 1 1 1 1 Qty. Device Description Straight .1" x.1" 20 pin Low Profile Header Gigabit Ethernet Transceiver 2 pin jumper Shunt Euro Terminal Block 2 PIN Part Number 2520-6002UG AM79761 103240-1 15-38-1024 5LEV-02 Manufacture 3M AMD AMP MOLEX Augot Augot/Alcoswitch C&K Concord Cui/Stack Inc. DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE E-F-Johnson E-F-Johnson Fair-Rite Kemet Kemet Kemet Lattice AMP LEDTRONICS LEDTRONICS LEDTRONICS Reference Number HP1-2 U1 W1 W1 PWR1 SW1 P1-5 ZTP1-7 PWR2 R1 R3 R4,R6,R31-33 R5,R7,R34-35 R8,R11,R14,R26,R29 R9,R13,R25,R27,R30,R3646 R10 R12 R15-24 R28 SMA1,SMA6-7 SMA2-5 FB1 C6-9,C30-31 C10 C32 U2 U2 LED0-9 LED10-12,LED14-17 LED13
10 Position Surface Mount Extended Actuator Dip ADE10S Switch Surface Mount Toggle Switch SPDT GT11MSCKE P.C. Pin Power Supply Jack 49.9 ohm Resistor 0 ohm Resistor 0 ohm Resistor 182 ohm Resistor 10K ohm Resistor 301 ohm Resistor 1K ohm Resistor 619 ohm Resistor 4.75K ohm Resistor 750 ohm Resistor Straight PC mount Jack Receptacle End Launch PC mount Jack Receptacle Wound Bead 0.01MF COG Ceramic Capacitor 0.1MF X7R Ceramic Capacitor 1000pf X7R Ceramic Capacitor High Performance EECMOS PLD 3.3volt 28 pin PLCC SMT socket "ULTRA Yellow" Surface Mount LED "HI-EFF Green" Surface Mount LED "ULTRA Red" Surface Mount LED .+3.3V Low Dropout Micropower Voltage Regulator 3A TO-220 Mounting Kit Heat Sink for To-220 SMF Omni-Blok Fuse Block with 750MA Fuse 10-8025-2-03 PJ-002 CRCW080549R9F CRCW1206000J CRCW0805000J CRCW12061820F CRCW08051002F CRCW08053010F CRCW08051001F CRCW08056190F CRCW08054751F CRCW08057500F 142-0701-201 142-0701-801 29-43-666681 C1812C103J5GAC C1206C104K5RAC C0805C102J5RAC GAL22LV10D-4LJ 822066-4 SML10Y4B-TR SML10G4B-TR 'SML10R6C-TR LT1529CT-3.3 Thermalloy Thermalloy 154750
Linear Technology VR1 4880 6078B LittleFuse VR1 VR1 F1
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 6 of 7
GigaPHY(TM) -SD Device
GDPHYSD_1B Eval Board Item Qty. Device Description 42) 43) 44) 45) 46) 47) 48) 49) 1 1 6 6 1 1 2 1 100MF Electrolytic Capacitor Ferrite Bead inductor Part Number 518D107M016AX7S TDKBC50-1206 Manufacture Sprague TDK ASMCO ASMCO Anixter Anixter ASMCO DVE Reference Number C2 FB2 ZM1-6 ZM1-6
NYLON Slotted Round Head Machine Screw 112508 Thread 6-32 Length 3/8" Nylon Threaded Spacer, Thread 6-32 Length 1/2" 1530 H - N -.500 - 1 Lab Bench Power Supply Cable 12" Hookup wire for power supply Red M16878/5-BGE-2 12" Hookup wire for power supply Black Plastic tiedowns 3-3/4" Switching Power Supply M16878/5BGE-0 4200 Wall Power Supply DSA-0301-05
Last Updated 11/04/97 (c) 1997 Advanced Micro Devices Trademark Information 7 of 7
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Gigabit Transceiver Section
LEDS
LED[10:0]
LED[10:0]
LED[10:0]
REFCLK SYSTEM CLK
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REFCLK
REFCLK
SYSCLK.1 Page 6 GIGABIT.1 Pages 2 to 4
LED.1 Page 5
2
EXTERNAL
3
POWER SUPPLY PWRSUPLY.1 Page 7
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SCHEMATIC DIAGRAM
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Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
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GPHYSD_1B
SHEET
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GPHYSD_1B
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EWRAP LOW Normal operation. High internal loopback EN_CDET LOW Current word alignment. LOW disables COM_DET HIGH Enables COM_DET HIGH Enables word resynchronization. 1 20PSHEAD 20PHEAD (OUTPUT) CLK1 3 CLK2 2 +5V 1 GND 20
DVSS
HP1 H.P. 100K OHM TERMINATION ADAPTER (OUTPUT) 01650-63203
HP2 H.P. 100K OHM TERMINATION ADAPTER 01650-63203 20PSHEAD 20PHEAD
CLK1 3 CLK2 2
+5V 1 GND 20
1
D11 8 D10 9 D9 10
D13 6 D12 7
D15 4 D14 5
D11 8 D10 9 D9 10
D13 6 D12 7
D15 4 D14 5
COM_DET
EN_CDET
EWRAP
RCLKN
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
RXD[8]
REFCLK
DVDD
DVDD DVDD DVDD
RXD[9]
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[9]
RCLK
D1 18 D0 19
D3 16 D2 17
D5 14 D4 15
D7 12 D6 13
D8 11
D1 18 D0 19
D3 16 D2 17
D5 14 D4 15
D7 12 D6 13
D8 11
DVSS
TXD[9:0] 301 RC0805 GRN_LED LED1206
1 2
A1 IN
U1 TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] REFCLK EWRAP EN_CDET 11 12 13 22 19 24 18 2 3 4 6 7 8 9 TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] REFCLK EWRAP EN_CDET TEST[1] TEST[2] TEST[3] TEST[4] TX[-] R31
DVDD
TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9]
RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[8] RXD[9] RCLK RCLKN COM_DET
45 44 43 41 40 39 38 35 34 31 30 47
RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9] RCLK RCLKN COM_DET
RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] RXD[9]
A1 IN
RXD[9:0]
301 RC0805
R30 LED17
R27 R26 R29 10K RC0805 10K RC0805
GRN_LED LED1206
1
LED16
2
RXD[7] 36
2 P4 SPDT SPDT 3
DVSS
2
EWRAP 1
REFCLK
COM_DET SMA7
2
3
4
26
DVSS DVDD
61
TX[-]
DVSS
5
2
3
4
C14 RC0805 0.01MF
R33 RX[-] 0R RC0805 1 of 2 AM79761A NC=16,17,27,48,49,64 OZ64PQFP AM79761
52
RX[-]
DVSS
5
2
P5 SPDT SPDT 3 2 1
EN_CDET
20 23
TX[+]
62
TX[+]
RCLK
1
SMA_STR SMA_STR
DVSS
AM79761 RX[+] 54 RX[+] RCLKN 1
SMA6 SMA_STR SMA_STR
R32
DVSS
DVSS
3
3
C28 0.01MF RC0805 RX[+] 1
SMA4 SMA_JEL SMA_JEL 2 3 4 5 TX[+]
R4 0R RC0805
C4 0.01MF RC0805 1
SMA2 SMA_JEL SMA_JEL 2 3 4 5
DVSS
DVSS
DVSS
DVSS
C29 0.01MF RC0805 RX[-] 1
SMA5 SMA_JEL SMA_JEL 2 3 4 5 TX[-]
R6 0R RC0805
C5 0.01MF RC0805 1
SMA3 SMA_JEL SMA_JEL 2 3 4 5
DVSS
DVSS
DVSS
DVSS
182 RC0805
182 RC0805
R5
R7
R34
R35
182 RC0805
182 RC0805
DVSS
DVSS
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DVSS
C24
RC0805 0.01MF
RC0805 0.01MF
SCHEMATIC DIAGRAM
APPROVED BY: DATE
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Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE DWG. NO.
QPHYSD_1B
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U3 74LCX540 From 10-bit receive outputs. RXD[9:0] A1 IN 20PSOLIC DVDD;20 DVSS;10 A2 A3 A4 A5 1 A6 A7 A8 A9 RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 1G 1 2G 19
DVSS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14 13 12 11
LED[0] LED[1] LED[2] LED[3] LED[4] LED[5] LED[6] LED[7]
LED[0] LED[1] LED[2] LED[3] LED[4] LED[5] LED[6] LED[7]
A2 A3 A4 A5 A6 A7 A8 A9
A1 IN
LED[10:0] To LED Block
1
U4 74LCX540 20PSOLIC DVDD;20 DVSS;10 A2 A3
DVDD
A1 IN
RXD[8] RXD[9]
RXD[8] RXD[9] COM_DET
2 3 4 5 6 7 8
A1 A2 A3 A4 A5 A6 A7 A8 1G 1 2G
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14 13 12 11
LED[8] LED[9] LED[10]
LED[8] LED[9] LED[10]
A2 A3 A4
A1 IN
301 RC0805
2
DVDD
2
R9
DVDD DVDD
9
DVDD
19
DVSS
3
SEL[0],SEL[1]=[1,1]....Alternating +/- K28.5 SEL[0],SEL[1]=[0,1]....Pseudo-random SEL[0],SEL[1]=[1,0]....Repeating 00111100xx SEL[0],SEL[1]=[0,0]....Not definded REFCLK
301 RC0805 GRN_LED LED1206
1 2
GRN_LED LED1206 LED15
DVDD
R13
1
R11
LED14 P2 SPDT SPDT 3
DVSS 2 DVDD
10K RC0805 1
10K RC0805
R8
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
U2 GAL22LV10 SEL[0] SEL[0] SEL[1] 16 13 12 11 SEL[1] 10 9 7 6 5 4 3 2 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 CLK/IO GAL22LV10 AMP28PLCC NC=1,8,15,22 DVSS;14 DVDD;28 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 27 26 25 24 23 21 20 19 18 17 TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9]
4.75K RC0805
To 10-bit transmitt inputs. TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] 3 A1 IN TXD[9:0]
2
P3 SPDT SPDT 3 2
DVSS DVDD
1
1 2 3 4 5 6 7 8 9
SW1 DIP SWITCH A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 ADE10S ADE10S C30 RC1812 0.01MF RC1812 0.01MF C31 RC1812 0.01MF C7 Manual Transmitt inputs.
DVSS 20 19 18 17 16 15 14 13 12 11
TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9]
TXD[0] TXD[1] TXD[2] TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9]
A1 IN
10 A10 DVSS
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Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE DWG. NO.
QPHYSD_1B
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1 DVDD DVDD DVDD DVDD DVDD DVDD DVDD
1
U1 5 10 28 50 C12 0.01MF RC0805 C11 0.01MF RC0805 C20 0.01MF RC0805 55 C25 0.01MF RC0805 C19 0.01MF RC0805 C16 0.01MF RC0805 1 14
2
FB2 VDDA 57 C17 0.01MF RC0805 VSSA 58
DVSS DVDD DVDD DVDD DVDD DVDD DVDD
VDDD[1] VDDD[2] VDDD[3] VDDD[4] VDDD[5] VDDD[6]
1 SM_BEAD RC1206
2
59
VDDP[1] VSSD[1] VSSD[2] VSSD[3] VSSD[4] VSSD[5] VSSD[6] VSSD[7] AM79761 Power 2 of 2 AM79761B NC=16,17,27,48,49,64 OZ64PQFP AM79761
DVDD
53 60 63 29 37 42 C27 0.01MF RC0805 C26 0.01MF RC0805 C23 0.01MF RC0805 C13 0.01MF RC0805 C15 0.01MF RC0805 C21 0.01MF RC0805
2
VDDP[2] VDDP[3] VDDT[1] VDDT[2] VDDT[3]
15 21 25 51 56
DVSS DVSS DVSS DVSS DVSS DVSS
VSST[1] VSST[2] VSST[3]
32 33 46
DVSS DVSS DVSS DVSS DVSS DVSS
3
3
1
+
2
C22 33MF [D]7343
DVSS
ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD
SCHEMATIC DIAGRAM
APPROVED BY:
4
DATE
Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE DWG. NO.
GPHYSD_1B
4
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BOARD
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GPHYSD_1B
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DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD DVDD
DVDD
DVDD
DVDD
1
1
301 RC0805 YEL_LED LED1206
1 2
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
301 RC0805
R36 LED0
R37
R38
R39
R40
R41
R42
R44
R45
R46
R43
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
YEL_LED LED1206
GRN_LED LED1206
1
1
1
1
1
1
1
1
1
1
LED1
2
LED2
2
LED3
2
LED4
2
LED5
2
LED6
2
LED7
2
LED8
2
LED9
2
LED10
2
2
2
LED[10:0]
A1 IN
A2 A3 A4 A5 A6 A7 A8 A9
LED[0] LED[1] LED[2] LED[3] LED[4] LED[5] LED[6] LED[7]
R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7]
A1 IN
3
A2 A3 A4
LED[8] LED[9] LED[10]
R[8] R[9] COM_DET
3
ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD
SCHEMATIC DIAGRAM
APPROVED BY:
4
DATE
Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE DWG. NO.
GPHYSD_1B
4
MODULE
LEDS
SHEET
1
BRD. NO.
GPHYSD_1B
REV
D
DATE
B
DRAWN BY
ENGINEER
Steve Cooper
A B
Robert Hartman
C
10-22-1997_10:48
PAGE
D
5 of 7
A
B
C
D
1
1
DVDD DVDD
R10 1K RC0805
C6 0.01MF RC1812 C32 1000pF RC0805
DVSS
P8 +3.3V ENABLES CLK OUTPUT P8 DVSS DISABLE CLK OUTPUT
2 DVDD
X1 2
DVSS
W1 HDR2 JUMPER2
1
1 4
TRI
VCC
14 11 R3
2
7
DVSS
GND
CLK
8
125_OSC_CLKA 0R RC1206
REFCLK
REFCLK
125MHZ_TR XSTAL_XX EMPTY RC1206 49R9 RC0805 R1 R2
SMA1 SMA_STR SMA_STR 5 4 3 2 1 125_EXT_CLK
3
DVSS
DVSS
3
DVSS
ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD
SCHEMATIC DIAGRAM
APPROVED BY:
4
DATE
Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE DWG. NO.
GPHYSD_1B
4
MODULE
SYSCLK
SHEET
1
BRD. NO.
GPHYSD_1B
REV
D
DATE
B
6 of 7
DRAWN BY
ENGINEER
Steve Cooper
A B
Robert Hartman
C
PAGE
D
10-15-1997_13:38
A
B
C
D
From +5Volt Regulated External Power Supply
PWR2 2
1
ZTP1 F1 1 VDDIN 1 750MA 2 VDDIN_A 1 2
FB1 5.5V External 3 4 FB3 W_BEAD C9 0.01MF RC1812 C10 0.1MF RC1206 +
ZTP2
5POS
1
3 EXTPWR PJ002
SMF154
C2 100MF AECAP-D
DVSS SYSGND
PWR1 +V_IN -V_IN PWRCON2 2POS_PWR 1 2
SYSGND
5POS
2
DVDD
5POS
2
750 RC0805
R28
R12 GRN_LED LED1206
1
R25
GRN_LED LED1206
1
1
URED_LED ULED1206
LED11
2 DVSS 3
LED12
2 DVSS
LED13
2
+5POS External Supply Indicator
619 RC0805 ZM1 TP1 MBMT
4 A
3.3V Internal
DVSS DVSS
301 RC0805
5POS 1
+
VR1 1529CT33 TO220-5 ZTP4 3.3V Internal 5 IN OUT 1 1
+ DVDD
[OFF] Output ON [ON] Output OFF R14 10K RC0805
C3 33MF [D]7343
DVSS
2
P1 SPDT SPDT 3 2 1
4
SD GND1 3
SENSE GND2 6
2 2
C1 33MF [D]7343
DVSS
C8
3
RC1812 0.01MF
DVSS
DVSS
DVSS
ZTP3
ZTP7
ZTP6
ZTP5
3.3V Internal Shutdown Switch [LOW] The Output is turned off.
DVSS
DVSS
DVSS
DVSS
[HIGH] The Output is turned on.
ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD
ZM3 TP1 MBMT ZM6 TP1 MBMT ZM5 TP1 MBMT ZM4 TP1 MBMT ZM2 TP1 MBMT
SCHEMATIC DIAGRAM
APPROVED BY: DATE
Gigabit Ethernet Transceiver 1000Base-X Eval. Brd.
SIZE
1
4
ZZ3 FIDUCIAL
1
ZZ2 FIDUCIAL
1
ZZ1 FIDUCIAL
1
MODULE
PWRSUPL
SHEET
DWG. NO.
GPHYSD_1B
BRD. NO.
GPHYSD_1B
REV
D
DATE
B
7 of 7
T3
T3
T3
DRAWN BY
ENGINEER
Steve Cooper
B
Robert Hartman
C
10-23-1997_14:32
PAGE
D

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