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128Mb: x4, x8, x16 SDRAM 3.3V
SYNCHRONOUS DRAM
* * * * * * * * * * *
Features:
Intel PC-100 (3-3-3) or PC133 (3-3-3) compatible Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access precharge time Programmable burst lengths: 1, 2, or 4 using Interleaved Burst Addressing Auto Precharge and Auto Refresh modes 64ms, 4,096-cycle refresh quad-row refresh, (15.6s/row) Self Refresh mode 1 LVTTL-compatible inputs and outputs Single +3.3V 0.3V power supply The x16 devices are optimized for both single and dual rank DIMM applications. The x8 devices are optimized for single rank DIMM applications.
Options:
Family: SpecTek Memory Configuration: 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) Design ID SDRAM 128 Megabit Design (Call SpecTek Sales for details on availability of "x" placeholders) Voltage and Refresh: 3.3V, Auto Refresh, 4K refresh 3.3V, Self or Auto Refresh1, 4K refresh Package Types: 54-pin plastic TSOP (400 mil) 60-ball FBGA (8mm x 16mm) 60-ball FBGA (11mm x 13mm) Timing Types: PC100 (3-3-3) PC133 (3-3-3) Part number example:
(For part numbers prior to December 2004, refer to page 9 for decoding.)
Designation:
SAA 32M4 16M8 8M16 Yx5x
L4 M4 TK FB2 FC2 -8A -75A
NOTES: 1. Only when specified. Consult Sales 2. Not available in x16 configuration
General Description:
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. Each is internally configured as a quad-bank DRAM. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered
SAA16M8Y95AL4TK-75A
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
coincident with the READ or WRITE commands are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, or 4 locations with burst terminate option using the Burst Interleaved Addressing mode only. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the abilities to synchronously burst data at a high data rate with automatic columnaddress generation, to interleave between internal banks in order to hide precharge time, and to randomly change column addresses on each clock cycle during a burst access. The x8 devices are optimized for single bank DIMM applications. The x16 devices are available for both single and dual bank DIMM applications. _________________________________________ CAPACITANCE:
Parameter Input Capacitance: A0 - A11, BA0, BA1 Input Capacitance: RAS#, CAS#, WE#, DQM, CLK, CKE, CS# Input/Output Capacitance: DQs Symbol CI1 CI2 CIO Min 1 1 1 Max 5 5 6 Units pF pF pF
Disclaimer: Except as specifically provided in this document, SpecTek makes no warranties, expressed or implied, including, but not limited to, any implied warranties of merchantability or fitness for a particular purpose. Any claim against SpecTek must be made within one year from the date of shipment from SpecTek, and SpecTek has no liability thereafter. Any liability is limited to replacement of the defective items or return of amounts paid for defective items (at buyer's election). In no event will SpecTek be responsible for special, indirect, consequential or incidental damages, even if SpecTek has been advised for the possibility of such damages. SpecTek's liability from any cause pursuant to this specification shall be limited to general monetary damages in an amount not to exceed the total purchase price of the products covered by this specification, regardless of the form in which legal or equitable action may be brought against SpecTek.
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ABSOLUTE MAXIMUM RATINGS:
Voltage on Vdd Supply relative to Vss Operating Temperature TA (Ambient) Storage Temperature Power Dissipation Short Circuit Output Current -1 to +4.6V 25 to +70 C -55 to +150 C 1W 50 mA
Stresses beyond these may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or beyond these conditions is not implied. Exposure to these conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Parameter Supply Voltage Input High (Logic 1) Voltage, All inputs Input Low (Logic 0) Voltage, All inputs Input Leakage Current Any input = 0V < VIN < Vdd All other pins not under test = 0V Output Leakage Current DQs are disabled; 0V < VOUT < VddQ Output High Voltage (IOUT = -4 mA) Output Low Voltage (IOUT = 4 mA) Symbol Vdd/Vddq VIH VIL II IOZ VOH VOL Min 3.0 2.2 -0.3 -10 -10 2.4 Max 3.6 Vdd + .3 0.8 10 10 0.4 Units V V V A A V V
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vdd = 3.3V 10%V, Temp. = 25 to 70 C
Supply Current OPERATING CURRENT: ACTIVE mode, burst = 1, READ or WRITE, tRC > tRC (MIN), one bank active, CL=3 STANDBY CURRENT: POWER-DOWN mode, CKE = LOW, Standard parts no accesses in progress Self refresh parts STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks idle STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks active after tRCD met, no accesses in progress. OPERATING CURRENT: BURST mode after tRCD met, continuous burst, READ, WRITE, all banks active, CL=3 AUTO REFRESH CURRENT tRC > tRC (MIN) CL = 3 AUTO REFRESH CURRENT tRC=15.6us CL = 3 SELF REFRESH CURRENT (Self refresh parts only, part M) Symbol Icc1 Idd2 Idd2 Icc3 Icc4 Icc5 Icc6 Icc7 Idd8 -75A 165 9 3 75 75 165 265 50 3 -8A 140 9 3 60 50 145 245 50 3 Units mA mA mA mA mA mA mA mA mA Notes 1, 2, 3, 4 32 32 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4
Notes 1. All voltages referenced to Vss. 2. An initial pause of 100 s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensure. (Vdd and VddQ must be powered-up simultaneously Vss and VssQ must be at the same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. Icc specifications are tested after the device is properly initialized. tCK= 10ns for -8 and tCK=7.5ns for -75A.
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V 10%V, Temp. = 25 to 70C
AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) CL = 3 Access time from CLK (positive edge) CL = 2 Address hold time Address setup time CLK high level width CLK low level width Clock cycle time CL = 3 Clock cycle time CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high impedance time Data-out low impedance time Data-out hold time ACTIVE to PRECHARGE command period AUTO REFRESH to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4096 cycles) PRECHARGE command period ACTIVE bank A to bank B command period Transition time Write recovery time Exit SELF REFRESH to ACTIVE command READ/WRITE command to READ/WRITE command CKE to clock disable or power down entry mode CKE to clock enable or power down exit setup SYMBOL tAC tAC tAH tAS tCH tCL tCK tCK tCKH tCKS tCMH tCMS tDH tDS tHZ tLZ tOH tRAS tRC tRCD tREF tRP tRRD tT tWR tXSR tCCD tCKED tPED -75A MIN -75A MAX 5.4 N/A -8A MIN -8A MAX 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns tCK tCK tCK tCK NOTES
0.8 1.5 2.5 2.5 7.5 N/A 0.8 1.5 0.8 1.5 0.8 1.5 9 1 2.7 44 60 22.5 22.5 15 0.3 20 8 1 1 1
1 2 3 3 10 1 2 1 2 1 2 9 2 3 50 80 30 30 20 0.3 20 8 1 1 1
4
16K
16K
64
64
2
2
3 1 2 2
AC ELECTRICAL CHARACTERISTICS: Vdd = 3.3V 10%V, Temp. = 25 to 70C
AC CHARACTERISTICS PARAMETER DQM to input data delay WRITE command to input data delay Data-in to ACTIVATE command w/ Auto precharge Data-in to precharge Last data-in to precharge command LOAD MODE REGISTER command to command Data-out to high impedance from precharge SYMBOL tDQD tDWD tDAL tDPL tRDL tMRD tROH -75A MIN 0 0 5 2 2 2 3 -75A MAX -8 MIN 0 0 5 2 2 2 3 -8 MAX UNITS tCK tCK tCK tCK tCK tCK tCK NOTES 1 1 3 2, 3 1 1 1
NOTES: 1. Clocks required specified by JEDEC functionality and not dependent on any timing parameter. 2. Timing actually specified by tCKS, clock(s) specified as a reference only at a minimum cycle rate. 3. Timing actually specified by tWR plus tRP clock(s) specified as a reference only at a minimum cycle rate. 4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. The last valid data element will meet tOH before going high-Z. 5. Based on tCK = 10ns for -8 and tCK = 7.5ns for -75a
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
54-PIN PLASTIC TSOP (400 mil)
(Package TK)
NOTE:
1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
5
www.spectek.com
SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
6
www.spectek.com
SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
FBGA "FB" PACKAGE 60-pin, 8mm x 16mm
NOTE:
1. All dimensions in millimeters. 2. Recommended Pad size for PCB is 0.33mm0.025mm.
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 SDRAM 3.3V
PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004 Options:
Architecture: 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) Voltage and Refresh: 3.3V, Auto Refresh 3.3V, Self or Auto Refresh1 Device Configuration: 32 Meg x 4 16 Meg x 8 8 Meg x 16 Package Types: 54-pin plastic TSOP (400 mil) 60-ball FBGA (8mm x 16mm) 60-ball FBGA (11mm x 13mm) Timing Types: PC100 (3-3-3) PC133 (3-3-3) Part number example: S80016LK7TW-8A
Marking:
S40032LK8 S80016LK7 S16008LK9 LK MK 8 7 9 TW FB2 FC2 -8A -75A
NOTES: 1. Only when specified. Consult Sales 2. Not available in x16 configuration http://www.spectek.com/menus/part_guides.asp
PDF: 09005aef807827f6 / Source: 09005aef807825bd 128Mb SDRAM Rev: 11/29/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek

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