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Freescale Semiconductor Advance Information
Document Number: MC34716 Rev 4.0, 12/2008
1.0 MHz Dual Switch-Mode DDR Power Supply
The 34716 is a highly integrated, space-efficient, low cost, dual synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with its second output having the ability to track an external reference voltage. it provides a full power supply solution for DoubleData-Rate (DDR) Memories. Channel one provides a source only, 5.0 A drive capability, while channel two can sink and source up to 3.0 A. Both channels are highly efficient with tight output regulation. With its high current drive capability, channel one can be used to supply the VDDQ to the memory chipset. The second channel's ability to track a reference voltage makes it ideal to provide the termination voltage (VTT) for modern data buses. The 34716 also provides a buffered output reference voltage (VREFOUT) to the memory chipset The 34716 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. It is housed in a Pb-free, thermally enhanced, and space efficient 26-Pin Exposed Pad QFN. Features * 50 m integrated N-channel power MOSFETs * Input voltage operating range from 3.0 to 6.0 V * 1% accurate output voltages, ranging from 0.7 to 3.6 V * The second output tracks 1/2 an external reference voltage * 1% accurate buffered reference output voltage * Programmable switching frequency range from 200 kHz to 1.0 MHz * Programmable soft start timing for channel one * Over-current limit and short-circuit protection on both channels * Thermal shutdown * Output over-voltage and under-voltage detection * Active low power good output signal * Active low standby and shutdown inputs * Pb-free packaging designated by suffix code EP.
34716
3.0 V to 6.0 V VIN
34716
DUAL SWITCH-MODE DDR POWER SUPPLY
EP SUFFIX 98ASA10728D 26-PIN QFN
ORDERING INFORMATION
Device MC34716EP/R2 Temperature Range (TA) -40 to 85C Package 26 QFN
VIN VDDQ PVIN1 BOOT1 SW1 VOUT1 INV1 COMP1 PGND1 VDDI FREQ ILIM1 GND
PVIN2 VREFIN BOOT2 SW2 VOUT2 INV2 COMP2 VREFOUT PGND2 PG STBY SD VIN
VDDQ VTT
VDDQ
Termination Resistors DDR Memory Controller
DDR Memory Chipset VREF
Memory Bus
MCU
Figure 1. 34716 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-8. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
STBY PG M1 System Reset
SD
Thermal Monitoring System Control Discharge VBG ILIM2 Bandgap Regulator VDDI Internal Voltage Regulator VIN
FREQ
Oscillator Buck Control Logic ISENSE2 ISENSE1
Current Monitoring
ILIM1
ILIM1
BOOT1 PVIN1 M4 SW1 M5 PGND1 COMP1 ISENSE
M2 VIN
M3 VIN M6
BOOT2 PVIN2
Gate Driver
FSW
FSW
Gate I Driver SENSE M7
SW2
INV1 VOUT1 M8
VBG M9 Discharge Discharge
CHANNEL 1
M10 Discharge
CHANNEL 2 +
VREFIN
GND
VREFOUT
Figure 2. 34716 Simplified Internal Block Diagram
34716
-
2
-
-
+
Error Amplifier
-
Error Amplifier
PWM Comparator Ramp Generator
PWM Comparator Ramp Generator
+
PGND2 COMP2
-
+
+
INV2 VOUT2
Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
FREQ
STBY
26 25 24 23 22 21 20 19 BOOT1 1 PVIN1 2 PVIN1 SW1 3 SW1 PGND1 4 PGND1 VOUT1 5 6 INV1 7 COMP1 8 VREFIN 9 VREFOUT 10 PG 11 12 13 COMP2 INV2 SD 15 PGND2 14 VOUT2 Transparent Top View PIN 27 16 SW2 PGND2 17 PVIN2 SW2 18 BOOT2 PVIN2
Figure 3. 34716 Pin Connections Table 1. 34716 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name BOOT1 PVIN1 SW1 PGND1 VOUT1 INV1 COMP1 VREFIN VREFOUT PG SD COMP2 INV2 Pin Function Passive Supply Output Ground Output Input Input Input Output Output Input Input Input Formal Name Bootstrap Power Input Voltage Switching Node Power Ground Output Voltage Discharge Path Error Amplifier Inverting Input Buck Convertor Compensation Input Reference Voltage Input Reference Voltage Output Power Good Output Signal Shutdown Input Buck Convertor Compensation Input Error Amplifier Inverting Input Definition Channel 1 Bootstrap capacitor input pin Channel 1 Buck converter power input Channel 1 Buck converter switching node Channel 1 Buck converter and discharge MOSFETs power ground Channel 1 Buck converter output voltage discharge pin Channel 1 Buck converter error amplifier inverting input Channel 1 Buck converter external compensation network input Voltage tracking reference voltage input This is a buffered reference voltage output It is an active low open drain power good status reporting output Shutdown mode input control pin Channel 2 Buck converter external compensation network input Channel 2 Buck converter error amplifier inverting input
ILIM1
VDDI
GND
VIN
VIN
NC
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Analog Integrated Circuit Device Data Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34716 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number 14 15 16 17 18 19 20 21 22,23 24 25 26 27 Pin Name VOUT2 PGND2 SW2 PVIN2 BOOT2 ILIM1 NC FREQ VIN GND VDDI STBY GND Pin Function Output Ground Output Power Input Input None Input Power Ground Output Input Ground Formal Name Output Voltage Discharge Path Power Ground Switching Node Power Input Voltage Bootstrap Input Soft Start Adjustment Input No Connect Frequency Adjustment Input Input Supply Voltage Signal Ground Internal Supply Voltage Standby Input Thermal Pad Definition Channel 2 Buck converter output voltage discharge pin Channel 2 Buck converter and discharge MOSFETs power ground Channel 2 Buck converter switching node Channel 2 Buck converter power input Channel 2 Bootstrap capacitor input pin Channel 1 soft start adjustment No internal connections to this pin The buck converters switching frequency adjustment input Power supply voltage of the IC Analog ground of the IC Internal supply voltage output Standby mode input control pin Thermal pad for heat transfer. Connect the thermal pad to the analog ground and the ground plane for heat sinking.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Input Supply Voltage (VIN) Pin High Side MOSFET Drain Voltage (PVIN1, PVIN2) Pins Switching Node (SW1, SW2) Pins BOOT1, BOOT2 Pins (Referenced to SW1, SW2 Pins Respectively) PG, VOUT1, VOUT2, SD, and STBY Pins VDDI, FREQ, ILIM1, INV1, INV2, COMP1, COMP2, VREFIN, and VREFOUT Pins Channel 1 Continuous Output Current(1) Channel 2 Continuous Output Current(1) ESD Voltage(2) Human Body Model Machine Model (MM) Charge Device Model THERMAL RATINGS Operating Ambient Temperature(3) Storage Temperature Peak Package Reflow Temperature During Reflow(4),(5) Maximum Junction Temperature Power Dissipation (TA = 85C)(6) Notes 1. Continuous output current capability so long as TJ is TJ(MAX). 2. 3. 4. 5. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Maximum power dissipation at indicated ambient temperature. TA TSTG TPPRT TJ(MAX) PD -40 to 85 -65 to +150 Note 5 +150 2.03 C C C C W VESD1 VESD2 VESD3 2000 200 750 VIN PVIN VSW VBOOT - VSW
-
Symbol
Value
Unit
-0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 3.0 +5.0 3.0
V V V V V V A A V
IOUT1 IOUT2
6.
34716
Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RESISTANCE(7) Thermal Resistance, Junction to Ambient, Single-layer Board (1s)(8) Thermal Resistance, Junction to Ambient, Four-layer Board (2s2p) Thermal Resistance, Junction to Board
(10) (9)
Symbol
Value
Unit
RJA RJMA RQJB
93 32 13.6
C/W C/W C/W
Notes 7. The PVIN, SW, and PGND pins comprise the main heat conduction paths. 8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are thermal vias connecting the package to the two planes in the board. (per JESD51-5) 10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic IC INPUT SUPPLY VOLTAGE (VIN) Input Supply Voltage Operating Range Input DC Supply Current(11) (Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs) Input DC Supply Current(11) (Standby Mode, SD = 1 & STBY = 0) Input DC Supply Current(11) (Shutdown Mode, SD = 0 & STBY = X) INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI) Internal Supply Voltage Range VDDI 2.35 2.5 2.65 V IINOFF 100 A IINQ 25 mA VIN IIN 3.0 6.0 35
V
Symbol
Min
Typ
Max
Unit
mA
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1) CH 1 High Side MOSFET Drain Voltage Range Output Voltage Adjustment Range Output Voltage Line
(12)
PVIN VOUTHI1 REGLN1 REGLD1 VREF1 VUVR1 VOVR1 IOUT1 ILIM1 VILIM1 ISHORT1
2.5 0.7 -1.0 -1.0
-
6.0 3.6 1.0 1.0
V V % %
Accuracy(12),(13),(14)
Regulation(12)
(Normal Operation, VIN = 3.0 to 6.0 V, IOUT1 = +5.0 A) Load Regulation(12) (Normal Operation, IOUT1 = 0.0 to 5.0 A) Error Amplifier Reference Voltage(12) Output Under-voltage Threshold Output Over-voltage Threshold Continuous Output Current Over-current Limit Soft Start Adjusting Reference Voltage Range Short-circuit Current Limit High Side N-CH Power MOSFET (M4) (IOUT1 = 1.0 A, VBOOT1 - VSW1= 3.3 V) Notes 11. 12. 13. 14. Section "MODES OF OPERATION", page 16 has a detailed description of the different operating modes of the 34716 Design information only, this parameter is not production tested. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended. 1% is assured at room temperature. RDS(ON)(12) -8.0 1.5 1.25 10 0.7 6.5 8.5 -1.5 8.0 5.0 VDDI 50 V % % A A V A m -1.0 1.0 %
RDS(ON)HS1
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Low Side N-CH Power MOSFET (M5) RDS(ON)(15) (IOUT1 = 1.0 A, VIN = 3.3 V) M2 RDS(ON) (VIN = 3.3 V, M2 is on) SW1 Leakage Current (Standby and Shutdown modes) PVIN1 Pin Leakage Current (Shutdown Mode) Error Amplifier DC Gain(15) Error Amplifier Unit Gain Bandwidth(15) Error Amplifier Slew Rate(15) Error Amplifier Input Offset(15) INV1 Pin Leakage Current Thermal Shutdown Threshold(15) Thermal Shutdown Hysteresis(15) AEA UGBWEA SREA OFFSETEA IINV1 TSDFET1 TSDHYFET1 -3.0 -1.0 150 3.0 7.0 0 170 25 3.0 1.0 dB MHz V/s mV A C C ISW IPVIN1 -10 -10 10 10 A A RDS(ON)M2 2.0 4.0 Symbol RDS(ON)LS1 Min 10 Typ Max 50 Unit m
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2) CH 2 High Side MOSFET Drain Voltage Range Output Voltage Adjustment Output Voltage Line Regulation Range(15) PVIN VOUTHI2 REGLN2 REGLD2 VREF2 VUVR2 VOVR2 IOUT2 ILIM2 ISHORT2 RDS(ON)HS2 RDS(ON)LS2 2.5 0.7 -1.0 -1.0 6.0 1.35 1.0 1.0 V V % %
Accuracy(15),(16),(17)
(15)
(Normal Operation, VIN = 3.0 to 6.0 V, IOUT2 = 3.0 A) Load Regulation(15) (Normal Operation, IOUT2 = -3.0 to 3.0 A) Error Amplifier Common Mode Voltage Range(15),(18) Output Under-voltage Threshold Output Over-voltage Threshold Continuous Output Current Over-current Limit (Sinking and Sourcing) Short-circuit Current Limit (Sinking and Sourcing) High Side N-CH Power MOSFET (M6) RDS(ON)(15) (IOUT2 = 1.0 A, VBOOT2 - VSW2= 3.3 V) Low Side N-CH Power MOSFET (M7) RDS(ON)(15) (IOUT2 = 1.0 A, VIN = 3.3 V) Notes 15. 16. 17. 18. Design information only, this parameter is not production tested. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended 1% is assured at room temperature The 1% output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7V 10 50 m 0.0 -8.0 1.5 -3.0 10 4.0 6.5 1.35 -1.5 8.0 3.0 50 V % % A A A m -1.0 1.0 %
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic M3 RDS(ON) (VIN = 3.3 V, M3 is on) SW2 Leakage Current (Standby and Shutdown modes) PVIN2 Pin Leakage Current (Standby and Shutdown Modes) Error Amplifier DC Gain(19) Error Amplifier Unit Gain Bandwidth Error Amplifier Slew Rate(19)
(19) (19)
Symbol RDS(ON)M3 ISW IPVIN2 AEA UGBWEA SREA OFFSETEA IINV2 TSDFET2 TSDHYFET2
Min 2.0
Typ -
Max 4.0
Unit
-10 -10
-
10 10
A A
-3.0 -1.0 -
150 3.0 7.0 0 170 25
3.0 1.0 -
dB MHz V/s mV A C C
Error Amplifier Input Offset INV2 Pin Leakage Current Thermal Shutdown
Threshold(19)
(19)
Thermal Shutdown Hysteresis OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range TRACKING (VREFIN, VREFOUT, VOUT1, VOUT2) VREFIN External Reference Voltage Range(19) VREFOUT Buffered Reference Voltage Range VREFOUT Buffered Reference Voltage Accuracy(20)
VFREQ
0.0
-
VDDI
V
VREFIN VREFOUT IREFOUT IREFOUTLIM RTDR(M10) RTDR(M8) RTDR(M9) IVOUTLKG2
0.0 0.0 -1.0 0.0 -1.0
11 50 50 50 -
2.7 1.35 1.0 8.0 1.0
V V % mA mA A
VREFOUT Buffered Reference Voltage Current Capability VREFOUT Buffered Reference Voltage Over-current Limit VREFOUT Total Discharge VOUT1 Total Discharge Resistance(19)
Resistance(19)
(19)
VOUT2 Total Discharge Resistance VOUT2 Pin Leakage Current (Standby Mode, VOUT2 = 3.6 V)
CONTROL AND SUPERVISORY (STBY, SD, PG) STBY High Level Input Voltage STBY Low Level Input Voltage STBY Pin Internal Pull-up Resistor SD High Level Input Voltage SD Low Level Input Voltage SD Pin Internal Pull-up Resistor PG Low Level Output Voltage (IPG = 3.0 mA) PG Pin Leakage Current (M1 is off, Pulled up to VIN) Notes 19. Design information only, this parameter is not production tested. 20. The 1% accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature. 34716 IPGLKG 1.0 A VSTBYHI VSTBYLO RSTBYUP VSDHI VSDLO RSDUP VPGLO 2.0 1.0 2.0 1.0 0.4 2.0 0.4 2.0 0.4 V V M V V M V
Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1) Switching Node (SW1) Rise Time(21) (PVIN = 3.3 V, IOUT1 = 5.0 A) Switching Node (SW1) Fall Time(21) (PVIN = 3.3 V, IOUT1 = 5.0 A) Minimum OFF Time Minimum ON Time Soft Start Duration (Normal Mode) ILIM1: 1.25 to 1.49 V 1.5 to 1.81 V 1.82 to 2.13 V 2.14 to 2.5 V Over-current Limit Timer Over-current Limit Retry Timeout Period Output Under-voltage/Over-voltage Filter Delay Timer tLIM1 tTIMEOUT1 tFILTER1 tOFFMIN tONMIN tSS1 80 5.0 3.2 1.6 0.8 0.4 10 120 25 ms ms s 150 0(22) ns ns ms tFALL1 5.0 ns tRISE1 8.0 ns
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2) Switching Node (SW2) Rise Time(21) (PVIN = 3.3 V, IOUT2 = 3.0 A) Switching Node (SW2) Fall Time(21) (PVIN = 3.3 V, IOUT2 = 3.0 A) Minimum OFF Time Minimum ON Time Soft Start Duration (Normal Mode) Over-current Limit Timer Over-current Limit Retry Timeout Period Output Under-voltage/Over-voltage Filter Delay Timer OSCILLATOR (FREQ)(23) fSW fSW 1.0 MHz tOFFMIN tONMIN tSS2 tLIM2 tTIMEOUT2 tFILTER2 80 5.0 150 100 1.6 10 120 25 ns ns ms ms ms s tFALL2 12.0 ns tRISE2 28 ns
Oscillator Default Switching Frequency (FREQ = GND) Oscillator Switching Frequency Range
200
-
1000
kHz
Notes 21. Design information only, this parameter is not production tested. 22. The regulator has the ability to enter into pulse skip mode when the inductor current ripple reaches the threshold for the LS zero detect, which has a typical value of 500 mA. 23. Oscillator Frequency tolerance is 10%.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic CONTROL AND SUPERVISORY (STBY, SD, PG) PG Reset Delay Thermal Shutdown Retry Timeout Period Minimum OFF Time Minimum ON Time Notes 24. Design information only, this parameter is not production tested.
(24)
Symbol
Min
Typ
Max
Unit
tPGRESET tTIMEOUT tOFFMIN tONMIN
8.0 80 -
150 100
12 120 -
ms ms ns ns
ELECTRICAL PERFORMANCE CURVES
VDDQ (VOUT1) % Efficiency vs IOUT
100% 95% 90% 85% Efficiency 80% 75% 70% 65% 60% 55% 50% 0.0 0.5 1.0 1.5 2.0 2.5 IOUT, Amps 3.0 3.5 4.0 4.5 5.0
VIN = 5V Fs = 1MHz TA=25C
VTT (VOUT2) % Efficien cy vs IOUT 100% 95% 90% 85% Efficiency 80% 75% 70% 65% 60% 55% 50% 0 0.5 1 1.5 IOUT, Amps 2 2.5 3
VIN = 5V Fs = 1MHz TA=25C
Figure 4. % Efficiency vs. IOUT
Figure 5. % Efficiency vs. IOUT
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
In modern microprocessor/memory applications, address commands and control lines require system level termination to a voltage (VTT) equal to 1/2 the memory supply voltage (VDDQ). Having the termination voltage at midpoint, the power supply insures symmetry for switching times. Also, a reference voltage (VREF) that is free of any noise or voltage variations is needed for the DDR SDRAM input receiver, VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will effect the setup and hold time of the memory. To comply with DDR requirements and to obtain best performance, VTT and VREF need to be tightly regulated to track 1/2 VDDQ across voltage, temperature, and noise margins. VTT should track any variations in the DC VREF value (VTT = VREF +/- 40 mV), (See Figure 6) for a DDR system level diagram. The 34716 supplies the VDDQ, VTT and a buffered VREF output. To ensure compliance with DDR specifications, the VDDQ line is applied to the VREFIN pin and divided by 2 internally through a precision resistor divider. This internal voltage is then used as the reference voltage for the VTT output. The same internal voltage is also buffered to give the VREF voltage at the VREFOUT pin for the application to use without the need for an external resistor divider. The 34716 provides the tight voltage regulation and power sequencing/ tracking required along with handling the DDR peak transient current requirements. It gives the user a complete DDR power supply solution with optimum performance. Buffering the VREF output helps its immunity against noise and load changes. The 34716 utilizes a voltage mode synchronous buck switching converter topology with integrated low RDS(ON) (50 m) N-channel power MOSFETs to provide an output voltage with an accuracy of less than 2.0% output voltage. It has a programmable switching frequency that allows for flexibility and optimization over the operating conditions and can operate at up to 1.0 MHz to significantly reduce the external components size and cost. The 34716 can supply up to 5.0 A from one output and sink and source up to 3.0 A of continuous current from the other output. It provides protection against output over-current, over-voltage, undervoltage, and over-temperature conditions. It also protects the system from short circuit events. It incorporates a power good output signal to alert the host when a fault occurs. For boards that support the Suspend-To-RAM (S3) and the Suspend-To-Disk (S5) states, the 34716 offers the STBY and the SD pins respectively. Pulling any of these pins low, puts the IC in the corresponding state. By integrating the control/supervisory circuitry along with the Power MOSFET switches for the buck converter into a space-efficient package, the 34716 offers a complete, smallsize, cost-effective, and simple solution to satisfy the needs of DDR memory applications. Besides DDR memory termination, the 34716 can be used to supply termination for other active buses and graphics card memory. It can be used in Netcom/Telecom applications like servers. It can also be used in desktop motherboards, game consoles, set top boxes, and high end high definition TVs.
VDDQ
VTT
VDDQ
RS
BUS
RT VREF
DDR Memory Controller
DDR Memory Input Receiver
Figure 6. DDR System Level Diagram
FUNCTIONAL PIN DESCRIPTION BOOTSTRAP INPUT (BOOT1, BOOT2)
Bootstrap capacitor input pin. Connect a capacitor (as discussed in Bootstrap capacitor on page 21) between this pin and the SW pin of the respective channel to enhance the gate of the high-side Power MOSFET during switching.
SWITCHING NODE (SW1, SW2)
Buck converter switching node. This pin is connected to the output inductor.
POWER GROUND (PGND1, PGND2)
Buck converter and discharge MOSFETs power ground. It is the source of the buck converter low side power MOSFET.
POWER INPUT VOLTAGE (PVIN1, PVIN2)
Buck converter power input voltage. This is the drain of the buck converter high side power MOSFET.
COMPENSATION INPUT (COMP1, COMP2)
Buck converter external compensation network connects to this pin. Use a type III compensation network.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
ERROR AMPLIFIER INVERTING INPUT (INV1, INV2)
Buck converter error amplifier inverting input. Connect the VDDQ voltage (channel 1) to INV1 pin through a resistor divider and connect the VTT voltage (channel 2) directly to INV2 pin.
STANDBY INPUT (STBY)
If this pin is tied to the GND pin, the device will be in Standby mode. If left unconnected or tied to the VIN pin, the device will be in Normal mode. The pin has an internal pullup of 1.5 M. This input accepts the S3 (Suspend-To-RAM) control signal.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT1, VOUT2)
Buck converters output voltage are connected to these pins. It only serves as the output discharge path once the SD signal is asserted.
SHUTDOWN INPUT (SD)
If this pin is tied to the GND pin, the device will be in Shutdown Mode. If left unconnected or tied to the VIN pin, the device will be in Normal mode. The pin has an internal pullup of 1.5 M. This input accepts the S5 (Suspend-To-Disk) control signal.
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
This is the output of the internal bias voltage regulator. Connect a 1.0 F, 6.0 V low ESR ceramic filter capacitor between this pin and the GND pin. Filtering any spikes on this output is essential to the internal circuitry stable operation.
REFERENCE VOLTAGE OUTPUT (VREFOUT)
This is a buffered reference voltage output that is equal to 1/2 VREFIN. It has a 10 mA current drive capability. This output is used as the VREF voltage rail and should be filtered against any noise. Connect a 0.1 F, 6.0 V low ESR ceramic filter capacitor between this pin and the GND pin and between this pin and VDDQ rail. VREFOUT is also used as the reference voltage for the buck converter error amplifier.
SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are referenced to this pin voltage.
INPUT SUPPLY VOLTAGE (VIN)
IC power supply input voltage. Input filtering is required for the device to operate properly.
REFERENCE VOLTAGE INPUT (VREFIN)
The output of channel two will track 1/2 the voltage applied at this pin.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to report the status of the device to a host. This output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. This output activates after a 10ms delay and must be pulled up by an external resistor to a supply voltage like VIN.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converters switching frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and GND pins. The default switching frequency (FREQ pin connected to ground, GND) is set at 1.0 MHz.
CHANNEL 1 SOFT START ADJUSTMENT INPUT (ILIM1)
Channel one Soft Start can be adjusted by applying a voltage between 1.25 V and VDDI.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34716 - Functional Block Diagram
Internal Bias Circuits
System Control and Logic
Oscillator
Protection Functions
Control and Supervisory Functions
Tracking and Sequencing
2 x Buck Converter
Figure 7. Block Illustration
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary supply voltages and bias currents for the internal circuitry. It consists of: * Internal voltage supply regulator: This regulator supplies the VDDI voltage that is used to drive the digital/ analog internal circuits. It is equipped with a Power-OnReset (POR) circuit that watches for the right regulation levels. External filtering is needed on the VDDI pin. This block will turn off during the shutdown mode. * Internal bandgap reference voltage: This supplies the reference voltage to some of the internal circuitry. * Bias circuit: This block generates the bias currents necessary to run all of the blocks in the IC.
PROTECTION FUNCTIONS
This block contains the following circuits: * Over-current Limit and Short-circuit Detection: This block monitors the output of the buck converters for over-current conditions and short-circuit events and alerts the system control for further command. * Thermal limit detection: This block monitors the temperature of the device for overheating events. If the temperature rises above the thermal shutdown threshold, this block will alert the system control for further commands. * Output over-voltage and under-voltage monitoring: This block monitors the buck converters output voltages to ensure they are within regulation boundaries. If not, this block alerts the system control for further commands.
SYSTEM CONTROL AND LOGIC
This block is the brain of the IC where the device processes data and reacts to it. Based on the status of the STBY and SD pins, the system control reacts accordingly and orders the device into the right status. It also takes inputs from all of the monitoring/protection circuits and initiates power up or power down commands. It communicates with the buck converter to manage the switching operation and protects it against any faults.
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It contains the following circuits: * Standby Control Input: An outside host can put the 34716 device into standby mode (S3 or Suspend-ToRAM mode) by sending a logic "0" to the STBY pin. * Shutdown Control Input: An outside host can put the 34716 device into shutdown mode (S5 or Suspend-ToDisk mode) by sending a logic "0" to the SD pin. * Power Good Output Signal: The 34716 can communicate to an outside host that a fault has occurred by pulling the voltage on the PG pin high
OSCILLATOR
This block generates the clock cycles necessary to run the IC digital blocks. It also generates the buck converters switching frequency. The switching frequency can be programmed by connecting a resistor divider to the FREQ pin, between VDDI and GND pins (See Figure 1, page 1).
through a pull-up resistor.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
TRACKING AND SEQUENCING
This block allows the output of channel 2 of the 34716 to track 1/2 the voltage applied at the VREFIN pin. This allows the VREF and VTT voltages to track 1/2 VDDQ and assures that none of them will be higher than VDDQ at any point during normal operating conditions. For power down during a shutdown (S5) mode, the 34716 uses internal discharge MOSFETs (M8, M9, and M10 on Figure 2, page 2) to discharge VDDQ, VTT, and VREF respectively. These discharge MOSFETs are only active during shutdown mode. Using this block along with controlling the SD and STBY pins can offer the user the device for power sequencing by controlling when to turn the 34716 outputs on or off.
operation. The buck converter is a high performance, fixed frequency (externally adjustable), Syncronous buck PWM
voltage-mode control with a minimum on time of 100ns.
It drives integrated 50 m N-channel power MOSFETs saving board space and enhancing efficiency. The switching regulator output voltage is adjustable with an accuracy of less than 2% to meet DDR requirements. The regulator's voltage control loop is compensated using a type III compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. A typical Bootstrap circuit with an internal PMOS switch is used to provide the voltage necessary to properly enhance the high-side MOSFET gate. The 34716 is designed to address DDR memory power supplies. The integrated converter has the ability to supply up to 5.0 A out of channel 1 and sink and source up to 3.0 A of continuous current from channel 2, providing a full power supply solution for DDR applications.
BUCK CONVERTER
This block provides the main function of the 34716: DC to DC conversion from an un-regulated input voltage to a regulated output voltage used by the loads for reliable
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SD = 0 & STBY=x VTT<=VUVF2 VTT Under-voltage VDDQ=ON VTT=ON VREF=ON PG = 1 VTT=>=VUVR2 VTT Over-voltage VDDQ=ON VTT=ON VREF=ON PG = 1 TJ >= 170C Shutdown VDDQ = Discharge VTT = Discharge VREF = Discharge PG = 1 SD = 1 & STBY=1 VIN < 3.0 V Power Off VDDQ=OFF VTT=OFF VREF=OFF PG = 1 3.0 V<=VIN<=6.0 V SD = 1 & STBY=1 SD = 1 & STBY=0 Standby VDDQ=OFF VTT=OFF VREF=ON PG = 1 VDDQ<=VUVF1 VDDQ Under-voltage VDDQ=ON VTT2=ON VREF=ON PG = 1 VTT2<=VOVF2 VDDQ>= VUVR1 Normal FSW is programmed ILM1 is programmed VDDQ and VTT tss = 1 VDDQ = ON VTT = ON VREF=ON PG = 0 TIMEOUT Expired VTT Short-circuit VOUT1=ON VOUT2=OFF VREF=ON PG = 1 TIMEOUT=1 TIMEOUT Expired VDDQ Short-circuit VDDQ=OFF VTT=ON VREF=ON PG = 1 TIMEOUT=1 IOUT1>=ISHORT1 VDDQ<= VOVF1 VDDQ>=VOVR1
VTT>=VOVR2
VDDQ Over-voltage VDDQ=ON VOTT=ON VREF=ON PG = 1
TJ<=145C
TIMEOUT Expired Channel 2 Thermal Shutdown VDDQ=ON VTT=OFF VREF=ON PG = 1 TIMEOUT Expired Channel 2 Over-current VDDQ=ON VTT=OFF VREF=ON IOUT2>=ILIM2 For>=10 ms PG = 1 TIMEOUT=1
TJ<=145C TJ>=170C TIMEOUT Expired Channel 1 Thermal Shutdown VDDQ=OFF VTT=ON TIMEOUT VREF=ON Expired PG = 1 Channel 1 Over-current VDDQ=OFF VTT=ON VREF=ON IOUT1>=ILIM1 PG = 1 For>=10 ms TIMEOUT=1
IOUT2>=ISHORT2
Figure 8. Operation Modes Diagram
MODES OF OPERATION
The 34716 has three primary modes of operation: Normal Mode In normal mode, all functions and outputs are fully operational. To be in this mode, the VIN needs to be within its operating range, both Shutdown and Standby inputs are high, and no faults are present. This mode consumes the most amount of power. Standby Mode This mode is predominantly used in Desktop memory solutions where the DDR supply is desired to be ACPI compliant (Advanced Configuration and Power Interface). When this mode is activated by pulling the STBY pin low, VTT is put in High Z state, IOUT2 = 0 A while VDDQ and VREF stay active. This is the S3 state Suspend-To-Ram or Self Refresh mode and it is the lowest DRAM power state. In this mode, the DRAM will preserve the data. While in this mode, the 34716 consumes less power than in the normal mode, because the buck converter and most of the internal blocks are disabled.
Shutdown Mode In this mode, activated by pulling the SD pin low, the chip is in a shutdown state and the outputs are all disabled and discharged. This is the S4/S5 power state or Suspend-ToDisk state, where the DRAM will loose all of its data content (no power supplied to the DRAM). The reason to discharge the VTT and VREF lines is to ensure upon exiting, the shutdown mode that VTT and VREF are lower than VDDQ, otherwise VTT can remain floating high, and be higher than VDDQ upon powering up. In this mode, the 34716 consumes the least amount of power since almost all of the internal blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34716 checks the status of the SD and STBY pins. If the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. If the device is in a standby mode, only the VDDI internal supply voltage and the bias currents are established and no further activities will occur. Once the SD and STBY pins are released to enable the device, the internal VDDI POR signal is also released. The rest of the internal blocks will be enabled, and the buck converters switching frequency and the VDDQ
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Soft start values are determined by reading the FREQ and ILIM1 pins respectively. A soft start cycle is then initiated to ramp up the outputs. While channel 1 buck converter uses an internal reference, channel 2 converter error amplifier uses the voltage on the VREFOUT pin (VREF) as its reference voltage. VREF is equal to 1/2 VDDQ, where VDDQ is applied to the VREFIN pin. This way, the 34716 assures that VREF and VTT voltages track 1/2 VDDQ to meet DDR requirements. Soft start is used to prevent the output voltage from overshooting during startup. At initial startup, the output capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage across the inductor will be PVIN during the capacitor charge phase which will create a very sharp di/dt ramp. Allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load current that can result in an undesired voltage spike once the capacitor is fully charged. The soft start is active each time the IC goes out of standby or shutdown mode, power is recycled, or after a fault retry. To fully take advantage of soft starting, it is recommended not to enable the VTT output before introducing VDDQ on the VREFIN pin. If this happens after a soft start cycle expires and the VREFIN voltage has a high dv/dt, the output will naturally track it immediately and ramp up with a fast dv/dt itself and that will defeat the purpose of soft starting. For reliable operation, it is best to have the VDDQ voltage available before enabling the VTT output. After a successful start-up cycle where the device is enabled, no faults have occurred, and the output voltages have reached their regulation point, the 34716 pulls the power good output signal low after a 10 ms reset delay, to indicate to the host that the device is in normal operation.
avoid erroneous under-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage rises above the rising under-voltage threshold (VUVR), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. The condition is the same for both outputs. Output Over-current This block detects over-current in the Power MOSFETs of the buck converter. It is comprised of a sense MOSFET and a comparator for each channel. The sense MOSFET acts as a current detecting device by sampling a ratio of the load current. That sample is compared via the comparator with an internal reference to determine if the output is in over-current or not. If the peak current in the output inductor reaches the over-current limit (ILIM), the converter will start a cycle-bycycle operation to limit the current, and a 10 ms over-current limit timer (tLIM) starts. The converter will stay in this mode of operation until one of the following occurs: * The current is reduced back to the normal level before tLIM expires, and in this case normal operation is regained. * tLIM expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. At the end of a timeout period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. * The device reaches the thermal shutdown limit (TSDFET) and turns off the output. The power good (PG) output signal is pulled high. * The output current keeps increasing until it reaches the short-circuit current limit (ISHORT). See below for more details. Short-circuit Current Limit This block uses the same current detection mechanism as the over-current limit detection block. If the load current reaches the ISHORT value, the device reacts by shutting down the output immediately. This is necessary to prevent damage in case of a permanent short-circuit. Then, at the end of a timeout period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. Thermal Shutdown Each channel has its own thermal shutdown block. Thermal limit detection block monitors the temperature of the device and protects against excessive heating. If the temperature reaches the thermal shutdown threshold (TSDFET), the converter output switches off and the power good output signal indicates a fault by pulling high. The device will stay in this state until the temperature has decreased by the hysteresis value and then After a timeout period (TTIMEOUT) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. If successful normal operation is regained, the power good output signal is asserted low to indicate that.
PROTECTION FUNCTIONS
The 34716 monitors the application for several fault conditions to protect the load from overstress. The reaction of the IC to these faults ranges from turning off the outputs to just alerting the host that something is wrong. In the following paragraphs, each fault condition is explained: Output Over-voltage An over-voltage condition occurs once the output voltage goes higher than the rising over-voltage threshold (VOVR). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the outputs will stay active. To avoid erroneous over-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage falls below the falling over-voltage threshold (VOVF), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. The condition is the same for both outputs. Output Under-voltage An under-voltage condition occurs once the output voltage falls below the falling under-voltage threshold (VUVF). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the outputs will stay active. To
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
C14 0.1 F VDDI STBY 26 25 BOOT1 STBY VDDI C28 SW1 0.1 F PVIN1 SW1 1 2 2 3 3 GND 4 4 5 C27 0.1 F VOUT1
VIN FREQ x ILIM1 24 23 22 GND VIN VIN 21 20 19 FREQ ILIM1 NC 18 17 17 16 16 15 15 14 C11 0.1 F VOUT2 GND BOOT2 C15 SW2 0.1 F PVIN2 SW2
BOOT1 PVIN1 PVIN1 SW1 SW1 PGND1 VREFOUT PGND1 VREFIN COMP1 VOUT1 INV1
BOOT2 PVIN2 PVIN2
MC34716
SW2 SW2 PGND2 PGND2 COMP2 VOUT2 INV2
PG PG
6
7
8
9 10
11 12 13 INV2 SD COMP2 VREFOUT C12 0.1 F
INV1 COMP1 VREFIN C13 0.1 F
Compensation Network SW1
VO1 INV1 C18 15 pF R15 22 k C19 0.75 nF R14 560 R2 12.7 k
SD
Compensation Network SW2
VO2 INV2
COMP1
C20 0.910 nF
R1 20 k
COMP2
C21 20 pF R19 15 k C22 1.8 nF R18 300
C230 1.0 nF
R4 20 k
R2 17.4 k_nopop
Buck Converter 1
SW1 D3 PMEG2010EA _nopop L1 1.0 H Vo1_2 Vo1_1 VO1 SW2 D2 OMEG2010EA _nopop
Buck Converter 2
L1 1.5 H Vo2_2 Vo2_1 VO2 R30 4.7_nopop C7 C6 C8 C9 100 F 100 F 100 F 1 nF_nopop
R20 4.7_nopop C10 C24 C25 C26 100 F100 F 100 F 1 nF_nopop
Figure 9. 34716 Typical Application
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
I/O Signals
J2 PVIN1 VO1 GND 3 2 1 J3
VIN Capacitors
VIN C17 10 F C16 0.1 F
PGOOD LED
VIN R7 1k D1 LED LED
VMASTER
VM
R8 10 k R9 10 k
VMASTER
PVIN2 VO2 GND VM VIN GND
3 2 1 3 2 1
J4
Jumpers
VO1 VMASTER STBY_nopop LED 1 2 1 SD 2 CON10A 1 3 5 7 9 J1 2 4 6 8 10 VREFIN PG STBY SD VDDI R16 10 k
ILIM1, FREQ
VDDI R12 10 k_nopop FREQ R11 10 k
ILIM1 R22 10 k_nopop
PVIN1 Capacitors
PVIN1 PVIN2
PVIN2 Capacitors
C1 0.1 F
C2 1.0 F
C3 C4 C5 100 F 100 F 100 F
C30 0.1 F
C31 1.0 F
C32 C33 C29 1002 F 100 F 100 F
Trimpots nopop
VDDI ILIM1 R21 POT_50 k_nopop FREQ R6 POT_50 k_nopop
Figure 10. 34716 Typical Application
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS
CONFIGURING THE OUTPUT VOLTAGE:
Channel 1 of the 34716 is a general purpose DC-DC converter, the resistor divider to the -INV1 node is responsible for setting the output voltage, according to the following equation:
680 733 787 840
0.936 - 1.092 0.781 - 0.936 0.625 - 0.780 0.469 - 0.624 0.313 - 0.468 0.157 - 0.312 0.000 - 0.156
VOUT
R1 = V REF + 1 R2
893 947 1000
Where VREF is the internal VBG=0.7 V. Channel 2 is a DDR specific voltage power supply, and the output voltage is given by the equation:
Table 5. Frequency Selection Table
SOFT START ADJUSTMENT
Table 6 shows the voltage that should be applied to the ILIM1 terminal to get the desired desired sort start timing on channel 1 only.
SOFT START [MS] 3.2 1.6 0.8 0.4 VOLTAGE APPLIED TO ILIM
VTT =
V REFIN 2
Where VREFIN is equal to VDDQ.
1.19 - 1.49 V 1.50 - 1.81 V 1.82 - 2.13 V 2.14 - 2.50 V
SWITCHING FREQUENCY CONFIGURATION
The switching frequency will have a value of 1.0 MHz by connecting the FREQ terminal to the GND. If the smallest frequency value of 200 kHz is desired, then connect the FREQ terminal to VDDI. To program the switching frequency to another value, an external resistor divider will be connected to the FREQ terminal to achieve the voltages given by Table 5.
FREQUENCY 200 253 307 360 413 466 520 573 627 VOLTAGE APPLIED TO PIN FREQ 2.341 - 2.500 2.185 - 2.340 2.029 - 2.184 1.873 - 2.028 1.717 - 1.872 1.561 - 1.716 1.405 - 1.560 1.249 - 1.404 1.093 - 1.248
Table 6. Soft Start Configurations
RFQH CVDDI RIH RIL RFQL
VDDI FREQ ILIM1 GND
Figure 11. Resistor Divider for Frequency and Soft Start Adjustment
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
SELECTING INDUCTOR
Inductor calculation process is the same for both Channels. The equation is the following:
Inductor Current Rise Time:
dt _ I _ rise =
L = D'MAX T
D'MAX
T
(Vout + I out * ( Rds (on) _ ls + r _ w)) I out Vout Maximum Off Time Percentage = 1- Vin _ max
Switching Period Drain - to - Source Resistance of FET Winding Resistance of Inductor Output Current Ripple
T * I OUT I OUT _ step
The following formula will be helpful to find the maximum allowed ESR.
ESRmax =
Rds (on) _ ls
VOUT * Fsw * L VOUT (1 - D min)
r_w
I OUT = 0.4 * I OUT
If channel 1 will be serving as power supply for channel 2, it is necessary to locate the LC poles at different frequencies in order to ensure that the input impedance of the second converter is always higher than the output impedance of the first converter, and thus, ensure system stability. This can be achieved by selecting different values for L1 and L2 slightly higher than the calculated value.
The effects of the ESR is often neglected by the designers and may present a hidden danger to the ultimate supply stability. Poor quality capacitors have widely disparate ESR value, which can make the closed loop response inconsistent.
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate voltage for the high side MOSFET. This N-Channel MOSFET needs a voltage difference between its gate and source to be able to turn on. The high side MOSFET source is the SW node, so it is not at ground and it is floating and shifting in voltage. We cannot just apply a voltage directly to the gate of the high side that is referenced to ground. We need a voltage referenced to the SW node. This is why the bootstrap capacitor is needed. This capacitor charges during the high side off time. Since the low side will be on during that time, the SW node and the bottom of the bootstrap capacitor will be connected to ground, and the top of the capacitor will be connected to a voltage source. The capacitor will charge up to that voltage source (for example 5.0 V). Now when the low side MOSFET switches off and the high side MOSFET switches on, the SW nodes rise to VIN, and the voltage on the boot pin will be VCAP + VIN. The gate of the high side will have VCAP across it and it will be able to stay enhanced. A 0.1 f capacitor is a good value for this bootstrap element.
SELECTING THE OUTPUT FILTER CAPACITOR
For the output capacitor, the following considerations are most important and not the actual Farad value: the physical size, the ESR of the capacitor, and the voltage rating. Calculate the minimum output capacitor using the following formula:
Co =
I OUT * dt _ I _ rise TR _ V _ dip
Transient Response percentage: TR_% (Use a recommended value of 2 to 4% to assure a good transient response.) Maximum Transient Voltage: TR_V_dip = VOUT*TR_% Maximum Current Step:
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight regulation output voltages. A high DC gain is required to accomplish this, but with high gain comes the possibility of instability. The purpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the control-to-output transfer function that could jeopardized the stability of the power supply. The Type III compensation network used for 34716 is comprised of two poles (one integrator and one high frequency, to cancel the zero generated from the ESR of the output capacitor) and two zeros to cancel the two poles generated from the LC filter as shown in Figure 12.
Iout _ step =
(Vin _ min - Vout ) * D _ max Fsw * L
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS
SWx VOUTx
5. Equating pole 2 to 5 times the Crossover Frequency to achieve a faster response and a proper phase margin
Lx RSx CSx R1x COx
5 * F CROSS = F
INVx CXx COMPx
1 --------------------------------------P2 = CF CX 2 * R F ------------------CF + Cx
RFx CFx
R2x
CX =
CF 2 * R F C F FP 2 - 1
Figure 12. Type III compensation network 1. Choose a value for R1 (R2only applies to Channel 1) 2. Consider a Crossover frequency of one tenth of the switching frequency, set the Zero pole frequency to Fcross/10
TRACKING CONFIGURATIONS
The 34716 allows default Ratiometric tracking on channel 2 by connecting VDDQ to the VREFIN terminal. It has an internal resistor divider that allows an output of VDDQ/2.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful consideration. First, there are high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spikes they can create. To do this, an understanding of the major current carrying loops is important. See Figure 13. These loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. Also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. If sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction. Second, small signal components which connect to sensitive nodes need consideration. The critical small signal components are the ones associated with the feedback circuit. The high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. Other critical small signal components include the bypass capacitors for VIN, VREFIN, and VDDI. Locate the bypass capacitors as close to the pin as possible. The use of a multi-layer printed circuit board is recommended. Dedicate one layer, usually the layer under the top layer, as a ground plane. Make all critical component ground connections with vias to this layer. Make sure that the power grounds, PGND1 and PGND2 are connected directly to the ground plane and not routed through the thermal pad or analog ground. Dedicate another layer as a power plane and split this plane into local areas for common voltage nets. The IC input supply (VIN) should be connected with a dedicated trace to the input supply This will help prevent noise on the buck regulator's power inputs (PVIN1 and PVIN2) from injecting switching noise into the IC's analog circuitry.
FP 0
1 1 = FCROSS = 10 2 * R1C F 1 CF = 2 * R1 FPO
3. Knowing the LC frequency, the Frequency of Zero 1 and Zero 2 in the compensation network is equal to FLC
FLC =
FZ 1 =
1 = FZ 1 = FZ 2 2 LX COX
FZ 2 = 1 2 * R1C S
1 2 * RF C F
This gives the result
RF =
1 2 * C F FZ 1
CS =
1 2 * R1 FZ 2
4. Calculate RS by placing the first pole at the ESR zero frequency
1 = FP1 2 * Co X * ESR 1 1 RS = FP1 = 2 * FP1C S 2 * RS C S FESR =
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
In order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. It is
VIN1
recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm.
PVIN1 and 2 VIN2 and 3
Loop Curr ent HS ON HS Loop Curr ent HS ON
HS SW1 SD
SW1 and 2 SW2 and 3
Loop Current SD ON LS GND2 and 3 PGND1 and 2 BUCK CONVERTER 1 Loop Current LS ON
Buck Converter 1 and 2 BUCK CONVERTER
2 and 3
Figure 13. Current Loop
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX 26-PIN 98ASA10728D ISSUE 0
34716
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGING DIMENSIONS
EP SUFFIX 26-PIN 98ASA10728D ISSUE 0
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REVISION HISTORY
REVISION HISTORY
REVISION 1.0 2.0
DATE 2/2006 2/2007
DESCRIPTION OF CHANGES * * * * * * * * * * * * * * * * * * * * * * * * * * * Pre-release version
* Implemented Revision History page
Initial release Converted format from Market Assessment to Product Preview * Major updates to the data, form, and style Changed Feature fom 2% to 1%, relabeled to include soft start Change references for 45 m Integrated N-Channel Power MOSFETs to 50 m Removed Machine Model in Maximum Ratings Changed Input DC Supply Current(11) , Input DC Supply Current(11), and Input DC Supply Current(11) Added CH 1 High Side MOSFET Drain Voltage Range Changed Output Voltage Accuracy(12),(13),(14) Changed Soft Start Adjusting Reference Voltage Range and Short-circuit Current Limit Changed High Side N-CH Power MOSFET (M4) RDS(ON)(12) and Low Side N-CH Power MOSFET (M5) RDS(ON)(15) Changed M2 RDS(ON) and PVIN1 Pin Leakage Current Added CH 2 High Side MOSFET Drain Voltage Range Changed Output Voltage Accuracy(15),(16),(17) Changed Short-circuit Current Limit (Sinking and Sourcing) Changed High Side N-CH Power MOSFET (M6) RDS(ON)(15) and Low Side N-CH Power MOSFET (M7) RDS(ON)(15) Changed M3 RDS(ON) and PVIN2 Pin Leakage Current Changed VREFOUT Buffered Reference Voltage Accuracy(20), VREFOUT Buffered Reference Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over-current Limit Changed STBY Pin Internal Pull-up Resistor and SD Pin Internal Pull-up Resistor Changed Soft Start Duration (Normal Mode) Changed Over-current Limit Retry Timeout Period and Output Under-voltage/Over-voltage Filter Delay Timer Changed Oscillator Default Switching Frequency, PG Reset Delay, and Thermal Shutdown Retry Timeout Period (24) Changed definition for Channel 1 Soft Start ADJUStment input (ILIM1) Changed drawings in 34716 Typical Application Changed table for Soft Start Adjustment Removed PC34716EP/R2 from the ordering information and added MC34716EP/R2 Changed data sheet status to Advance Information Made changes to Switching Node (SW1, SW2) Pins, BOOT1, BOOT2 Pins (Referenced to SW1, SW2 Pins Respectively), Output Under-voltage Threshold, Output Over-voltage Threshold, Both channels of High Side N-CH Power MOSFET (M4) RDS(ON)(12), Both channels of Low Side N-CH Power MOSFET (M5) RDS(ON)(15), Charge Device Model Added Machine Model (MM), Both channels of SW2 Leakage Current (Standby and Shutdown modes), Both channels of (Error Amplifier DC Gain(15), Error Amplifier Unit Gain Bandwidth(15), Error Amplifier Slew Rate(15), Error Amplifier Input Offset(15)) Fixed drawing for Type III compensation network Added pin 27 to Figure 3 and the 34716 Pin Definitions Added the section Layout Guidelines
3.0
5/2007
4.0
12/2007
*
*
* * *
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC34716 Rev 4.0 12/2008

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