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24AA00/24LC00/24C00 128 Bit I2CTM Bus Serial EEPROM DEVICE SELECTION TABLE Device 24AA00 24LC00 24C00 VCC Range 1.8 - 6.0 2.5 - 6.0 4.5 - 5.5 Temp Range C,I C,I C,I,E NC 3 4 Vss PACKAGE TYPES 8-PIN PDIP/SOIC NC NC 1 8 VCC NC SCL SDA 24xx00 2 7 6 5 FEATURES * Low power CMOS technology - 500 A typical active current - 250 nA typical standby current * Organized as 16 bytes x 8 bits * 2-wire serial interface bus, I2CTM compatible * 100 kHz (1.8V) and 400 kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * 4 ms maximum byte write cycle time * 1,000,000 erase/write cycles guaranteed * ESD protection > 4 kV * Data retention > 200 years * 8L DIP, SOIC, TSSOP and 5L SOT-23 packages * Temperature ranges available: - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C 8-PIN TSSOP NC NC NC VSS 1 2 3 4 8 7 6 5 VCC NC SCL SDA 24xx00 5-PIN SOT-23 SCL VSS SDA 1 2 3 5 VCC 24xx00 DESCRIPTION The Microchip Technology Inc. 24AA00/24LC00/24C00 (24xx00*) is a 128-bit Electrically Erasable PROM memory organized as 16 x 8 with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts for the 24xx00 version, and every version maintains a maximum standby current of only 1 A and typical active current of only 500 A. This device was designed for where a small amount of EEPROM is needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24xx00 is available in 8-pin PDIP, 8-pin SOIC (150 mil), 8-pin TSSOP and the 5-pin SOT-23 packages. 4 NC BLOCK DIAGRAM HV GENERATOR I/O CONTROL LOGIC MEMORY CONTROL LOGIC XDEC EEPROM ARRAY SDA SCL YDEC VCC VSS SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation. *24xx00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices. 1998 Microchip Technology Inc. DS21178C-page 3-1 24AA00/24LC00/24C00 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* TABLE 1-1 Name VSS SDA SCL VCC PIN FUNCTION TABLE Function Ground Serial Data Serial Clock +1.8V to 6.0V (24AA00) +2.5V to 6.0V (24LC00) +4.5V to 5.5V (24C00) VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. NC No Internal Connection TABLE 1-2 DC CHARACTERISTICS All Parameters apply across the recom- Commercial (C): Tamb = 0C to +70C, VCC = 1.8V to 6.0V mended operating ranges unless other- Industrial (I): Tamb = -40C to +85C, VCC = 1.8V to 6.0V Automotive (E) Tamb = -40C to +125C, VCC = 4.5V to 5.5V wise noted Parameter SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS -10 -10 -- -- -- -- .05 VCC Min. 0.7 VCC 0.3 VCC -- .40 10 10 10 2 1 1 Max. Units V V V V A A pF mA mA A (Note) (Note) Vcc 2.5V (Note) IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V VIN = VCC or VSS VOUT = VCC or VSS VCC = 5.0V (Note) Tamb = 25C, f = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SDA = SCL = VCC Conditions Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING DATA TF THIGH TR SCL TSU:STA TLOW THD:DAT TSU:DAT TSU:STO SDA IN TSP THD:STA TBUF TAA SDA OUT DS21178C-page 3-2 1998 Microchip Technology Inc. 24AA00/24LC00/24C00 TABLE 1-3 AC CHARACTERISTICS Commercial (C): Industrial (I): Automotive (E): Symbol FCLK Min -- -- -- 4000 4000 600 4700 4700 1300 -- -- -- -- 4000 4000 600 4700 4700 600 0 250 250 100 4000 4000 600 -- -- -- 4700 4700 1300 20+0.1 CB -- -- 1M Tamb = 0C to +70C, VCC = 1.8V to 6.0V Tamb = -40C to +85C, VCC = 1.8V to 6.0V Tamb = -40C to +125C, VCC = 4.5V to 5.5V Max 100 100 400 -- -- -- -- -- -- 1000 1000 300 300 -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 3500 900 -- -- -- 250 50 4 -- Units kHz Conditions 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V (Note 1) 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V (Note 2) 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 6.0V (Note 1), CB 100 pF (Notes 1, 3) All Parameters apply across all recommended operating ranges unless otherwise noted Parameter Clock frequency Clock high time THIGH ns Clock low time TLOW ns SDA and SCL rise time (Note 1) SDA and SCL fall time START condition hold time TR ns TF THD:STA ns ns START condition setup time TSU:STA ns Data input hold time Data input setup time THD:DAT TSU:DAT ns ns STOP condition setup time TSU:STO ns Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance TAA ns TBUF ns TOF TSP TWC ns ns ms cycles 25C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's BBS or website. 1998 Microchip Technology Inc. DS21178C-page 3-3 24AA00/24LC00/24C00 2.0 2.1 PIN DESCRIPTIONS SDA Serial Data 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 4-1). This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 4.1 Bus not Busy (A) 2.2 SCL Serial Clock Both data and clock lines remain HIGH. This input is used to synchronize the data transfer from and to the device. 4.2 Start Data Transfer (B) 2.3 Noise Protection The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 0.1 Stop Data Transfer (C) 3.0 FUNCTIONAL DESCRIPTION A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. The 24xx00 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24xx00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.3 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited. DS21178C-page 3-4 1998 Microchip Technology Inc. 24AA00/24LC00/24C00 4.4 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24xx00 does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2). FIGURE 4-1: SCL (A) (B) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (C) (D) (C) (A) SDA START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 8 9 1 2 3 Data from transmitter Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. 1998 Microchip Technology Inc. DS21178C-page 3-5 24AA00/24LC00/24C00 5.0 DEVICE ADDRESSING 6.0 6.1 WRITE OPERATIONS Byte Write After generating a START condition, the bus master transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of operation is to be performed. The slave address for the 24xx00 consists of a 4-bit device code (1010) followed by three don't care bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 5-1). The 24xx00 monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Device Select Bits Don't Care Bits 0 X X X R/W ACK S 1 0 1 Slave Address Start Bit Acknowledge Bit Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24xx00. Only the lower four address bits are used by the device, and the upper four bits are don't cares. The 24xx00 will acknowledge the address byte and the master device will then transmit the data word to be written into the addressed memory location. The 24xx00 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24xx00 will not generate acknowledge signals (Figure 7-2). After a byte write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abort and no data will be written. The 24xx00 employs a VCC threshold detector circuit which disables the internal erase/ write logic if the VCC is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00) at nominal conditions. DS21178C-page 3-6 1998 Microchip Technology Inc. 24AA00/24LC00/24C00 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? YES Next Operation NO FIGURE 7-2: BUS ACTIVITY MASTER SDA LINE BYTE WRITE S T A R T S 1 0 1 CONTROL BYTE WORD ADDRESS DATA S T O P P A C K A C K 0 X X X 0 A C K X X X X BUS ACTIVITY X = Don't Care Bit 1998 Microchip Technology Inc. DS21178C-page 3-7 24AA00/24LC00/24C00 8.0 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. device as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24xx00 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. 8.1 Current Address Read The 24xx00 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the device issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 8-1). 8.3 Sequential Read 8.2 Random Read Sequential reads are initiated in the same way as a random read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the device to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24xx00 contains an internal address pointer which is incremented by one at the completion of each read operation. This address pointer allows the entire memory contents to be serially read during one operation. Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the FIGURE 8-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T CONTROL BYTE DATA S T O P S 1 0 1 0 XXX1 P A C K N O A C K X = Don't Care Bit FIGURE 8-2: RANDOM READ S T A R T CONTROL BYTE WORD ADDRESS (n) XXXX BUS ACTIVITY MASTER S T A R T CONTROL BYTE DATA (n) S T O P S 10 10XXX0 S 10 10XXX1 P A C K N O A C K SDA LINE BUS ACTIVITY X = Don't Care Bit A C K A C K FIGURE 8-3: BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P P A C K A C K A C K A C K N O A C K DS21178C-page 3-8 1998 Microchip Technology Inc. 24AA00/24LC00/24C00 NOTES: 1998 Microchip Technology Inc. DS21178C-page 3-9 24AA00/24LC00/24C00 24XX00 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24xx00 -- /P Package: P SN ST OT = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body) TSSOP, 8-lead SOT-23, 5-lead Temperature Range: Blank = 0C to +70C I = -40C to +85C E = -40C to +125C 24AA00 24AA00T 24LC00 24LC00T 24C00 24C00T 128 bit 1.8V I2C Serial EEPROM 128 bit 1.8V I2C Serial EEPROM (Tape and Reel) 128 bit 2.5V I2C Serial EEPROM 128 bit 2.5V I2C Serial EEPROM (Tape and Reel) 128 bit 5.0V I2C Serial EEPROM 128 bit 5.0V I2C Serial EEPROM (Tape and Reel) Device: Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) DS21178C-page 3-10 1998 Microchip Technology Inc. Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. * * * If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. 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Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02 2002 Microchip Technology Inc. |
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