View PENTIUMPROCESSORWITHMMX_364183.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E
n n n n
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
166 MHz 160 200 MHz 182
iCOMP(R)
Maximum Operating Frequency iCOMP(R) Index 2.0 Rating
233 MHz 203
NOTE: Contact Intel Corporation for more information about
Index 2.0 ratings.
Support for MMXTM Technology Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit Processor with 64-Bit Data Bus Superscalar Architecture Enhanced Pipelines Two Pipelined Integer Units Capable of Two Instructions per Clock Pipelined MMX Unit Pipelined Floating-Point Unit Separate Code and Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions
n n n n n n n n n
Enhanced CMOS Silicon Technology 4-Mbyte Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Dual Processing Configuration Internal Error Detection Features Multi-Processor Support Multiprocessor Instructions Support for Second Level Cache On-Chip Local APIC Controller MP Interrupt Management 8259 Compatible Power Management Features System Management Mode Clock Control Fractional Bus Operation 233 MHz Core/66 MHz Bus 200 MHz Core/66 MHz Bus 166 MHz Core/66 MHz Bus
n n
The Pentium(R) processor with MMXTM technology extends the Pentium processor family, providing performance needed for mainstream desktop applications as well as for workstations. The Pentium processor with MMX technology is compatible with the entire installed base of applications for MS-DOS*, Windows*, OS/2* and UNIX*. The Pentium processor with MMX technology is the first microprocessor to support Intel MMX technology. Furthermore, the Pentium processor with MMX technology superscalar architecture can execute two instructions per clock cycle. Enhanced branch prediction and separate caches also increase performance. The pipelined floating-point unit delivers workstation level performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The Pentium processor with MMX technology has 4.5 million transistors and is built on Intel's enhanced CMOS silicon technology. The Pentium processor with MMX technology may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are available on request.
June 1997
Order Number: 243185.004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium(R) Processor with MMXTM technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel's website at http\\:www.intel.com *Third-party brands and names are the property of their respective owners.
COPYRIGHT (c) INTEL CORPORATION, 1997
E
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
CONTENTS
PAGE PAGE 2.2. Design Notes................................................13 2.3. Quick Pin Reference....................................13 2.4. Pin Reference Tables...................................24 2.5. Pin Grouping According to Function............27 3.0. ELECTRICAL SPECIFICATIONS...................28 3.1. Electrical Characteristics and Differences between the Pentium(R) Processor with MMXTM Technology and the Pentium Processor 133/150/166/200.........................28 3.1.1. POWER SUPPLIES..............................28 3.1.2. CONNECTION SPECIFICATIONS ......28 3.1.3. BUFFER MODELS................................30 3.2. Absolute Maximum Ratings..........................30 3.3. DC Specifications.........................................30 3.4. AC Specifications.........................................34 4.0. MECHANICAL SPECIFICATIONS .................43 5.0. THERMAL SPECIFICATIONS........................46 5.1. Measuring Thermal Values..........................46 5.1.1. THERMAL EQUATIONS AND DATA...46
1.0. MICROPROCESSOR ARCHITECTURE OVERVIEW ....................................................... 3 1.1. Pentium(R) Processor Family Architecture....... 5 1.2. Pentium(R) Processor with MMXTM Technology..................................................... 7 1.2.1. FULL SUPPORT FOR INTEL MMXTM TECHNOLOGY ...................................... 7 1.2.2. DOUBLE CODE AND DATA CHACHES TO 16K EACH ........................................ 7 1.2.3. IMPROVED BRANCH PREDICTION..... 7 1.2.4. ENHANCED PIPELINE .......................... 7 1.2.5. DEEPER WRITE BUFFERS................... 8 Processor with MMXTM 1.3. Mobile Technology..................................................... 8 2.0. PINOUT.............................................................. 9 2.1. Pinout and Pin Descriptions........................... 9 2.1.1. PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY PINOUT .......... 9 2.1.2. PIN CROSS-REFERENCE TABLE FOR PENTIUM(R) PROCESSOR WITH MMXTM........................................ 11 Pentium(R)
3
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
1.0.
MICROPROCESSOR ARCHITECTURE OVERVIEW
* * * * * * * * * * * * * *
Improved Instruction Execution Time Separate Code and Data Caches
E
The Pentium(R) processor with MMXTM technology extends the Intel Pentium family of microprocessors. It is binary compatible with the 8086/88, 80286, Intel386TM DX, Intel386 SX, Intel486TM DX, Intel486 SX, Intel486 DX2 and Pentium processors 60/66/75/90/100/120/133/150/166/200. The Pentium processor family currently includes the following products.
Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Bus Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions Dual processing support On-chip local APIC device
*
Pentium processor with MMX technology: - - - Pentium processor with MMX technology at 233 MHz, iCOMP(R) Index 2.0 rating = 203 Pentium processor with MMX technology at 200 MHz, iCOMP Index 2.0 rating = 182 Pentium processor with MMX technology at 166 MHz, iCOMP Index 2.0 rating = 160
*
Pentium processor 133/150/166/200. The name "Pentium processor 133/150/166/200" will be used in this document to refer to the Pentium processor with 133, 150, 166 and 200 MHz versions of the Pentium processor: - - - - - - - - Pentium processor at 200 MHz, iCOMP Index 2.0 rating = 142 Pentium processor at 166 MHz, iCOMP Index 2.0 rating = 127 Pentium processor at 150 MHz, iCOMP Index 2.0 rating = 114 Pentium processor at 133 MHz, iCOMP Index 2.0 rating = 111 Pentium processor at 120 MHz, iCOMP Index 2.0 rating = 100 Pentium processor at 100 MHz, iCOMP Index 2.0 rating = 90 Pentium processor at 90 MHz, iCOMP Index 2.0 rating = 81 Pentium processor at 75 MHz, iCOMP Index 2.0 rating = 67
In addition to the features listed above, the Pentium processor with MMX technology offers the following enhancements over Pentium processor 133/150/ 166/200:
* * * * *
Support for Intel MMX technology Doubled code and data cache sizes to 16 KB each Improved branch prediction Enhanced pipeline Deeper write buffers
The following features are supported by the Pentium processor 133/150/166/200, but these features are not supported by the Pentium processor with MMX technology:
* * *
Functional redundancy check and Lock Step operation. Support for Intel 82498/82493 and 82497/82492 cache chipset products Split line accesses to the code cache
The Pentium processor family supports the features of previous Intel Architecture processors, and provides significant enhancements and additions including the following:
* * * 4
Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit
E
1.1.
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are multi-ported to support snooping. Individual pages can be configured as cacheable or noncacheable by software or hardware. The caches can be enabled or disabled by software or hardware. The Pentium processors have increased the data bus to 64 bits to improve the data transfer rate. Burst read and burst write back cycles are supported by the Pentium processors. In addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. The Pentium processors' Memory Management Unit contains optional extensions to the architecture which allow 4Kbyte and 4-Mbyte page sizes. The Pentium processors have added significant data integrity and error detection capability. Data parity checking is still supported on a byte-by-byte basis. Address parity checking and internal parity checking features have been added along with a new exception, the machine check exception. As more and more functions are integrated on chip, the complexity of board level testing is increased. To address this, the Pentium processors have increased test and debug capability. The Pentium processors implement IEEE Boundary Scan (Standard 1149.1). In addition, the Pentium processors have specified 4 breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. Execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. System Management Mode (SMM) has been implemented along with some extensions to the SMM architecture. Enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. Figure 1 shows a block diagram of the Pentium processor with MMX technology as a representative of the Pentium processor family. The block diagram shows the two instruction pipelines, the "u" pipe and the "v" pipe. The u-pipe can execute all integer and floating-point instructions. The v-pipe can execute simple integer instructions and the FXCH floating-point instructions.
For a more detailed description of the Pentium processor family products, please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428).
Pentium(R) Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The on-chip memory management unit (MMU) is completely compatible with the Intel386 family and Intel486 family of processors. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the BTB so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 processor. Faster algorithms provide up to 10X speed-up for common operations including add, multiply and load. Pentium processors include separate code and data caches are integrated on-chip to meet performance goals. Each cache has a 32-byte line size. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be write back or write through on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an
5
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Control ROM
V-Pipeline Connection U-Pipeline Connection
Control
DP Logic
TLB Branch Prefetch Target Address Buffer
Code Cache 16 KBytes
128
Instruction Pointer
Branch Verif. & Target Addr
64-Bit Data Bus
Prefetch Buffers Instruction Decode
Control Unit Floating Point Unit Control Register File
Add
32-Bit Address Bus
Bus Unit
Page Unit Generate
(U Pipeline) Address
Address Generate
(V Pipeline)
Control Integer Register File ALU
MMX Unit
TM
Divide
80
ALU (U Pipeline)
64 32
(V Pipeline)
Multiply
80
Barrel Shifter
64-Bit Data Bus Data APIC
32-Bit Addr. Bus
32 32 32
Control
TLB
Data Cache 16 KBytes
32 32 32
Figure 1. Pentium(R) Processor with MMXTM Technology Block Diagram The separate code and data caches are shown. The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the Pentium processor. Instructions are fetched from the code cache or from the external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache. The decode unit decodes the prefetched instructions so the Pentium processors can execute the 6 instruction. The control ROM contains the microcode which controls the sequence of operations that must be performed to implement the Pentium processor architecture. The control ROM unit has direct control over both pipelines. The Pentium processors contain a pipelined floatingpoint unit that provides a significant floating-point performance advantage over previous generations of processors. Symmetric dual processing in a system is supported with two Pentium processors. The two processors appear to the system as a single Pentium processor. Operating systems with dual processing support properly schedule computing tasks between the two processors. This scheduling of tasks is transparent to software applications and the end-user. Logic built into the processors support a "glueless" interface for
easy system design. Through a private bus, the two Pentium processors arbitrate for the external bus and maintain cache coherency. Dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. In this document, in order to distinguish between two Pentium processors in dual processing mode, one processor will be designated as the "Primary" processor and the other as the "Dual" processor. The Pentium processors are produced on the enhanced 0.35 m CMOS process which allows high device density and lower power dissipation. In addition to the SMM features described above, the Pentium processor supports clock control. When the clock to the Pentium processor is stopped, power dissipation is virtually eliminated. The combination of these improvements makes the Pentium processor a good choice for energy-efficient desktop designs. The Pentium processor supports fractional bus operation. This allows the internal processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. The Pentium processor contains an on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple I/O subsystem support, 8259A compatibility, and interprocessor interrupt support. The architectural features introduced in this chapter are more fully described in the Pentium(R) Processor Family Developer's Manual (Order Number 241428).
E
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
envelope of the original Pentium processor while providing a significant performance increase. In addition to the architecture described in the previous section for the Pentium processor family, the Pentium processor with MMX technology has several additional micro-architectural enhancements, compared to the Pentium processor 133/150/166/200, which are described below: 1.2.1. FULL SUPPORT FOR INTEL MMXTM TECHNOLOGY
MMX technology is based on the Single Instruction Multiple Data (SIMD) technique which enables increased performance on a wide variety of multimedia and communications applications. Fiftyseven new instructions and four new 64-bit data types are supported in the Pentium processor with MMX technology. All existing operating system and application software are fully-compatible with the Pentium processor with MMX technology. 1.2.2. DOUBLE CODE AND DATA CACHES TO 16K EACH
1.2.
Pentium(R) Processor with MMXTM Technology
On-chip level-1 data and code cache sizes have been doubled to 16 KB each and are 4-way set associative on the Pentium processor with MMX technology. Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently-used instructions and data. The instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. The data cache supports a writeback (or alternatively, write-through, on a line by line basis) policy for memory updates. 1.2.3. IMPROVED BRANCH PREDICTION
The Pentium processor with MMX technology is a significant addition to the Pentium processor family. Available at 166, 200 and 233 MHz, it is the first microprocessor to support Intel's MMX technology. The Pentium processor with MMX technology is both software and pin compatible with previous members of the Pentium processor family. It contains 4.5 million transistors and is manufactured on lntel's enhanced 0.35 micron CMOS process which allows voltage reduction technology for low power and high density. This enables the Pentium processor with MMX technology to remain within the thermal
Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved on the Pentium processor with MMX technology to increase its accuracy. Further, the Pentium processor with MMX technology has four prefetch buffers that can hold up to four successive code streams. 1.2.4. ENHANCED PIPELINE
An additional pipeline stage has been added and the pipeline has been enhanced to improve performance. 7
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
The integration of the MMX pipeline with the integer pipeline is very similar to that of the floating-point pipeline. Under some circumstances, two MMX instructions or one integer and one MMX instruction can be paired and issued in one clock cycle to increase throughput. The enhanced pipeline is described in more detail in the Pentium(R) Processor Family Developer's Manual (Order Number 241428). 1.2.5. DEEPER WRITE BUFFERS
1.3.
Mobile Pentium (R) Processor with MMXTM Technology
E
Currently, Intel's Mobile Pentium processor with MMX technology family consists of three products. Detailed information on Mobile Pentium processors with MMX technology based on the enhanced CMOS process technology is available in the datasheet Mobile Pentium(R) Processor with MMXTM Technology (Order Number 243292). Please reference the datasheet for correct pinout, mechanical, thermal and electrical specifications.
A pool of four write buffers is now shared between the dual pipelines to improve memory write performance.
8
E
2.0. 2.1.
2.1.1.
AN AM AL AK AJ AH AG AF AE VCC3 AD AC AB VSS AA VCC3 Z Y X W VCC3 V U VCC3 T S VCC3 R Q P N M VSS L K VSS J VCC3 H G VCC3 F E VCC3 D C B A D9 D11 NC DP0 D4 D6 VSS D2 VCC3 VSS NC VSS VCC3 VCC3 VSS VSS A22 VSS A28 A3 VSS A30 NC
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
PINOUT Pinout and Pin Descriptions
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY PINOUT
AN A6 A4 A7 A29 A25 A26 A24 A21 A23 INTR NMI A27 A31 A5 A8 A11 A9 A10 VCC3 VSS A12 A13 VCC3 VCC3 VCC3 VSS A16 A15 A17 A18 A19 VCC3 VCC2 VCC2 VCC2 VSS VCC2 VCC2 VCC2 FLUSH# INC VSS W/R# INC INC AM AL AK AJ ADS# HLDA BREQ AH LOCK# VSS AG PCD SMIACT# VCC2 PCHK# VSS
APCHK# PBREQ# VCC2
VSS A14
VSS
VSS A20
VSS NC
VSS
VSS
VSS
VSS
EADS# ADSC# PWT
VCC2 DET#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
RESET CLK
BE7#
BE5#
BE3#
BE1#
D/C#
AP
AF AE
D/P#
PBGNT# VSS PRDY PHITM# VCC2 HOLD VSS
AD AC AB AA Z Y X W
R/S#
SMI#
IGNNE# INIT PEN#
WB/WT# PHIT# VCC2 BOFF# VSS
VSS
VCC3 FRCMC#1 BF0 VSS BF1 NC
NA# BRDYC# VCC2 BRDY# VSS
KEN# EWBE# VCC2
VSS STPCLK# VSS VCC3
Top Side View
AHOLD
INV
VSS
V U
CACHE# VCC2
VSS
VCC3 NC NC NC
MI/O# BP3 BP2
VSS
VCC2
T S R Q P N M L
PM1BP1 VSS
FERR# PM0BP0 VCC2
VCC3 CPUTYP TRST# VSS VCC3 TDI TMS TDO TCK
IERR# DP7 D62 D60 D59 D58 D56 D53 DP5 D7 D42 D12 DP1 D17 D16 D20 D22 VCC3 D21 D19 D24 VSS D23 D26 D25 VSS D28 D27 D30 D29 DP3 D31 VSS D33 D32 VSS VSS D35 D34 VSS D37 D36 D39 D38 D40 DP4 VSS D46 D44 D45 D43 INC D49 D48 D47 D51 D55 D57 D61 D63
VSS
VCC2
VSS
VCC2
PICD1 VCC3 D0 PICD0
VSS
VCC2
K J H G F
PICCLK D1 D5 D3
VSS
VCC2
DP6 D52 D50 INC INC D54
E D C B A
D8 D10 D13 D15 D18 D14
DP2 VSS
VSS
VSS
VSS
VSS D41
VCC3
VCC3
VCC3
VCC3 VCC3
VCC2 VCC2
VCC2
VCC2
VCC2
VCC2
NOTE: 1. The FRCMC# pin is not defined for Pentium(R) processor with MMXTM technology. Pin Y35 should be left as a "NC" or tied to VCC3 via an external pull-up resistor.
PP0008a
Figure 2.
Pentium(R)
Processor with MMXTM Technology SPGA and PPGA Package Pinout (Top Side View)
9
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W VCC2 EWBE# KEN# V U T S VCC2 R Q P N M L VCC2 K J H G VCC2 F DP6 E D54 D D50 C B A 1 2 INC INC INC 3 4 D47 D43 D48 D45 D44 DP4 D40 D38 D39 D36 D37 D34 D35 D32 VSS D33 DP3 D31 VSS VSS D29 D30 D27 VSS D28 D25 D26 D23 D24 VSS D19 DP1 D21 D20 VCC3 D22 D17 D16 D12 D52 D49 D46 D42 D7 D51 DP5 VCC2 VSS D55 VSS D57 D56 D53 VCC2 VSS D61 D59 D58 VCC2 CACHE# INV VSS MI/O# BP3 VSS AHOLD NC INC 2 3 INC 4 5 INC 6 7 8 9 10 11 12 13 14 15 16 VCC2 VCC2 17 18 VCC2 19 20 21 22 23 24 25 26 VCC2 VCC3 VCC3 VCC3
27 28 29 30 31 32 33 34 35 36 37 VCC3 VCC3 A10 A8 A7 A5 A31 A26 A27 A21 A23 INTR NMI A24 A29 A25 A22 A6 A4 A3 A28 NC A30
E
AN VSS AM AL VSS AK AJ VSS AH AG VCC3 VSS D/P# AE VCC3 AD AC VCC3 AB AA Z AF VSS R/S# VSS VSS Y X W NC VCC3 VSS V U
FLUSH# VCC2 VCC2 VSS VSS
ADSC# EADS# W/R#
VCC2 DET#
VSS
VSS
VSS
VSS NC
VSS A20
VSS A18 A19
VSS A16 A17
VSS A14 A15
VSS A12 A13
VSS A11 A9
PWT HITM# BUSCHK# BE0# D/C# HIT# A20M#
BE2#
BE4#
BE6#
SCYC CLK
AP
BE1#
BE3#
BE5#
BE7#
RESET
BREQ HLDA VSS
ADS#
LOCK#
VCC2 SMIACT# PCD VSS PCHK#
VCC2 PBREQ#APCHK# VSS PBGNT#
VCC2 PHITM# PRDY VSS VCC2 HOLD
SMI#
PHIT# WB/WT# BOFF#
INIT IGNNE# VCC3 PEN#
VSS
VCC2 BRDYC# NA# VSS BRDY#
1 BF0 FRCMC# VCC3
BF1
Pin Side View
STPCLK# VSS VCC3 VSS VCC3 T VCC3 VSS VCC3 Q P S R
VCC3 NC NC NC
VSS
BP2
VSS
PM1BP1
VCC2 PM0BP0 FERR# VSS IERR# D63 D62 D60 DP7
TRST# CPUTYP
TMS TDO TCK VCC3 TDI
VSS VCC3 VSS L K N M
PICD1 VCC3 D0 VSS
J PICD0 D2 VCC3 H PICCLK VSS D3 D5 D6 D8 D14 D13 D18 D15 D10 D1 D4 VCC3 DP0 C DP2 D9 B VSS D41 5 6 VSS VSS VSS VCC2 VSS VCC3 VSS VSS D11 A VCC2 7 8 VCC2 9 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 E D VCC3 G F
NOTE: 1. The FRCMC# pin is not defined for Pentium(R) processor with MMXTM technology. Pin Y35 should be left as a "NC" or tied to VCC3 via an external pull-up resistor.
PP0009a
Figure 3.
Pentium(R)
Processor with MMXTM Technology SPGA and PPGA Package Pinout (Pin Side View)
10
E
2.1.2. A3 A4 A5 A6 A7 A8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
PIN CROSS-REFERENCE TABLE FOR PENTIUM(R) PROCESSOR WITH MMXTM Table 1. Pin Cross-Reference by Pin Name (xPGA Package) Address AL35 AM34 AK32 AN33 AL33 AM32 A9 A10 A11 A12 A13 A14 AK30 AN31 AL31 AL29 AK28 AL27 A15 A16 A17 A18 A19 A20 AK26 AL25 AK24 AL23 AK22 AL21 A21 A22 A23 A24 A25 A26 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33
Data K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03
11
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
AK06 AL05 AJ03 AB04 P04 AA35 AA33 PRDY PWT R/S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 U05 W05 AH04 T04 Y05 AC33 AG05 AF04 Z34 Q03 R04
Table 1. Pin Cross-Reference by Pin Name (xPGA Package) (Cont'd) Control A20M# ADS# ADSC# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# BRDYC# AK08 AJ05 AM02 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04 Y03 BREQ BUSCHK# CACHE# CPUTYP D/C# D/P# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# FRCMC#1 AJ01 AL07 U03 Q35 AK04 AE35 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 AN07 Y35 HIT# HITM# HLDA HOLD IERR# IGNNE# INIT
INTR/LINT0 AD34 INV KEN# LOCK# M/IO# NA# NMI/LINT1 PCD PCHK# PEN# PM0/BP0 PM1/BP1
VCC2DET# AL01 W/R# WB/WT# AM06 AA05
APIC PICCLK PICD0 [DPEN#] PICD1 [APICEN] L35 H34 (2) J33 CLK [BF0] [BF1]
Clock Control AK18 (2) Y33 X34 V34
Dual Processor Private Interface PBGNT# PBREQ# PHIT# PHITM# AD04 AE03 AA03 AC03
STPCLK#
VCC2 A17 A15 A13 A11 A09 A07 G01 J01 L01 N01 Q01 S01 U01 W01 Y01 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
12
E
A19 A21 A23 A25 A27 A29 E37 G37 J37 L37 L33 N37 B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 H02 H36 K02 K36 M02 M36
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 1. Pin Cross-Reference by Pin Name (xPGA Package) (Cont'd) VCC3 Q37 S37 T34 U33 U37 W37 Y37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21
VSS P02 P36 R02 R36 T02 T36 U35 V02 V36 X02 X36 Z02 Z36 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37
NC A37 R34 S33 S35 W33 W35 AL19 AN35 --
INC A03 B02 C01 AN01 AN03 AN05
NOTES: 1. The FRCMC# pin is not defined for the Pentium(R) processor with MMXTM technology. This pin should be left as a "NC" or tied to VCC3 via an external pull-up resistor on the Pentium processor with MMX technology. 2. PICCLK and CLK are 3.3V-tolerant-only on the Pentium processor with MMX technology. Please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428) for the CLK and PICCLK signal quality specification.
2.2.
Design Notes
2.3.
Quick Pin Reference
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to GND. No Connect (NC) pins must remain unconnected. Connection of NC or INC pins may result in component failure or incompatibility with processor steppings.
This section gives a brief functional description of each of the pins. For a detailed description, see the Hardware Interface chapter in the Pentium(R) Processor Family Developer's Manual (Order Number 241428). NOTE All input pins must meet their AC/DC specifications to guarantee proper functional behavior.
13
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. When a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. Square brackets around a signal name indicate that the signal is defined only at RESET.
The following pins become I/O pins when two Pentium processors with MMX technology are operating in a dual processing environment: ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M/IO#, D/C#, W/R#, SCYC, BE#4
E
Table 2. Quick Pin Reference Symbol A20M# Type I Name and Function When the address bit 20 mask pin is asserted, the Pentium(R) processor with MMXTM technology emulates the address wraparound at 1 Mbyte which occurs on the 8086 by masking physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus. The effect of A20M# is undefined in protected mode. A20M# must be asserted only when the processor is in real mode. A20M# is internally masked by the Pentium processor with MMX technology when configured as a Dual processor. A31-A3 I/O As outputs, the address lines of the processor along with the byte enables define the physical area of memory or I/O accessed. The external system drives the inquire address to the processor on A31-A5. The address strobe indicates that a new valid bus cycle is currently being driven by the Pentium processor with MMX technology. The address strobe (copy) is functionally identical to ADS#. In response to the assertion of address hold, the Pentium processor with MMX technology will stop driving the address lines (A31-A3) and AP in the next clock. The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. Address parity is driven by the Pentium processor with MMX technology with even parity information on all Pentium processor with MMX technology generated cycles in the same clock that the address is driven. Even parity must be driven back to the Pentium processor with MMX technology during inquire cycles on this pin in the same clock as EADS# to ensure that correct parity check status is indicated by the Pentium processor with MMX technology. The address parity check status pin is asserted two clocks after EADS# is sampled active if the Pentium processor with MMX technology has detected a parity error on the address bus during inquire cycles. APCHK# will remain active for one clock each time a parity error is detected (including during dual processing private snooping). Advanced Programmable Interrupt Controller Enable enables or disables the on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the APIC is enabled. APICEN shares a pin with the PICD1 signal.
ADS# ADSC# AHOLD
O O I
AP
I/O
APCHK#
O
[APICEN] PICD1
I
14
E
Symbol BE7#-BE4# BE3#-BE0# Type O I/O BF[1:0] I BOFF# I
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 2. Quick Pin Reference (Cont'd) Name and Function The byte enable pins are used to determine which bytes must be written to external memory or which bytes were requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-3). Additionally, the lower 4-byte enables (BE3#-BE0#) are used on the Pentium processor with MMX technology as APIC ID inputs and are sampled at RESET. In dual processing mode, BE4# is used as an input during Flush cycles. The bus frequency pins determine the bus-to-core frequency ratio. BF[1:0] are sampled at RESET, and cannot be changed until another non-warm (1 ms) assertion of RESET. Additionally, BF[1:0] must not change values while RESET is active. See Table 3 for Bus Frequency Selections. The backoff input is used to abort all outstanding bus cycles that have not yet completed. In response to BOFF#, the Pentium processor with MMX technology will float all pins normally floated during bus hold in the next clock. The processor remains in bus hold until BOFF# is negated, at which time the Pentium processor with MMX technology restarts the aborted bus cycle(s) in their entirety. The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0. These pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. BP1 and BP0 are multiplexed with the performance monitoring pins (PM1 and PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. BRDY# I The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the Pentium processor with MMX technology data in response to a write request. This signal is sampled in the T2, T12 and T2P bus states. The burst ready (copy) is functionally identical to BRDY#. The bus request output indicates to the external system that the Pentium processor with MMX technology has internally generated a bus request. This signal is always driven whether or not the Pentium processor with MMX technology is driving its bus.
BP[3:2] PM/BP[1:0]
O
BRDYC# BREQ
I O
15
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Table 2. Quick Pin Reference (Cont'd) Symbol BUSCHK# Type I Name and Function The bus check input allows the system to signal an unsuccessful completion of a bus cycle. If this pin is sampled active, the Pentium processor with MMX technology will latch the address and control signals in the machine check registers. If, in addition, the MCE bit in CR4 is set, the Pentium processor with MMX technology will vector to the machine check exception. NOTE: To assure that BUSCHK# will always be recognized, STPCLK# must be deasserted any time BUSCHK# is asserted by the system, before the system allows another external bus cycle. If BUSCHK# is asserted by the system for a snoop cycle while STPCLK# remains asserted, usually (if MCE=1) the processor will vector to the exception after STPCLK# is deasserted. But if another snoop to the same line occurs during STPCLK# assertion, the processor can lose the BUSCHK# request. CACHE# O For Pentium processor with MMX technology-initiated cycles thecache pin indicates internal cacheability of the cycle (if a read), and indicates a burst write back cycle (if a write). If this pin is driven inactive during a read cycle, the Pentium processor with MMX technology will not cache the returned data, regardless of the state of the KEN# pin. This pin is also used to determine the cycle length (number of transfers in the cycle). The clock input provides the fundamental timing for the Pentium processor with MMX technology. Its frequency is the operating frequency of the Pentium processor with MMX technology external bus, and requires TTL levels. All external timing parameters except TDI, TDO, TMS, TRST#, and PICD0-1 are specified with respect to the rising edge of CLK. This pin is 3.3V-tolerant-only on the Pentium processor with MMX technology. Please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428) for the CLK and PICCLK signal quality specification. NOTE: It is recommended that CLK begin toggling within 150 ms after V reaches its CC proper operating level. This recommendation is to ensure long-term reliability of the device. CPUTYP I CPU type distinguishes the Primary processor from the Dual processor. In a single processor environment, or when the Pentium processor with MMX technology is acting as the Primary processor in a dual processing system, CPUTYP should be strapped to VSS. The Dual processor should have CPUTYP strapped to VCC3. The data/code output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. D/C# distinguishes between data and code or special cycles.
CLK
I
D/C#
O
16
E
Symbol D/P# Type O D63-D0 I/O DP7-DP0 I/O
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 2. Quick Pin Reference (Cont'd) Name and Function The dual/primary processor indication. The Primary processor drives this pin low when it is driving the bus, otherwise it drives this pin high. D/P# is always driven. D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin is defined only on the Primary processor. Dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. Within these restrictions, two processors of different steppings may operate together in a system. These are the 64 data lines for the processor. Lines D7-D0 define the least significant byte of the data bus; lines D63-D56 define the most significant byte of the data bus. When the CPU is driving the data lines, they are driven during the T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data bus when BRDY# is returned. These are the data parity pins for the processor. There is one for each byte of the data bus. They are driven by the Pentium processor with MMX technology with even parity information on writes in the same clock as write data. Even parity information must be driven back to the Pentium processor with MMX technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor with MMX technology. DP7 applies to D63-56, DP0 applies to D7-0. Dual processing enable is an output of the Dual processor and an input of the Primary processor. The Dual processor drives DPEN# low to the Primary processor at RESET to indicate that the Primary processor should enable dual processor mode. DPEN# may be sampled by the system at the falling edge of RESET to determine if the dual-processor socket is occupied. DPEN# is multiplexed with PICD0. This signal indicates that a valid external address has been driven onto the Pentium processor with MMX technology address pins to be used for an inquire cycle. The external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. When the Pentium processor with MMX technology generates a write, and EWBE# is sampled inactive, the Pentium processor with MMX technology will hold off all subsequent writes to all E- or Mstate lines in the data cache until all write cycles have completed, as indicated by EWBE# being active. The floating-point error pin is driven active when an unmasked floating-point error occurs. FERR# is similar to the ERROR# pin on the Intel387TM math coprocessor. FERR# is included for compatibility with systems using DOS type floating-point error reporting. FERR# is never driven active by the Dual processor.
[DPEN#] PICD0
I/O
EADS#
I
EWBE#
I
FERR#
O
17
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Table 2. Quick Pin Reference (Cont'd) Symbol FLUSH# Type I Name and Function When asserted, the cache flush input forces the Pentium processor with MMX technology to write back all modified lines in the data cache and invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the Pentium processor with MMX technology indicating completion of the write back and invalidation. If FLUSH# is sampled low when RESET transitions from high to low, tristate test mode is entered. If two Pentium processors with MMX technology are operating in dual processing mode and FLUSH# is asserted, the Dual processor will perform a flush first (without a flush acknowledge cycle), then the Primary processor will perform a flush followed by a flush acknowledge cycle. NOTE: If the FLUSH# signal is asserted in dual processing mode, it must be deasserted at least one clock prior to BRDY# of the FLUSH Acknowledge cycle to avoid DP arbitration problems. FRCMC# I Functional Redundancy Checking is not supported on thePentium processor with MMX technology. The FRCMC# pin is not defined for the Pentium processor with MMX technology. This pin should be left as a"NC" or tied to VCC3 via an external pull-up resistor. The hit indication is driven to reflect the outcome of an inquire cycle. If an inquire cycle hits a valid line in either the Pentium processor with MMX technology data or instruction cache, this pin is asserted two clocks after EADS# is sampled asserted. If the inquire cycle misses the Pentium processor with MMX technology cache, this pin is negated two clocks after EADS#. This pin changes its value only as a result of an inquire cycle and retains its value between the cycles. The hit to a modified line output is driven to reflect the outcome of an inquire cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. It is used to inhibit another bus master from accessing the data until the line is completely written back. The bus hold acknowledge pin goes active in response to a hold request driven to the processor on the HOLD pin. It indicates that the Pentium processor with MMX technology has floated most of the output pins and relinquished the bus to another local bus master. When leaving bus hold, HLDA will be driven inactive and the Pentium processor with MMX technology will resume driving the bus. If the Pentium processor with MMX technology has a bus cycle pending, it will be driven one clock cycle after HLDA is de-asserted. In response to the bus hold request, the Pentium processor with MMX technology will float most of its output and input/output pins and assert HLDA after completing all outstanding bus cycles. The Pentium processor with MMX technology will maintain its bus in this state until HOLD is de-asserted. HOLD is not recognized during LOCK cycles. The Pentium processor with MMX technology will recognize HOLD during reset.
HIT#
O
HITM#
O
HLDA
O
HOLD
I
18
E
Symbol IERR# Type O IGNNE# I
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 2. Quick Pin Reference (Cont'd) Name and Function The internal error pin is used to indicate internal parity errors. If a parity error occurs on a read from an internal array, the Pentium processor with MMX technology will assert the IERR# pin for one clock and then shutdown. This is the ignore numeric error input. This pin has no effect when the NE bit in CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the Pentium processor with MMX technology will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium processor with MMX technology will execute the instruction in spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the floating-point instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium processor with MMX technology will stop execution and wait for an external interrupt. IGNNE# is internally masked when the Pentium processor with MMX technology is configured as a Dual processor. INIT I The Pentium processor with MMX technology initialization input pin forces the Pentium processor with MMX technology to begin execution in a known state. The processor state after INIT is the same as the state after RESET except that the internal caches, write buffers, and floating-point registers retain the values they had prior to INIT. INIT may NOT be used in lieu of RESET after power-up. If INIT is sampled high when RESET transitions from high to low, thePentium processor with MMX technology will perform built-in self test prior to the start of program execution. INTR/LINT0 I An active maskable interrupt input indicates that an external interrupt has been generated. If the IF bit in the EFLAGS register is set, thePentium processor with MMX technology will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. INTR must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. If the local APIC is enabled, this pin becomes LINT0. INV I The invalidation input determines the final cache line state (S or I) in case of an inquire cycle hit. It is sampled together with the address for the inquire cycle in the clock EADS# is sampled active. The cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. When the Pentium processor with MMX technology generates a cycle that can be cached (CACHE# asserted) and KEN# is active, the cycle will be transformed into a burst line fill cycle.
KEN#
I
19
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Table 2. Quick Pin Reference (Cont'd) Symbol LINT0/INTR LINT1/NMI LOCK# Type I I O Name and Function If the APIC is enabled, this pin is local interrupt 0. If the APIC is disabled, this pin is INTR. If the APIC is enabled, this pin is local interrupt 1. If the APIC is disabled, this pin is NMI. The bus lock pin indicates that the current bus cycle is locked. ThePentium processor with MMX technology will not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. The memory/input-output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes between memory and I/O cycles. An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. The Pentium processor with MMX technology will issue ADS# for a pending cycle two clocks after NA# is asserted. The Pentium processor with MMX technology supports up to 2 outstanding bus cycles. The non-maskable interrupt request signal indicates that an external non-maskable interrupt has been generated. If the local APIC is enabled, this pin becomes LINT1. PBGNT# I/O Private bus grant is the grant line that is used when two Pentium processors with MMX technology are configured in dual processing mode, in order to perform private bus arbitration. PBGNT# should be left unconnected if only one Pentium processor with MMX technology exists in a system. Private bus request is the request line that is used when two Pentium processor with MMX technology are configured in dual processing mode, in order to perform private bus arbitration. PBREQ# should be left unconnected if only one Pentium processor with MMX technology exists in a system. The page cache disable pin reflects the state of the PCD bit in CR3, the Page Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an external cacheability indication on a page by page basis. The parity check output indicates the result of a parity check on a data read. It is driven with parity status two clocks after BRDY# is returned. PCHK# remains low one clock for each clock in which a parity error was detected. Parity is checked only for the bytes on which valid data is returned. When two Pentium processors with MMX technology are operating in dual processing mode, PCHK# may be driven two or three clocks after BRDY# is returned.
M/IO#
O
NA#
I
NMI/LINT1
I
PBREQ#
I/O
PCD
O
PCHK#
O
20
E
Symbol PEN# Type I PHIT# I/O PHITM# I/O
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 2. Quick Pin Reference (Cont'd) Name and Function The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. If this pin is sampled active in the clock a data parity error is detected, the Pentium processor with MMX technology will latch the address and control signals of the cycle with the parity error in the machine check registers. If, in addition, the machine check enable bit in CR4 is set to "1", the Pentium processor with MMX technology will vector to the machine check exception before the beginning of the next instruction. Private hit is a hit indication used when two Pentium processors with MMX technology are configured in dual processing mode, in order to maintain local cache coherency. PHIT# should be left unconnected if only one Pentium processor with MMX technology exists in a system. Private modified hit is a hit on a modified cache line indication used when two Pentium processors with MMX technology are configured in dual processing mode, in order to maintain local cache coherency. PHITM# should be left unconnected if only one Pentium processor with MMX technology exists in a system. The APIC interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the Pentium processor with MMX technology. This pin is 3.3V-tolerant-only on the Pentium processor with MMX technology. Please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428) for the CLK and PICCLK signal quality specification. PICD0-1 [DPEN#] [APICEN] PM/BP[1:0] I/O Programmable interrupt controller data lines 0-1 of the Pentium processor with MMX technology comprise the data portion of the APIC 3-wire bus. They are open-drain outputs that require external pull-up resistors. These signals are multiplexed with DPEN# and APICEN respectively. These pins function as part of the performance monitoring feature. The breakpoint 1-0 pins are multiplexed with theperformance monitoring 1-0 pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring. PRDY O The probe ready output pin is provided for use with the Intel debug port. Please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428) for more details. The page write through pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry. The PWT pin is used to provide an external write back indication on a page-by-page basis. The run/stop input is provided for use with the Intel debug port. Please refer to the Pentium(R) Processor Family Developer's Manual (Order Number 241428) for more details.
PICCLK
I
O
PWT
O
R/S#
I
21
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Table 2. Quick Pin Reference (Cont'd) Symbol RESET Type I Name and Function RESET forces the Pentium processor with MMX technology to begin execution at a known state. All the Pentium processor with MMX technology internal caches will be invalidated upon the RESET. Modified lines in the data cache are not written back. FLUSH# and INIT are sampled when RESET transitions from high to low to determine if tristate test mode or checker mode will be entered, or if Built-In Self-Test (BIST) will be run. The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together. This signal is defined for locked cycles only. It is undefined for cycles which are not locked. The system management interrupt causes a system management interrupt request to be latched internally. When the latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode. An active system management interrupt active output indicates that the processor is operating in System Management Mode. Assertion of the stop clock input signifies a request to stop the internal clock of the Pentium processor with MMX technology, thereby causing the core to consume less power. When the CPU recognizes STPCLK#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK# is asserted, the Pentium processor with MMX technology will still respond to interprocessor and external snoop requests. The testability clock input provides the clocking function for the Pentium processor with MMX technology boundary scan in accordance with the IEEE Boundary Scan interface (Standard 1149.1). It is used to clock state information and data into and out of the Pentium processor with MMX technology during boundary scan. The test data input is a serial input for the test logic. TAP instructions and data are shifted into the Pentium processor with MMX technology on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state. The test data output is a serial output of the test logic. TAP instructions and data are shifted out of the Pentium processor with MMX technology on the TDO pin on TCK's falling edge when the TAP controller is in an appropriate state. The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes. When asserted, the test reset input allows the TAP controller to be asynchronously initialized. The Pentium processor with MMX technology has 25 2.8Vpower inputs. The Pentium processor with MMX technology has 28 3.3Vpower inputs. VCC2 detect is used in flexible motherboard implementations to configure the voltage output set-point appropriately for the V inputs of the processor. CC2
SCYC
O
SMI#
I
SMIACT# STPCLK#
O I
TCK
I
TDI
I
TDO
O
TMS TRST# VCC2 VCC3 VCC2DET#
I I I I O
22
E
Symbol VSS W/R# Type I O WB/WT# I
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 2. Quick Pin Reference (Cont'd) Name and Function The Pentium processor with MMX technology has 53ground inputs. Write/read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W/R# distinguishes between write and read cycles. The write back/write through input allows a data cache line to be defined as write back or write through on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
Core and bus frequencies can be set according to Table 3 below. Each Pentium processor with MMX technology specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to maximum core frequency range). Operation in other bus-to-core ratios or outside the specified operating frequency range is not supported. For example, the 166 MHz Pentium processor with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2/5 bus-to-core ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. Table 3 clarifies and summarizes these specifications. Table 3. Bus Frequency Selections BF1 0 0 1 1 BF0 1 0 0 1 Bus/Core Ratio 1/3 2/5 1/2 (1, 2) 2/7 Max Bus/Core Frequency (MHz) 66/200 66/166 N/A (2) 66/233 Min Bus/Core Frequency (MHz) 33/100 33/83 N/A (2) 33/117
NOTES: 1. This is the default bus to core ratio for the Pentium(R) processor with MMXTM technology. If the BF pins are left floating, the processor will be configured for the 1/2 bus to core frequency ratio. 2. Currently, there are no products that support these bus fractions.
23
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
2.4.
Pin Reference Tables
Table 4. Output Pins Name Active Level Low Low Low Low High Low N/A Low Low Low High Low Low N/A Low High High High High Low N/A Low Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF# Bus Hold, BOFF#
E
ADS#
(1)
ADSC# APCHK# BE7#-BE4# BREQ CACHE# (1) D/P# (2) FERR# (2) HIT# (1) HITM# (1, 3) HLDA (1) IERR# LOCK# (1) M/IO# (1), D/C# (1), W/R# (1) PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, PCD SCYC (1) SMIACT# TDO VCC2DET#
All states except Shift-DR and Shift-IR
NOTES: All output and input/output pins are floated during tristate test mode (except IERR#). 1. These are I/O signals when two Pentium(R) processor with MMXTM technology are operating in dual processing mode. 2. These signals are undefined when the processor is configured as a Dual processor. 3. M# pin has an internal pull-up resistor.
24
E
Name A20M# (1) AHOLD APICEN BF0 BF1 BOFF# BRDY# BRDYC# BUSCHK# CLK CPUTYP EADS# EWBE# FLUSH# HOLD IGNNE# (1) INIT INTR INV LINT[1:0] KEN# NA# NMI PEN# PICCLK R/S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB/WT# Active Level Low High High N/A N/A Low Low Low Low N/A High Low Low Low High Low High High High High Low Low High Low High N/A High Low Low N/A N/A N/A Low N/A
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 5. Input Pins Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Synchronous Synchronous/RESET Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up First BRDY#/NA# TCK TCK Pull-up Pull-up BRDY# EADS# APICEN at RESET First BRDY#/NA# Bus State T2, TD, T2P BRDY# Pull-up Pull-up Pull-up Pull-down Bus State T2, T12, T2P Bus State T2, T12, T2P BRDY# Pull-up Pull-down Pull-up Internal Resistor Qualified
NOTES: 1. Undefined when the processor is configured as a Dual processor.
25
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
(1)
Table 6. Input/Output Pins Name A31-A3 AP BE3#-BE0# D63-D0 DP7-DP0 DPEN# PICD0 PICD1 Active Level N/A N/A Low N/A N/A low N/A N/A When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF#
Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# RESET
Internal Resistor
Pull-down (2)
Pull-up Pull-up Pull-down
NOTES: 1. All output and input/output pins are floated during tristate test mode (except TDO, IERR# and TDO). 2. BE3#-BE0# have Pull-downs during RESET only.
Table 7. Inter-Processor Input/Output Pins Name PHIT# PHITM# PBGNT# PBREQ# Active Level Low Low Low Low Internal Resistor Pull-up Pull-up Pull-up Pull-up
NOTES: For proper inter-processor operation, the system cannot load these signals.
26
E
2.5.
Clock
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Pin Grouping According to Function
Table 8 organizes the pins with respect to their function. Table 8. Pin Functional Grouping Function CLK RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, NA# PCD, PWT KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# CPUTYP, D/P# R/S#, PRDY VCC2DET# Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Bus Arbitration Dual Processing Private Bus Control Interrupts Floating-Point Error Reporting System Management Mode TAP Port Breakpoint/Performance Monitoring Power Management Miscellaneous Dual Processing Debugging Voltage Detection Pins
27
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
3.0.
ELECTRICAL SPECIFICATIONS
This section describes the electrical differences between the Pentium processor with MMX technology and the Pentium processor 133/150/166/200, as well as the AC and DC specifications of the Pentium processor with MMX technology.
Pentium processor 133/150/166/200 designs can easily be converted to support the Pentium processor with MMX technology. In order to maintain compatibility with Pentium processor 133/150/166/200-based platforms, the Pentium processor with MMX technology supports the standard 3.3V specification on its VCC3 pins. 3.1.1.1. Power Supply Sequencing
E
3.1.
Electrical Characteristics and Differences between the Pentium(R) Processor with MMXTM Technology and the Pentium Processor 133/150/166/200
There is no specific power sequence required for powering up or powering down the separate VCC2 and VCC3 supplies of the Pentium processor with MMX technology. It is recommended that the VCC2 and VCC3 supplies be either both ON or both OFF within one second of each other. 3.1.2. CONNECTION SPECIFICATIONS
When designing a Pentium processor with MMX technology system from a Pentium processor 133/150/166/200 system, there are a number of electrical differences that require attention. Designing a single motherboard that supports various members of the Pentium processor family including the Pentium processor with MMX technology, Pentium processor 133/150/166/200, Pentium OverDrive(R) processor, or future Pentium OverDrive processor can be easily accomplished. Refer to the Pentium(R) Processor Flexible Motherboard Design Guidelines application note (Order Number 243187) for more information and specific implementation examples. The following sections highlight key electrical issues pertaining to the Pentium processor with MMX technology power supplies, connection specifications and buffer models. 3.1.1. POWER SUPPLIES
Connection specifications for the power and ground inputs, 3.3V inputs and outputs, and the NC/INC and unused inputs are discussed in the following sections. 3.1.2.1. Power and Ground
For clean on-chip power distribution, the Pentium processor with MMX technology in PPGA and SPGA packages has 28 VCC3 (I/O power), 25 VCC2 (core power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external VCC and VSS pins of the Pentium processor with MMX technology. On the circuit board all VCC3 pins must be connected to a 3.3V VCC plane. All VCC2 pins must be connected to a 2.8V VCC plane. All VSS pins must be connected to a VSS plane. 3.1.2.1.1. VCC2 and VCC3 Measurement Specification
The main electrical difference between the Pentium processor with MMX technology and the Pentium processor 133/150/166/200 is the operating voltage. The Pentium processor with MMX technology requires two separate voltage inputs, VCC2 and VCC3. The VCC2 pins supply power to the Pentium processor with MMX technology core, while the VCC3 pins supply power to the processor I/O pins. The Pentium processor 133/150/166/200, on the other hand, requires a single voltage supply for all VCC pins. This single supply powers both the core and I/O pins of the Pentium processor 133/150/166/200. By connecting all of the VCC2 pins together and all the VCC3 pins together on separate power islands, 28
The values of VCC2 and VCC3 should be measured at the bottom side of the processor pins using an oscilloscope with a 3 dB bandwidth of at least 20 MHz (100 MS/s digital sampling rate). There should be a short isolation ground lead attached to a processor pin on the bottom side of the board. The measurement should be taken at the following VCC/VSS pairs: AN13/AM10, AN21/AM18, AN29/ AM26, AC37/Z36, U37/R36, L37/H36, A25/B28, A17/B20, A7/B10, G1/K2, S1/V2, AC1/Z2. One-half of these pins are VCC2 while the others are VCC3; the operating ranges for the VCC2 and VCC3 pins are
E
3.1.2.1.2.
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the Pentium processor with MMX technology on both the VCC2 and VCC3 plane to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. Detailed decoupling recommendations are provided in the Flexible Motherboard Design Guidelines application note (Order Number 243187) 3.1.2.2. 3.3V Inputs and Outputs
specified at different voltages. See Table 10 for the specification. The display should show continuous sampling of the voltage line, at 20 mV/div, and 500 ns/div with the trigger point set to the center point of the range. Slowly move the trigger to the high and low ends of the specification, and verify that excursions beyond these limits are not observed. There are no allowances for crossing the high and low limits of the voltage specification. For more information on measurement techniques, see the Voltage Guidelines for Pentium(R) Processors with MMXTM Technology application note (Order Number 243186). Decoupling Recommendations
Liberal decoupling capacitance should be placed near the Pentium processor with MMX technology. The Pentium processor with MMX technology, when driving its large address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the Pentium processor with MMX technology and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the power plane. Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. For the Pentium processor with MMX technology, the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. A typical example would be entering or exiting the Stop Grant State. Another example would be executing a HALT instruction, causing the Pentium processor with MMX technology to enter the AutoHALT Power Down State, or transitioning from HALT to the Normal State. All of these examples may cause abrupt changes in the power being consumed by the Pentium processor with MMX technology. Note that the AutoHALT Power Down feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low Effective Series Resistance (ESR) in the 10 to 100 range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power
The inputs and outputs of the Pentium processor with MMX technology comply with the 3.3V JEDEC standard levels. Both inputs and outputs are also TTL-compatible, although the inputs cannot tolerate voltage swings above the VIN3 (max) specification. System support components which use TTLcompatible inputs will interface to the Pentium processor with MMX technology without extra logic. This is because the Pentium processor drives according to the 5V TTL specification (but not beyond 3.3V). For Pentium processor with MMX technology inputs, the voltage must not exceed the 3.3V VIN3 (max) specification. System support components can consist of 3.3V devices or open-collector devices. In an open-collector configuration, the external resistor should be biased to VCC3. All pins, including the CLK and PICCLK of the Pentium processor with MMX technology, are 3.3Vtolerant-only. If an 8259A interrupt controller is used, for example, the system must provide level converters between the 8259A and the Pentium processor with MMX technology. 3.1.2.3. NC/INC and Unused Inputs
All NC and INC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to V (ground). SS
29
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
3.1.2.4. Private Bus
When two Pentium processors with MMX technology are operating in dual processor mode, a "private bus" exists to arbitrate for the processor bus and maintain local cache coherency. The private bus consists of two pinout changes: 1. 2. Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. Ten output pins become I/O pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#, HITM#, HLDA, SCYC, BE#4.
the values of the components have changed to reflect the minor manufacturing process and package differences between the processors. The system should see insignificant differences between the AC behavior of the Pentium processor with MMX technology and the Pentium processor 133/150/166/200. Simulation of AC timings using the Pentium processor with MMX technology buffer models is recommended to ensure robust system designs. Pay specific attention to the signal quality restrictions imposed by 3.3V buffers.
E
The new pins are given AC specifications of valid delays at 0 pF, setup times and hold times. Simulate with these parameters and their respective I/O buffer models to guarantee that proper timings are met. The AC specification gives input setup and hold times for the ten signals that become I/O pins. These setup and hold times must only be met when a dual processor is present in the system. 3.1.3. BUFFER MODELS
3.2.
Absolute Maximum Ratings
Table 9 provides stress ratings only. Functional operation at the Absolute Maximum Ratings is not implied or guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor with MMX technology contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields.
The structure of the buffer models for the Pentium processor with MMX technology and the Pentium processor 133/150/166/200 are identical. Some of
Table 9. Absolute Maximum Ratings Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 VCC3 Supply Voltage with respect to VSS VCC2 Supply Voltage with respect to VSS 3V Only Buffer DC Input Voltage Min -65 -65 -0.5 -0.5 -0.5 Max 150 110 4.6 3.7 VCC3 +0.5 (not to exceed VCC3 max) WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the DC specifications is not recommended or guaranteed and extended exposure beyond the DC specifications may affect device reliability. Unit C C V V V Notes
30
E
3.3. DC Specifications
Symbol TCASE VCC2 VCC3 Parameter Case Temperature VCC2 Voltage VCC3 Voltage
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 10 and Table 11 list the DC Specifications of the Pentium processor with MMX technology. Table 10. VCC and TCASE Specifications Min 0 2.7 3.135 2.8 3.3 Nom Max 70 2.9 3.6 Unit C V V Range = 2.8 3.57% (1) Range = 3.3 -5%, +9.09% (1) Notes
NOTES: 1. See the VCC measurement specification section earlier in this chapter.
Table 11. 3.3V DC Specifications (See Table 10 for VCC and TCASE assumptions.) Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 Min -0.3 2.0 Max 0.8 VCC3 +0.3 0.4 Unit V V V V Notes TTL Level TTL Level (3) TTL Level (1, 4) TTL Level (2)
NOTES: 1. Parameter measured at -4 mA. 2. Parameter measured at 3 mA. 3. Parameter measured at nominal VCC3 which is 3.3V. 4. In dual processing systems, up to a 10 mA load from the second processor may be observed on the PCHK# signal. Based on silicon characterization data, VOL3 of PCHK# will remain less than 400 mV even with a 10 mA load. PCHK# V will OL3 increase to approximately 500 mV with a 14 mA load (worst case for a DP system with a 4 mA system load).
Table 12. ICC Specifications (Measured at VCC2=2.9V and VCC3=3.6V.) Symbol ICC2 Parameter Power Supply Current Min Max 6500 5700 4750 750 650 540 Unit mA mA mA mA mA mA Notes 233 MHz 200 Mhz (1) 166 MHz (1) 233 MHz 200 MHz 166 MHz
(1) (1)
ICC3
Power Supply Current
31
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
NOTES: 1. This value should be used for power supply design. It was determined using a worst case instruction mix and maximum VCC. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes.
E
Notes
(4)
Table 13. Power Dissipation Requirements for Thermal Design (Measured at VCC2=2.8V and VCC3=3.3V.) Parameter Active Power Typical 7.9 (5) 7.3 (5) 6.1 (5)
(1)
Max
(2)
Unit Watts Watts Watts Watts Watts Watts Watts
17.0 (6) 15.7 (6) 13.1 (6) 2.61 2.41 2.05
233 MHz 200 MHz 166 MHz 233 MHz (3) 200 MHz (3) 166 MHz (3) All frequencies
Stop Grant / Auto Halt Powerdown Power Stop Clock Power 0.03
< 0.3
NOTES: 1. This is the typical power dissipation in a system. This value is expected to be the average value that will be measured in a system using a typical device at VCC2 = 2.8V running typical applications. This value is highly dependent upon the specific system configuration. Typical power specifications are not tested. 2. Systems must be designed to thermally dissipate the maximum active power dissipation. It is determined using worst case instruction mix with VCC2 = 2.8V and VCC3 = 3.3 and also takes into account the thermal time constants of the package. 3. Stop Grant/Auto Halt Power Down Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT instruction. 4. Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input. 5. Active Power (typ) is the average power measured in a system using a typical device running typical applications under normal operating conditions at nominal VCC and room temperature. 6. Active Power (max) is the maximum power dissipation under normal operating conditions at nominal V CC2, worst-case temperature, while executing the worst case power instruction mix. Active power (max) is equivalent to Thermal Design Power (max).
32
E
Symbol CIN CO CI/O CCLK CTIN CTOUT CTCK ILI ILO IIH IIL Parameter Input Capacitance Output Capacitance I/O Capacitance CLK Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 14. Input and Output Characteristics Min Max 15 20 25 15 15 20 15 15 15 200 -400 Unit pF pF pF pF pF pF pF A A A A
(4) (4) (4) (4) (4) (4) (4)
Notes
0 < VIN < VIL, VIH > VIN > VCC (1) 0 < VIN < VIL, VIH > VIN > VCC (1) VIN = 2.4V (3) VIN = 0.4V (2, 5)
NOTES: 1. This parameter is for inputs/outputs without an internal pull-up or pull-down. 2. This parameter is for inputs with an internal pull-up. 3. This parameter is for inputs with an internal pull-down. 4. Guaranteed by design. 5. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
33
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
3.4.
AC Specifications
The AC specifications consist of output delays, input setup requirements and input hold requirements. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor with MMX technology operation. Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling to account for signal flight time delays.
Each Pentium processor with MMX technology specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to maximum core frequency range). Operation in other bus-tocore ratios or outside the specified operating frequency range is not supported. For example, the 166 MHz Pentium processor with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2/5 bus-to-core ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. Table 3 clarifies and summarizes these specifications.
E
Table 15. Pentium(R) Processor with MMXTM Technology AC Specifications for 66-MHz Bus Operation (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol Frequency t1a t1b t2 t3 t4 t5 t6a t6b t6c t6d t6e t6f t6g t6h CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time PWT, PCD, CACHE# Valid Delay AP Valid Delay BE0-7#, LOCK# Valid Delay ADS# Valid Delay ADSC#, D/C#, W/R#, SCYC, Valid Delay M/IO# Valid Delay A3-A16 Valid Delay A17-A31 Valid Delay 4.0 4.0 0.15 0.15 1.0 1.0 0.9 0.8 0.8 0.8 0.5 0.6 1.5 1.5 7.0 8.5 7.0 6.0 7.0 5.9 6.6 6.6 Parameter Min 33.33 15.0 Max 66.6 30.0 250 Unit MHz ns ps ns ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4 5 5 5 5 5 5 5 5
(4)
Figure 4 4
Notes
Adjacent Clocks (1, 25) 2V (1) 0.8V (1) (2.0V-0.8V) (1, 5) (0.8V-2.0V) (1, 5)
34
E
Symbol t7 Parameter ADS#, ADSC#, AP, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay t8a t8b t9a t9b t9c t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24a PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 15. Pentium(R) Processor with MMXTM Technology AC Specifications for 66-MHz Bus Operation (Cont'd) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Min Max 10.0 Unit ns Figure 6
(1)
Notes
APCHK#, IERR#, FERR# Valid Delay
1.0 1.0 1.0 1.0 1.0 1.0 0.7 1.0 1.0 1.3
8.3 7.0 8.0 7.3 6.8 6.8 6.0 10.0 8.0 7.5 10.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5 5 5 5 5 5 5 5 5 6 7 7 7 7 7 7 7 7 7 7 7 7 7
(4)
(4) (4) (4)
D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time EADS#, INV, AP Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, NA# Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time
(1)
6.0 1.0 5.0 5.0 1.0 5.0 4.5 1.0 5.0 1.0 5.5 1.0 5.0
(26)
35
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Unit ns ns ns ns ns ns ns CLK ns ns CLK ns ns ns ns CLK ms ns ns CLK 7 7 8 8 8 8 8 8
(12, 16) (13) (17)
Table 15. Pentium(R) Processor with MMXTM Technology AC Specifications for 66-MHz Bus Operation (Cont'd) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol t24b t25a t25b t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42a Parameter PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, VCC & CLK Stable RESET Active After VCC & CLK Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals Min 4.8 1.0 1.5 5.0 1.0 5.0 1.0 2.0 5.0 1.0 2.0 2.8 1.5 5.0 1.0 15.0 1.0 5.0 1.0 2.0 Max Figure 7 7 7 7 7 7 7
(12, 16)
Notes
(13)
(12, 16, 17)
(13)
(15, 17)
7 7
(12, 16, 17) (13) 15, 17)
Power up
(12, 16, 17)
(13)
To RESET falling edge
(16)
t42b 36
2.0
CLK
To RESET falling edge
E
Symbol Parameter (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. t42c Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 BF0, BF1, CPUTYP Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 15. Pentium(R) Processor with MMXTM Technology AC Specifications for 66-MHz Bus Operation (Cont'd) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Min Max Unit Figure
(27)
Notes
3.0
CLK
To RESET falling edge
(27)
BF0, BF1, CPUTYP Setup Time
1.0 2.0 2.0 2.0 16.0 62.5 25.0 25.0 5.0 5.0 40.0 5.0 13.0 2.5 20.0 25.0 2.5 20.0 25.0 5.0 13.0
ms CLK CLK CLK MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8
To RESET falling edge
(22)
To RESET falling edge
(22)
To RESET falling edge To RESET falling edge
4 4 4 4 4 10 9 9 9 9 9 9 9 9 2V (1) 0.8V (1) (2.0V-0.8V) (1, 8, 9) (0.8V-2.0V) (1, 8, 9) Asynchronous (1)
(7) (7) (8) (1, 8) (3, 8, 10) (1, 3, 8, 10) (3, 7, 10) (3, 7, 10)
All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
APIC AC Specifications t60a t60b t60c t60d PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time 2.0 60.0 15.0 15.0 16.66 500.0 MHz ns ns ns 4 4 4 4 37
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Unit ns ns ns ns Figure 4 4 7 7 5 5 To PICCLK To PICCLK From PICCLK (28) From PICCLK (28) Notes ns ns
Table 15. Pentium(R) Processor with MMXTM Technology AC Specifications for 66-MHz Bus Operation (Cont'd) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol t60e t60f t60g t60h t60i t60j Parameter PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (LtoH) PICD0-1 Valid Delay (HtoL) Min 0.15 0.15 3.0 2.5 4.0 4.0 38.0 22.0 Max 2.5 2.5
NOTES: Please refer to Table 16 for footnotes.
38
E
Symbol t80a t80b t83a t83b t83c t83d t83e t84a t84b Parameter PBREQ#, PBGNT#, PHIT# Flight Time PHITM# Flight Time A5-A31 Setup Time D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time ADS#, M/IO# Setup Time HIT#, HITM# Setup Time HLDA Setup Time CACHE#, HIT# Hold Time ADS#, D/C#, W/R#, M/IO#, A5-A31, HLDA, SCYC Hold Time LOCK# Hold Time HITM# Hold Time DPEN# Valid Time DPEN# Hold Time APIC ID (BE0#-BE3#) Setup Time APIC ID (BE0#-BE3#) Hold Time D/P# Valid Delay
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Table 16. Pentium(R) Processor with MMXTM Technology Dual Processor Mode AC Specifications for 66-MHz Bus Operation (See Table 10 for VCC and TCASE assumptions.) Min 0.0 0.0 3.7 4.0 5.8 6.0 6.0 1.0 0.8 Max 2.0 1.8 Unit ns ns ns ns ns ns ns ns ns Figure 5 5 7 7 7 7 7 7 7
(11, 24)
Notes
(11, 24) (18) (18, 21)
(18, 21) (18, 21) (18, 21) (18, 21) (18, 21)
t84c t84d t85 t86 t87 t88 t89
0.9 0.7 10.0 2.0 2.0 2.0 1.0 8.0
ns ns CLK CLK CLK CLK ns
7 7
(18, 21) (18, 21) (18, 19, 23) (18, 20, 23)
8 8 5
To falling Edge of RESET (23) From Falling Edge of RESET (23) Primary Processor Only
NOTES: (R) Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium processor family. Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer models to account for signal flight time delays. 1. Not 100% tested. Guaranteed by design/characterization. 2. TTL input test waveforms are assumed to be 0 to 3V transitions with 1 V/ns rise and fall times. 3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and TMS). These timings correspond to the response of these signals due to boundary scan operations. 4. APCHK#, FERR#, HLDA, IERR#, LOCK# and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8V/ns ( CLK input rise/fall time 8V/ns. 6. 0.3V/ns ( input rise/fall time 5V/ns. 7. Referenced to TCK rising edge. 8. Referenced to TCK falling edge. 9. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz. 10. During debugging, do not use the boundary scan timings (t55 to t58).
39
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
11. This is a flight time specification, that includes both flight time and clock skew. The flight time is the time from where the unloaded driver crosses 1.5V (50% of min VCC), to where the receiver crosses the 1.5V level (50% of min VCC). See Figure 11. The minimum flight time minus the clock skew must be greater than zero. 12. Setup time is required to guarantee recognition on a specific clock. Pentium processor with MMXTM technology must meet this specification for dual processor operation for the FLUSH# and RESET signals. 13. Hold time is required to guarantee recognition on a specific clock. Pentium processor with MMX technology must meet this specification for dual processor operation for the FLUSH# and RESET signals. 14. All TTL timings are referenced from 1.5V. 15. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. 16. This input may be driven asynchronously. However, when operating two processors in dual processing mode, FLUSH# and RESET must be asserted synchronously to both processors. 17. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT and SMI# must be de-asserted (inactive) for a minimum of two clocks before being returned active. 18. Timings are valid only when dual processor is present. 19. Maximum time DPEN# is valid from rising edge of RESET. 20. Minimum time DPEN# is valid after falling edge of RESET. 21. The D/C#, M/IO#, W/R#, CACHE# and A5-A31 signals are sampled only on the CLK that ADS# is active. 22. In order to override the internal defaults and guarantee that the BF[1:0] inputs remain stable while RESET is active, these pins should be strapped directly to or through a pull-up/pull-down resistor to VCC3 or ground. Driving these pins with active logic is not recommended unless stability duringt RESET can be guaranteed. Similarly, CPUTYP should also be strapped directly to or through a pull-up/pull-down resistor to VCC3 or ground. 23. RESET is synchronous in dual processing mode. All signals which have a setup or hold time with respect to a falling or rising edge of RESET in UP mode, should be measured with respect to the first processor clock edge in which RESET is sampled either active or inactive in dual processing mode. 24. The PHIT# and PHITM# signals operate at the core frequency. 25. These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 kHz and 1/3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. The internal clock generator requires a constant frequency CLK input to within 250 ps. Therefore, the CLK input cannot be changed dynamically. 26. In dual processing mode, timing t14 is replaced by t83a . Timing t14 is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active) in both uniprocessor and dual processor modes. 27. BRDYC# and BUSCHK# are used as reset configuration signals to select buffer size. 28. This assumes an external pull-up resistor to VCC and a lumped capacitive load. The pull-up resistor must be between 300 ohms and 1K ohms, the capacitance must be between 20 pF and 240 pF, and the RC product must be between 6 ns and 36 ns. VOL for PICD0-1 is 0.55V.
E
Tz Tv 2.0V CLK 0.8V Tw Tx Ty
Tv = t5, t49, t60e Tw = t4, t48, t60f Tx = t3, t47, t60d Ty = t1, t45, t60b Tz = t2, t46, t60c
1.5V
Figure 4. Clock Waveform 40
E
1.5V Tx max. Signal
Tx = t6, t8, t9, t10, t11, t12, t60i, t60j, t80a, t89
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Tx min.
1.5V
VALID
Figure 5. Valid Delay Timings
Tx = t7, t13; Ty = t6min, t12min
Figure 6. Float Delay Timings
Tx = t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g (to PICCLK),t81, t83 Ty = t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h (to PICCLK), t82, t84
Figure 7. Setup and Hold Timings
41
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Tt = t40, Tu = t41, Tv = t37, T w =t42, t43a, t43c, t87, Tx = t43b, t43d, t43f, t88, Ty = t38, t39, Tz = t36
Figure 8. Reset and Configuration Timings
Tr = t57, Ts = t58, Tu = t54, Tv = t51, Tw = t52, Tx = t53, Ty = t55, Tz = t56
Figure 9. Test Timings
Tx = t50
Figure 10. Test Reset Timings
42
E
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Figure 11. 50 Percent VCC Measurement of Flight Time
4.0.
MECHANICAL SPECIFICATIONS
The Pentium processor with MMX technology is packaged in 296-pin staggered pin grid array ceramic (SPGA) or plastic (PPGA) packages. The pins are arranged in a 37 x 37 matrix and the package dimensions are 1.95" x 1.95" (Table 17). A 1.25" x 1.25" copper tungsten heat spreader may be attached to the top of some of the ceramic packages. This package design with spreader has been replaced with a package which has no attached
spreader. In this section, both ceramic (spreader and non-spreader) as well as plastic packages are shown. Package summary information is provided in Table 17. The mechanical specifications for the Pentium processor with MMX technology are provided in Table 18 and Table 19. Figure 12 and Figure 13 show the package dimensions.
Table 17. Package Information Summary for Pentium(R) Processor with MMXTM Technologty Package Type Ceramic Staggered Pin Grid Array (SPGA) Plastic Staggered Pin Grid Array (PPGA) Total Pins 296 296 Pin Array 37 x 37 37 x 37 Package Size 1.95" x 1.95" 4.95 cm x 4.95 cm 1.95" x 1.95" 4.95 cm x 4.95 cm
43
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
SEATING PLANE L
e1
D D1 S1
1.65 REF.
S1
D1 D B
Pin C3
2.29 REF. 1.52 45 INDEX CHAMFER (INDEX CORNER)
A A1 A2
Figure 12. SPGA Package Dimensions
Table 18. SPGA Package Dimensions Millimeters Symbol A A1 A2 B D D1 e1 L N S1 1.52 Min 2.62 0.69 3.31 0.43 49.28 45.59 2.29 3.05 296 2.54 Max 2.97 0.84 3.81 0.51 49.78 45.85 2.79 3.30 Lead Count 0.060 Ceramic Lid Ceramic Lid Notes Min 0.103 0.027 0.130 0.017 1.940 1.795 0.090 0.120 296 0.100 Inches Max 0.117 0.033 0.150 0.020 1.960 1.805 0.110 0.130 Lead Count Ceramic Lid Ceramic Lid Notes
44
E
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Figure 13. PPGA Package Dimensions
Table 19. PPGA Package Dimensions Millimeters Symbol A A1 A2 B D D1 D2 e1 F1 F2 L N 3.05 296 0.40 49.43 45.59 23.44 2.29 17.56 23.04 3.30 Lead Count 0.120 296 Min 2.72 1.83 1.00 0.51 49.63 45.85 23.95 2.79 0.016 1.946 1.795 0.923 0.090 0.692 0.907 0.130 Lead Count Max 3.33 2.23 Notes Min 0.107 0.072 0.039 0.020 1.954 1.805 0.943 0.110 Inches Max 0.131 0.088 Notes
45
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
Inches Min 0.060 Max 0.100 Notes THERMAL EQUATIONS AND DATA TA = TC - (P * CA)
Table 19. PPGA Package Dimensions Millimeters Symbol S1 Min 1.52 Max 2.54 Notes
5.0.
THERMAL SPECIFICATIONS
5.1.1.
The Pentium processor with MMX technology is specified for proper operation when case temperature, TCASE, (TC) is within the specified range of 0C to 70C.
For the Pentium processor with MMX technology, an ambient temperature, TA (air temperature around the processor), is not specified directly. The only restriction is that TC is met. To calculate TA values, the following equations may be used:
5.1.
Measuring Thermal Values
Where:
To verify that the proper TC is maintained, it should be measured at the center of the package top surface (opposite of the pins). The measurement is made in the same way with or without a heatsink attached. When a heatsink is attached, a hole (smaller than 0.150" diameter) should be drilled through the heatsink to allow probing the center of the package. See Figure 14 for an illustration of how to measure TC. To minimize the measurement errors, recommended to use the following approach: it is
CA = JA - JC
TA and TC = Ambient and case temperature. (C)
CA = JA = JC =
Case-to-ambient thermal resistance. (C/Watt) Junction-to-ambient thermal resistance. (C/Watt) Junction-to-case thermal resistance. (C/Watt) Maximum power consumption (Watt)
*
Use 36-gauge or finer diameter K, T, or J type thermocouples. The laboratory testing was done using a thermocouple made by Omega* (part number 5TC-TTK-36-36). Attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements. The laboratory testing was done by using Omega Bond (part number OB-100). The thermocouple should be attached at a 90degree angle as shown in Figure 14. The hole size should be smaller than 0.150' in diameter. Make sure there is no contact between thermocouple cement and heatsink base. The contact will affect the thermocouple reading.
P=
*
* * *
Table 20 and Table 21 list the JC and CA values for the Pentium processor with MMX technology with passive heatsinks. JC is thermal resistance from die to package case. JC values shown in these tables are typical values. The actual JC values depend on actual thermal conductivity and process of die attach. CA is thermal resistance from package case to the ambient. CA values shown in these tables are typical values. The actual CA values depend on the heatsink design, interface between heatsink and package, the air flow in the system, and thermal interactions between processor and surrounding components through PCB and the ambient. Figure 15 and Figure 16 show Table 20 and Table 21 in graphical format.
46
E
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
PPGA
SPGA Figure 14. Technique fore Measuring TC on PPGA and SPGA Packages
47
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
200 6.7 6.1 5.4 4.8 4.4 4.0 3.7 3.4 3.1 12.1 400 4.6 4.1 3.7 3.3 3.1 2.9 2.7 2.5 2.3 9.7 600 3.7 3.4 3.0 2.7 2.5 2.3 2.2 2.1 2.0 8.0 800 3.1 2.9 2.6 2.4 2.2 2.1 1.9 1.9 1.8 7.0
Table 20. Thermal Resistance for SPGA Packages Heatsink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink
JC
(C/Watt) 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 1.4 0 9.2 8.9 8.5 8.2 7.8 7.1 6.4 6.0 5.5 14.4
CA (C/Watt) vs. Laminar Airflow (linear ft/min)
100 8.1 7.6 7.1 6.6 6.1 5.4 4.8 4.4 4.0 13.4
NOTES: Heatsinks are omni directional pin aluminum alloy. Features were based on standard extrusion practices for a given height: Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 200 mils Heatsink attach was 0.005" of thermal grease. Attach thickness of 0.002" will improve performance approximately 0.3C/Watt.
48
E
10 9 8 7 Theta ca [C/W] 6 5 4 3 2 1 0 0.2 0.4
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Air Flow Rate [LFM]
0 200 600 100 400 800
0.6
0.8 Heat Sink Height [in]
1.0
1.2
1.4
Figure 15. Thermal Resistance vs. Heatsink Height, SPGA Packages
49
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
E
200 6.4 5.8 5.1 4.5 4.1 3.7 3.4 3.1 2.8 11.2 400 4.3 3.8 3.4 3.0 2.8 2.6 2.4 2.2 2.0 7.7 600 3.4 3.1 2.7 2.4 2.2 2.0 1.9 1.8 1.7 6.3 800 2.8 2.6 2.3 2.1 1.9 1.8 1.6 1.6 1.5 5.4
Table 21. Thermal Resistances for PPGA Packages Heat Sink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None
JC
(C/Watt) 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 1.2 0 8.9 8.6 8.2 7.9 7.5 6.8 6.1 5.7 5.2 12.9
CA (C/Watt) vs. Laminar Airflow (linear ft/min)
100 7.8 7.3 6.8 6.3 5.8 5.1 4.5 4.1 3.7 12.2
NOTES: Heatsinks are omni directional pin aluminum alloy. Features were based on standard extrusion practices for a given height: Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Based thickness ranged from 79 to 200 mils Heatsink attach was 0.005" of thermal grease. Attach thickness of 0.002" will improve performance approximately 0.3C/Watt.
50
E
10 9 8 7 Theta ca [C/W] 6 5 4 3 2 1 0 0.2 0.4
PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY
Air Flow Rate [LFM]
0 200 600 100 400 800
0.6
0.8 Heat Sink Height [in]
1.0
1.2
1.4
Figure 16. Thermal Resistance vs. Heatsink Height, PPGA Packages
51

▲Up To Search▲

Price & Availability of PENTIUMPROCESSORWITHMMX

	To Download PENTIUMPROCESSORWITHMMX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .