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L24W02
Serial EEPROM
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DataShee
Data Sheet
Revision A
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S062A
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LinkSmart
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Revision history
Rev. No. A Approved date 2004/8/20 History Initial issue Remark (purpose) Preliminary
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All rights reserved. LinkSmart reserves the right to change its products and specification without prior notice. For the most up-to-date information, please visit our website at http://www.linksmart.com.tw or http://www.lstmc.com. All companies, brands, logos, pictures, product names and trademarks are the property of owner respective companies. LinkSmart Technology Co., Ltd. has been award ISO-9000 certification. All IC products are designed and manufactured in according with the highest quality standards and objectives. LinkSmart Technology Co., Ltd. B1, No. 216, Ta-Hsueh Road, Hsin-Chu City, Taiwan TEL: (886)-3-575 1188 FAX: (886)-3-575 1180 LinkSmart Microelectronics Technology Co., Ltd. 4F, A6 Standard Factory, Li Yuan Economic Development Park, Wu Xi City, China TEL: (86)-510-5160 232 FAX: (86)-510-5160 272 LinkSmart Microelectronics Technology Co., Ltd. (Sales Office) Room 2407, Nan-Shan Software Park, Nan-Shan District, ShenZhen City, China TEL: (86)-755-2658 1768 FAX: (86)-755-2658 1781 http://www.linksmart.com.tw http://www.lstmc.com
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Features Operating voltage: 3V~5.5V Low power consumption - Operation: 5mA max. - Standby: 5A max. Internal organization: - 2K: 256x8 2-wire Serial Interface Write cycle time: 5ms max. Automatic erase-before-write operation General Description The L24W02 is a 2K-bits serial read/write nonvolatile memory device using the CMOS floating gate process. Its 2,048 bits of memory are organized into 256 words and each word is 8 bits. The device is optimized for use in many industrial and commercial applications where low power and Block Diagram
I/O Control Logic HV Pump X D E C
Partial page write allowed 8-byte Page Write Mode Write operation with built-in timer Hardware controlled write protection 40-year data retention 1,000,000 (106)rewrite cycles per word Commercial temperature range (0C to +70C) 8-pin SOP/DIP/TSSOP package
low voltage operation are essential. Up to eight L24W02 devices may be connected to the same two-wire bus. The L24W02 is guaranteed for 1,000,000 (106) erase/write cycles and 40 years data retention.
Pin Configurations
A0 1 2 3 4 8 7 6 5 Vcc WP SCL SDA A1 A2
EEPROM Array Page Buf YDEC
SCL SDA
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WP Memory Control Logic
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L24W02 8PIN SOP/DIP/TSSOP
A0~A2 Vcc Vss
Address Counter
Sense AMP R/W Control
Pin Description Pin Name A0~A2 SDA SCL WP Vss Vcc
I/O I I/O I I I
Description Address inputs Serial data inputs/output Serial clock data input Write protect Negative power supply Positive power supply
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Absolute Maximum Ratings Operating Temperature (Commercial) .............................................................................. 0C to 70C Storage Temperature .................................................................................................. -50C to 125C Applied VCC Voltage with Respect to VSS .................................................................... -0.3V to 6.0V Applied Voltage on any Pin with Respect to VSS ....................................................... -0.3V to VCC+0.3V Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Test Conditions Vcc Conditions VCC Operating Voltage -- -- ICC1 Operating Current 5V Read at 100kHz ICC2 Operating Current 5V Write at 100kHz VIL Input Low Voltage -- -- VIH Input High Voltage -- -- VOL Output Low Voltage 3V IOL=2.1mA ILI Input Leakage Current 5V VIN=0 or VCC ILO Output Leakage Current 5V VOUT=0 or VCC .com or V ISTB1 Standby Current 5V VIN=0 CC ISTB2 Standby Current 3V VIN=0 or VCC CIN Input Capacitance (See Note) -- f=1MHz 25C COUT Output Capacitance (See Note) -- f=1MHz 25C Note: These parameters are periodically sampled but not 100% tested Symbol Parameter Min. 3 -- -- -1 0.7VCC -- -- -- -- -- -- -- Ta=0C to 70C Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. Unit
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5.5 V 2 mA 5 mA 0.3Vcc V Vcc+0.5 V 0.4 V 1 A 1 A 5 A 4 A 6 pF 8 pF
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A.C. Characteristics Symbol fSK tHIGH tLOW tR tF Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Ta=0C to 70C Remark -- -- -- Standard Mode* Min. Max. -- 100 4000 -- 4700 -- -- 1000 -- 300 -- -- -- -- -- 3500 -- Vcc=5V10% Min. -- 600 1200 -- -- 600 600 0 100 600 -- 1200 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- Unit kHz ns ns ns ns ns ns ns ns ns ns ns
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Note Note After this period the first tHD:STA START Condition Hold Time 4000 clock pulse is generated Only relevant for tSU:STA START Condition Setup Time repeated START 4000 condition tHD:DAT Data Input Hold Time -- 0 tSU:DAT Data Input Setup Time -- 200 tSU:STO STOP Condition Setup Time -- 4000 tAA Output Valid from Clock -- -- Time in which the bus must be free before a tBUF Bus Free Time 4700 new transmission can start .com Input Filter Time Constant tSP Noise suppression time -- (SDA and SCL Pins) tWR Write Cycle Time -- -- Notes: These parameters are periodically sampled but not 100% tested * The standard mode means VCC=3V to 5.5V For relative timing, refer to timing diagrams
100 5
-- --
50 5
ns ms
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Functional Description Serial clock (SCL) The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. Serial data (SDA) The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open- drain or open collector devices. A0, A1, A2 The A2,A1 and A0 pins are device address inputs that are hard wired for the L24W02.As many as eight 2K devices may be addressed on a single bus system (The device addressing is discussed in detail under the Device Ad- dressing section). Write protect (WP) The L24W02 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to the Vss. When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status At Vcc At Vss Protect Array Full Array (2K) Normal Read/Write Operations
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Memory organization L24W02, 2K Serial EEPROM Internally organized with 256 8-bit words, the 2K requires an 8-bit data word address for random word .com addressing. Device operations Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. Start condition A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). Stop condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
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SDA
Data allowed to change
SCL Start condition Stop condition
Device addressing The 2K EEPROM devices require an 8-bit device address word following a start condition to enable the
Address or acknowledge valid
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
chip for a read or write operation. The device address word consists of a mandatory one, zero sequence for the first four most significant bits (refer to diagram showing the Device Address). This is common to all EEPROM devices. The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must compare to their corresponding hard-wired input pins. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeeds the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.
1 0 1 0 A2 A1 A0 R/W
Device Address
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
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Write operations Byte write A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a micro- controller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write is completed (refer to Byte write timing). Page write The 2K EEPROM is capable of 8-byte page writes. A page write is initiated the same as byte write, but the micro controller does not sand a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the micro controller can transmit up to seven more data words. The EEPROM will respond with a zero after each data word received. The micro controller must terminate the page write sequence with a stop condition. The data word address lower three (2K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location (refer to Page write timing). Acknowledge polling Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W=0). If the device is still busy with the write cycle, then no ACK will .com be returned. If the cycle is completed, then the device will return the ACK and the master can then proceed with the next read or write command.
Send Write Command
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Send Stop Condition to lnitiate Write Cycle
Send Start
Send Cotroll Byte With R/W=0
(ACK=0)?
No
Yes Next Operation Acknowledge polling flow
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B y te w r i te t im in g D e v ic e a d d re s s SDA S S ta r t A2
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
W o r d a d d re s s
DATA P
A1 A0
R /W ACK ACK ACK
S to p
P a g e w r it e ti m in g W o r d a d d re s s DATA n DATA n+x P ACK ACK ACK ACK S to p
D e v ic e a d d r e s s SDA S S t a rt
DATA n+1
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Write protect The L24W02 can be used as a serial ROM when the WP pin is connected to Vcc. Programming will be inhibited and the entire memory will be writing protected. Read operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. Current address read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The addresses roll over during read from the last byte of the last memory page to the first byte of the first page. The addresses roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The micro controller does not respond with an input zero but generates a following stop condition (refer to Current read timing). Random read A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The micro controller must then generate another start condition. The micro controller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The micro controller does not respond with a zero but does generate a following stop condition (refer to Random read timing).
C u rre n t re ad tim in g
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SDA S S ta rt
D e vice a d d re ss
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S to p P ACK No ACK
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A2
A1 A0
R a n d o m re a d tim in g D e vice a d d re ss SDA S S ta rt A2 A1 A0 ACK W o rd a dd re ss S ACK S ta rt ACK DATA S to p P No ACK
D e vice a d dre ss
Sequential read Sequential reads are initiated by either a current address read or a random address read. After the micro controller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the micro controller does not respond with a zero but generates a following stop condition.
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S eq u e n tia l re a d tim in g D e vice a d d re ss SDA S S ta rt ACK
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
DATA n
D ATA n+1
DATA n+x S to p P
ACK
No ACK
T im in g D ia g ra m s
tF tLO W SCL t S U :S T A SDA tS P SDA OUT tA A V a lid .com V a lid tB U F t H D :S T A t H D :D A T t S U :D A T t S U :S T O tR t H IG H
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SCL SDA
8 th b it W o rd n ACK
tW R S top C o n d itio n S ta rt C o n dition
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Package Information 8-pin DIP (300mil) Outline Dimensions
A
8 5 4
B
1
H C D E F G
I
Symbol A B C D E F G H I
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Min. 355 240 125 125 16 50 295 335 0
Dimensions in mil Nom .com 100 -
Max 375 260 135 145 20 70 315 375 15
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
8-pin SOP (150mil) Outline Dimensions
8 A 1
5 4
C
C G D E F H
Symbol A B C C D E F G H
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Dimensions in mil Min. Nom 228 149 14 .com 189 53 50 4 22 4 0 -
Max 244 157 20 197 69 10 28 12 10
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Product Tape and Reel Specifications Reel Dimensions
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SOP 8PIN Symbol A B C D T1 T2
.com Description Reel Outer Diameter Reel Inner Diameter
Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness
Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.15 12.8+0.3 -0.2 12.80.2
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Carrier Tape Dimensions
D
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
P0
P1
t
E
F W C B0
D 1
P A0 K 0
SOP 8PIN Symbol W
Description Carrier Tape Width Cavity Pitch .com Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width
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P E F D D1 P0 P1 A0 B0 K0 t C
Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3
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Part Number Information
L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
L
24
W
02
C
J
LinkSmart
EEPROM Based Products
Voltage
Density 02 : 2K 04 : 4K 08 : 8K 16 : 16K 32 : 32K 64 : 64K
Version A : Version A C : Version C
Package K : PDIP 8L J : SOP 8L
24 : Serial EEPROM C : 4.5~5.5V W : 2.7~5.5V M : 2.2~5.5V
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.com Application Serial EEPROM are ideal non-volatile cost effective memory solutions in applications that require: * Low voltage and current for handheld battery applications as in a keyless entry transmitter * Small footprint and board space as in cellular phone applications * BYTE level ERASE, WRITE, and READ of data as in a TV tuner * Multiple non-volatile functions in the same application such as a VCR * Low availability of microcontroller I/O lines
The typical functions that serial EEPROM are utilized for are: * Memory storage of channel selectors or analog controls (volume, tone, etc.) in consumer electronics products e.g. DVD, VCD, CD... * Electronic real time event or maintenance logs such as page counting in office automation products. Also, configuration or DIP switch storage in office automation products * Power down storage and retrieval of events such as fault detection or error diagnostics in automotive products * Last number redial storage and speed dial number storage in telecom products * User in-circuit reprogrammable looks up tables such as bar code readers, point-of-sale terminals, environmental controls and other industrial products. Other application examples include: * Data storage from a learn function as in a remote control transmitter * Reprogrammable calibration data for test equipment or analog interface products * ID number storage for security or remote access for electronic keys and entry databases
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L24W02 2K 2-Wire (256x8) 3V~5.5V CMOS Serial EEPROM
PRELIMINARY A
Serial EEPROM Selection Guide Density Page Write Write Cycle P/N Endurance (Int. Organization) Mode Time (max) L24C02 2K-bits (256x8) 8-bytes 5ms 106 L24W02 L24M04 L24W04 L24M08 L24W08 L24W16 L24W32 L24W64 2K-bits (256x8) 4K-bits (512x8) 4K-bits (512x8) 8K-bits (1,024x8) 8K-bits (1,024x8) 16K-bits (2,048x8) 32K-bits (4,096x8) 64K-bits (8,192x6) 8-bytes 16-bytes 16-bytes 16-bytes 16-bytes 32-bytes 32-bytes 32-bytes 5ms 5ms 5ms 5ms 5ms 10ms 10ms 10ms 10
6 6 6 6 6 5 5 5
Operating Voltage 4.5V~5.5V 3V~5.5V 2.2V~5.5V 3V~5.5V 2.2V~5.5V 3V~5.5V 2.7V~5.5V 2.7V~5.5V 2.7V~5.5V
Package SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP SOP/DIP/TSSOP
10
10
10 10
10 10 10
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