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 Preliminary Information
AMD-K6
Processor
Data Sheet
(R)
Preliminary Information
(c) 1998 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD's written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products, except as provided in AMD's Terms and Conditions of Sale for such products.
Trademarks AMD, the AMD logo, and combinations thereof, K86, AMD-K5, and the AMD-K6 logo are trademarks, and RISC86 and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks, and Windows NT is a trademark of Microsoft Corporation. Netware is a registered trademark of Novell, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 "IEEE Standard Test Access Port and Boundary-Scan Architecture," Copyright (c) 1990 by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part One
AMD-K6(R) Processor Family
1 2
3
AMD-K6(R) Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AMD-K6(R) Processor Microarchitecture Overview . . . . . . . . . 7 Enhanced RISC86(R) Microarchitecture . . . . . . . . . . . . . . . . . . . 8 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 11 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4
2.5 2.6 2.7
3
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Register Data Types . . . . . . . . . . . . . . . . . . . . . 28 MMXTM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37
Contents
iii
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
3.2
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 39 Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Instructions Supported by the AMD-K6 Processor . . . . . . . . 49
4 5
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32 5.33 5.34 5.35 5.36 5.37 5.38 A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 79 A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 81 AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 84 BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 89 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 90 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . . 94 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . . 95 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . . 96 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . . 98 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 100 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 106 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
iv
Contents
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
5.39 5.40 5.41 5.42 5.43 5.44 5.45 5.46 5.47 5.48 5.49 5.50 5.51 5.52
RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 111 SMIACT# (System Management Interrupt Active) . . . . . . 112 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 116
6
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 6.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 123 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 126 Misaligned Single-Transfer Memory Read and Write . . . . . 128 Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 130 Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 135 Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 136 Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 136 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 140 AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 142 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 146 AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Locked Operation with BOFF# Intervention . . . . . . . . . . . . 154 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3
6.4
6.5
Contents
v
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
6.6
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Basic Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Stop Grant and Stop Clock States . . . . . . . . . . . . . . . . . . . . . 161 INIT-Initiated Transition from Protected Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
7
Power-on Configuration and Initialization . . . . . . . . . . . . . . 167
7.1 Signals Sampled During the Falling Transition of RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 168 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 170
7.2 7.3
7.4
8
Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.1 8.2 8.3 8.4 8.5 8.6 8.7 MESI States in the Data Cache . . . . . . . . . . . . . . . . . . . . . . . 172 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Cache Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Write to a Cacheable Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Write to a Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Write Allocate Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Descriptions of the Logic Mechanisms and Conditions . . . . 180 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 WBINVD and INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Cache-Line Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Cache Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Writethrough vs. Writeback Coherency States . . . . . . . . . . 187 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 187
8.8 8.9 8.10
8.11 8.12
9
Floating-Point and Multimedia Execution Units . . . . . . . . . 189
9.1 Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 189 Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . 189 External Logic Support of Floating-Point Exceptions . . . . . 189
vi
Contents
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
9.2 9.3
Multimedia Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Floating-Point and MMX Instruction Compatibility . . . . . . 191 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 FERR# and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
10
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 193
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SMM Operating Mode and Default Register Values . . . . . 193 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 I/O Trap Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 202
11
Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
11.1 11.2 11.3 Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 205 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . 212 L1 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.4 11.5
12
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
12.1 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Enter Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Exit Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Enter Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Exit Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Enter Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . 226 Exit Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . 226 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Enter Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Exit Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
12.2
12.3
12.4
Contents
vii
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
13
Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
13.1 13.2 13.3 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 230 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . 231
14
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.1 14.2 14.3 14.4 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
15
I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.1 15.2 15.3 15.4 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 I/O Buffer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 I/O Model Application Note . . . . . . . . . . . . . . . . . . . . . . . . . 239 I/O Buffer AC and DC Characteristics . . . . . . . . . . . . . . . . . 239
16
Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 241
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 241 Clock Switching Characteristics for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Clock Switching Characteristics for 60-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 243 Output Delay Timings for 66-MHz Bus Operation . . . . . . . 244 Input Setup and Hold Timings for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Output Delay Timings for 60-MHz Bus Operation . . . . . . . 248 Input Setup and Hold Timings for 60-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 252
17
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
17.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 259 Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 262 Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . . 262 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Airflow Management in a System Design . . . . . . . . . . . . . . . 264
17.2
18 19 20
Pin Description Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
20.1 321-Pin Staggered CPGA Package Specification . . . . . . . . 271
21 viii
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Contents
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Part Two
AMD-K6 Processor Model 7
22 23 24
275
AMD-K6 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
24.1 24.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . 281 Instructions Supported by the AMD-K6 Processor . . . . . . . 283
25 26
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
26.1 26.2 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . . 287
27 28
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Power-on Configuration and Initialization . . . . . . . . . . . . . . 291
28.1 State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 291 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
29 30 31 32
Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Floating-Point and Multimedia Execution Units . . . . . . . . . 295 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 297 Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
32.1 32.2 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 299 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
33 34 35
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
34.1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
35.1 35.2 35.3 35.4 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
36 Contents
I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 ix
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
37 38
Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 311 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
38.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 313
39 40 41 42
Pin Description Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
x
Contents
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
List of Figures
Part One
AMD-K6 Processor Family
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34.
3
AMD-K6 Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 11 Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AMD-K6 Processor Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . 14 AMD-K6 Processor Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 22 Integer Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Packed Decimal Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Precision Real Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MMX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MMX Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 36 Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 37 Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . . . . 38 Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . . 39 Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 40 Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of Figures
xi
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71.
4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 44 Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 44 Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 46 System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Misaligned Single-Transfer Memory Read and Write . . . . . . 129 Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 131 Burst Writeback due to Cache-Line Replacement . . . . . . . . . 133 Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 137 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 139 HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 141 AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 143 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 147 AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 155 Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 157 Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 159 Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 162 Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 163 INIT-Initiated Transition from Protected Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 179 Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 180 External Logic for Supporting Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
xii
List of Figures
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101.
SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 218 Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 219 Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 228 Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 230 K6STD Pulldown V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 K6STD Pullup V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 255 Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 256 TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Power Consumption vs. Thermal Resistance . . . . . . . . . . . . . 260 Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 261 Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 262 Voltage Regulator Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Airflow for a Heatsink with Fan . . . . . . . . . . . . . . . . . . . . . . . . 263 Airflow Path in a Dual-fan System . . . . . . . . . . . . . . . . . . . . . . 264 Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 265 AMD-K6 Processor Top-Side View . . . . . . . . . . . . . . . . . . . . . . 267 AMD-K6 Processor Pin-Side View . . . . . . . . . . . . . . . . . . . . . . 268 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 272
Part Two
AMD-K6 Processor Model 7
Figure 102. Figure 103. Figure 104. Figure 105.
275
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 282 SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 283 AMD-K6 Processor Model 7 Top-Side View. . . . . . . . . . . . . . . 315 AMD-K6 Processor Model 7 Pin-Side View . . . . . . . . . . . . . . . 316
List of Figures
xiii
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
xiv
List of Figures
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
List of Tables
Part One
AMD-K6 Processor Family
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36.
3
Execution Latency and Throughput of Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose Register Dword, Word, and Byte Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 39 Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 47 Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 48 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MMX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 118 Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Bus-Cycle Order During Misaligned Transfers . . . . . . . . . . . . 128 A[4:3] Address-Generation Sequence During Bursts . . . . . . . 130 Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 135 Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 156 Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . 158 Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 168 Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Data Cache States for Read and Write Accesses . . . . . . . . . . 182 Cache States for Inquiries, Snoops, Invalidation, and Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Snoop Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 195 SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 200
List of Tables
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Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58.
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 209 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 210 Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 221 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . 235 A[20:3], ADS#, HITM#, and W/R# Strength Selection . . . . . . 237 CLK Switching Characteristics for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 CLK Switching Characteristics for 60-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 244 Input Setup and Hold Timings for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Output Delay Timings for 60-MHz Bus Operation . . . . . . . . . 248 Input Setup and Hold Timings for 60-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 RESET and Configuration Signals (60-MHz and 66-MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 253 Test Signal Timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Package Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . 259 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 271 Valid Ordering Part Number Combinations . . . . . . . . . . . . . . 273
Part Two
AMD-K6 Processor Model 7
Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72.
275
Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . 282 Extended Feature Enable Register (EFER) Definition . . . . . 282 SYSCALL/SYSRET Target Address Register (STAR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 291 Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 300 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . 307 Package Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . 313 Valid Ordering Part Number Combinations . . . . . . . . . . . . . . 321
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AMD-K6(R) Processor Data Sheet
Revision History
Date June 1997 June 1997 June 1997 June 1997 Sept 1997 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 March 1998 Rev E E E E F G G G G G G G G G G G H Description Replaced overbar with # to identify active-Low signals. Corrected description in "Write Allocate" on page 177. Revised latency and throughput information in Table 1, "Execution Latency and Throughput of Execution Units," on page 18. Updated Figure 79, "Suggested Component Placement," on page 230 of Chapter 13, "Power and Grounding". Unreleased version. Divided book into Part 1 and Part 2. Part 1 provides information about the AMD-K6(R) processor family (Model 6 and Model 7) and Part 2 provides information specific to the AMD-K6 processor Model 7 (0.25-micron process technology). Added Figure 17, "MMXTM Data Types," on page 30 in Chapter 3, "Software Environment". Qualified conditions under which Write Allocate occurs in the memory area between 640 Kbytes and 1 Mbyte in "Write Allocate Limit" on page 178 of Chapter 8, "Cache Organization". Changed power dissipation specifications for Stop Grant State and Stop Clock State for 166MHz, 200MHz, and 233MHz components in Table 45, "Typical and Maximum Power Dissipation," on page 235, and Table 56, "Package Thermal Specification," on page 259. Removed all references to Write KEN# Control Register (WKCR) from Chapter 3, "Software Environment", Chapter 5, "Signal Descriptions", and Chapter 8, "Cache Organization". Added top-side view pin description diagram. See Figure 99, "AMD-K6(R) Processor Top-Side View," on page 267. Added voltage detection pin to diagram in Chapter 4, "Logic Symbol Diagram". Modified flatness specification (symbol f) in Table 57, "321-Pin Staggered CPGA Package Specification," on page 271. Corrected Figure 44, "Bus State Machine Diagram," on page 123 in Chapter 6, "Bus Cycles" to accurately show the direct transition from the Pipeline Data state to the Data-NA# Requested state. Corrected list of internal resources tested during BIST in Chapter 11, "Test and Debug" on page 203. Revised Figure 92, "Power Consumption vs. Thermal Resistance," on page 260 in Chapter 17, "Thermal Design". Revised signal description of VCC2H/L# on page 287 in Chapter 26, "Signal Descriptions".
Revision History
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Revision History
Preliminary Information
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AMD-K6(R) Processor Data Sheet
About This Data Sheet
The AMD-K6(R) Processor Data Sheet supports the Model 6 and Model 7 versions of the AMD-K6 processor family. Model 6 refers to the AMD-K6 manufactured in the 0.35-micron process technology and Model 7 refers to the AMD-K6 manufactured in the 0.25-micron process technology. The data sheet is divided into two parts. Part One (chapters 1-21) contains information that pertains to the entire AMD-K6 desktop family and information specific to the Model 6. Part Two (chapters 22-42) contains information regarding new specifications and differences that pertain only to Model 7 as compared to Model 6.
About This Data Sheet
1
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
2
About This Data Sheet
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Part One
AMD-K6 Processor Family
The AMD-K6(R) Processor Data Sheet supports the Model 6 and Model 7 versions of the AMD-K6 processor family. Model 6 refers to the AMD-K6 manufactured with 0.35-micron process technology and Model 7 refers to the AMD-K6 manufactured with 0.25-micron process technology. Part One (chapters 1-21) contains information that pertains to the entire AMD-K6 desktop family and information specific to Model 6.
(R)
Part One
AMD-K6(R) Processor Family
3
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
4
AMD-K6(R) Processor Family
Part One
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
1
s
AMD-K6(R) Processor
Advanced 6-Issue RISC86(R) Superscalar Microarchitecture x Seven parallel specialized execution units x Multiple sophisticated x86-to-RISC86 instruction decoders x Advanced two-level branch prediction x Speculative execution x Out-of-order execution x Register renaming and data forwarding x Issues up to six RISC86 instructions per clock Large On-Chip Split 64-Kbyte Level-One (L1) Cache x 32-Kbyte instruction cache with additional predecode cache x 32-Kbyte writeback dual-ported data cache x MESI protocol support High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit High-Performance Industry-Standard MMXTM Instructions 321-Pin Ceramic Pin Grid Array (CPGA) Package (Socket 7 Compatible) Industry-Standard System Management Mode (SMM) IEEE 1149.1 Boundary Scan Full x86 Binary Software Compatibility
s
s s s s s s
As the next generation in the AMD K86TM family of x86 processors, the innovative AMD-K6 processor brings industry-leading performance to PC systems running the extensive installed base of x86 software. In addition, its socket 7 compatible, 321-pin Ceramic Pin Grid Array (CPGA) package enables the AMD-K6 to reduce time-to-market by leveraging today's cost-effective infrastructure to deliver a superior price/performance PC solution. To provide state-of-the-art performance, the AMD-K6 processor incorporates the innovative and efficient RISC86 microarchitecture, a large 64-Kbyte level-one cache (32-Kbyte dual-ported data cache, 32-Kbyte instruction cache with predecode data), a powerful IEEE 754-compatible and 854-compatible floating-point execution unit, and a high-performance multimedia execution unit for executing industry-standard MMX instructions. These features have been combined to deliver industry leadership in 16-bit and 32-bit performance, providing exceptional performance for both Windows(R) 95 and Windows NTTM software bases.
Chapter 1
AMD-K6(R) Processor
5
Preliminary Information AMD-K6(R) Processor Data Sheet
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The AMD-K6 processor's RISC86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. Advanced design techniques implemented in the AMD-K6 include multiple x86 instruction decode, single-clock internal RISC operations, seven execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. In addition, the processor supports the industry's most advanced branch prediction logic by implementing an 8192-entry branch history table, the industry's only branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. These design techniques enable the AMD-K6 processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. The AMD-K6 processor is fully x86 binary code compatible. AMD's extensive experience through four generations of x86 processors has been carefully integrated into the AMD-K6 to provide complete compatibility with Windows 95, Windows 3.x, Windows NT, DOS, OS/2, Unix, Solaris, NetWare(R) , Vines, and other leading x86 operating systems and applications. The AMD-K6 processor is Socket 7 compatible, allowing the processor to be quickly and easily integrated into a mature and cost-effective industry-standard infrastructure of motherboards, chipsets, power supplies, and thermal designs. AMD has designed, manufactured, and delivered over 50 million Microsoft (R) Windows-compatible processors in the last five years alone. The AMD-K6 processor is the next generation in this long line of processors. With its combination of state-of-the-art features, industry-leading performance, high-performance multimedia engine, full x86 compatibility, and low-cost infrastructure, the AMD-K6 is the superior choice for mainstream personal computers.
6
AMD-K6(R) Processor
Chapter 1
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
2
2.1
Internal Architecture
Introduction
The AMD-K6 processor implements advanced design techniques k n ow n a s t h e R I S C8 6 m i c ro a rch it e c t u re . The R I S C8 6 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. This chapter describes the techniques used and the functional elements of the RISC86 microarchitecture.
2.2
AMD-K6(R) Processor Microarchitecture Overview
When discussing processor design, it is important to understand t h e t e r m s a r ch i t e c t u re , m i c r o a r ch i t e c t u re , a nd d e s i g n implementation. The term architecture refers to the instruction set and features of a processor that are visible to software p rog ra m s r u n n ing o n t h e p ro c e s so r. The a rchi t ec t ure de termines w hat software the processor can run. The architecture of the AMD-K6 processor is the industry-standard x86 instruction set. The term microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. The AMD-K6 is based on a sophisticated RISC core known as the Enhanced RISC86 microarchitecture. The Enhanced RISC86 microarchitecture is an advanced, second-order decoupled decode/execution design approach that enables industry-leading performance for x86-based software. The term design implementation refers to the actual logic and circuit designs from which the processor is created according to the microarchitecture specifications.
Chapter 2
Internal Architecture
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Preliminary Information AMD-K6(R) Processor Data Sheet
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Enhanced RISC86(R) Microarchitecture
Th e E n h anced RISC86 mi croarchi tecture defi nes t h e characteristics of the AMD-K6. The innovative RISC86 microarchitecture approach implements the x86 instruction set by internally translating x86 instructions into RISC86 operations. These RISC86 operations were specially designed to include direct support for the x86 instruction set while observing the RISC performance principles of fixed length encoding, regularized instruction fields, and a large register set. The Enhanced RISC86 microarchitecture used in the AMD-K6 enables higher processor core performance and promotes straightforward extensibility in future designs. Instead of directly executing complex x86 instructions, which have lengths of 1 to 15 bytes, the AMD-K6 processor executes the simpler and easier fixed-length RISC86 opcodes, while maintaining the instruction coding efficiencies found in x86 programs. Th e A MD -K 6 p ro c e s so r c o n t a i n s p ara l l el d e c o d e rs , a centralized RISC86 operation scheduler, and seven execution units that support superscalar operation--multiple decode, execution, and retirement--of x86 instructions. These elements are packed into an aggressive and highly efficient six-stage pipeline. Decoders. Decoding of the x86 instructions begins when the on-chip instruction cache is filled. Predecode logic determines the length of an x86 instruction on a byte-by-byte basis. This p re d e c o d e i n fo r m a t i o n i s s t o re d , a l o n g w i t h t h e x 8 6 instructions, in the instruction cache, to be used later by the decoders. The decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into RISC86 operations. Note: In this chapter, "clock" refers to a processor clock. The AMD-K6 processor categorizes x86 instructions into three types of decodes--short, long and vector. The decoders process either two short, one long, or one vector decode at a time. The three types of decodes have the following characteristics: s Short decodes--x86 instructions less than or equal to seven bytes in length s Long decodes--x86 instructions less than or equal to 11 bytes in length s Vector decodes--complex x86 instructions
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Internal Architecture
Chapter 2
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Short and long decodes are processed completely within the decoders. Vector decodes are started by the decoders and then completed by fetched sequences from an on-chip ROM. After decoding, the RISC86 operations are delivered to the scheduler for dispatching to the executions units. Scheduler/Instruction Control Unit. The centraliz ed scheduler or buffer is managed by the Instruction Control Unit (ICU). The ICU buffers and manages up to 24 RISC86 operations at a time. This equals from 6 to 12 x86 instructions. This buffer size (24) is perfectly matched to the processor's six-stage RISC86 pipeline and seven parallel execution units. The scheduler accepts as many as four RISC86 operations at a time from the decoders. The ICU is capable of simultaneously issuing up to six RISC86 operations at a time to the execution units. This consists of the following types of operations:
s s s s s s
Memory load operation Memory store operation Complex integer or MMX register operation Simple integer register operation Floating-point register operation Branch condition evaluation
Registers. The scheduler uses 48 physical registers that are contained within the RISC86 microarchitecture when managing the 24 RISC86 operations. The 48 physical registers are located in a general register file and are grouped as 24 general registers, plus 24 renaming registers. The 24 general registers consist of 16 scratch registers and eight registers that correspond to the x86 general purpose registers--EAX, EBX, ECX, EDX, EBP, ESP, ESI and EDI. Branch Logic. The AMD-K6 processor is designed with highly sophisticated dynamic branch logic consisting of the following:
s s s
Branch history/Prediction table Branch target cache Return address stack
The AMD-K6 implements a two-level branch prediction scheme based on an 8192-entry branch history table. The branch history table stores prediction information that is used for predicting conditional branches. Because the branch history table does not Chapter 2 Internal Architecture 9
Preliminary Information AMD-K6(R) Processor Data Sheet
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store predicted target addresses, special address ALUs calculate target addresses on-the-fly during instruction decode. Th e b ra n ch t a rg e t c a ch e a u g m e n t s p re d i c t e d b ra n ch performance by avoiding a one clock cache-fetch penalty. This specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. The return address stack is a unique device specifically designed for optimizing CALL and RETURN pairs. In summary, the AMD-K6 uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. AMD-K6(R) Processor Block Diagram. As shown in Figure 1 on page 11, the high-performance, out-of-order execution engine of the AMD-K6 processor is mated to a split level-one 64-Kbyte writeback cache with 32 Kbytes of instruction cache and 32 Kbytes of data cache. The instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. The ICU issues and retires RISC86 operations contained in the scheduler. The system bus interface is an industry-standard 64-bit Pentium(R) processor demultiplexed bus. The AMD-K6 processor combines the latest in processor microarchitecture to provide the highest x86 performance for t od ay's p e rs ona l c o m p u t e rs. The A M D -K 6 of f e rs t ru e sixth-generation performance and full x86 binary software compatibility.
10
Internal Architecture
Chapter 2
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
Predecode Logic
Level-One Instruction Cache (32 KByte + Predecode) 16-Byte Fetch Level-One Cache Controller Dual Instruction Decoders x86 to RISC86 Four RISC86 Decode Scheduler Buffer (24 RISC86)
64-Entry ITLB Branch Logic (8192-Entry BHT) (16-Entry BTC) (16-Entry RAS)
Socket 7 Bus Interface
Out-of-Order Execution Engine Six RISC86 Operation Issue
(R)
Instruction Control Unit
Load Unit
Store Unit
Integer X (Register) Unit
Multimedia Unit
Integer Y (Register) Unit
Floating-Point Unit
Branch (Resolving) Unit
Store Queue
Level-One Dual-Port Data Cache (32 KByte)
128-Entry DTLB
Figure 1. AMD-K6(R) Processor Block Diagram
2.3
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the AMD-K6 processor is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The cache line size is 32 bytes and lines are prefetched from main memory using an efficient pipelined burst transaction. As the instruction cache is filled, each instruction byte is analyzed for instruction boundaries using predecoding logic. Predecoding annotates each instruction byte with information that later enables the decoders to efficiently decode multiple instructions simultaneously.
Cache
The processor cache design takes advantage of a sectored organization (see Figure 2 on page 12). Each sector consists of 64 bytes configured as two 32-byte cache lines. The two cache lines of a sector share a common tag but have separate pairs of MESI (Modified, Exclusive, Shared, Invalid) bits that track the state of each cache line.
Chapter 2
Internal Architecture
11
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
Tag Address
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits Cache Line 2 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization Two forms of cache misses and associated cache fills can take place--a sector replacement and a cache line replacement. In the case of a sector replacement, the miss is due to a tag mismatch, in which case the required cache line is filled from external memory, and the cache line within the sector that was not required is marked as invalid. In the case of a cache line replacement, the address matches the tag, but the requested cache line is marked as invalid. The required cache line is filled from external memory, and the cache line within the sector that is not required remains in the same cache state. Prefetching The AMD-K6 processor performs cache prefetching for sector replacements only--as opposed to cache line replacements. This cache prefetching results in the filling of the required cache line first, and a prefetch of the second cache line. Furthermore, the prefetch of the cache line that is not required is initiated only in the forward direction--that is, only if the requested cache line is the first cache line within the sector. From the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. Decoding x86 instructions is particularly difficult because the instructions are variable-length and can be from 1 to 15 bytes long. Predecode logic supplies the predecode bits that are associated with each instruction byte. The predecode bits indicate the number of bytes to the start of the next x86 instruction. The predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in Figure 2 on page 12. The predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding.
Predecode Bits
12
Internal Architecture
Chapter 2
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
2.4
Instruction Fetch and Decode
The processor can fetch up to 16 bytes per clock out of the instruction cache or branch target cache. The fetched information is placed into a 16-byte instruction buffer that feeds directly into the decoders (see Figure 3). Fetching can occur along a single execution stream with up to seven outstanding branches taken. The instruction fetch logic is capable of retrieving any 16 contiguous bytes of information within a 32-byte boundary. There is no additional penalty when the 16 bytes of instructions lie across a cache line boundary. The instruction bytes are loaded into the instruction buffer as they are consumed by the decoders. Although instructions can be consumed with byte g ra nu l a r i t y, t h e i n s t r u c t i o n b u f f e r i s m a n a g e d o n a memory-aligned word (2 bytes) organization. Therefore, instructions are loaded and replaced with word granularity. When a control transfer occurs--such as a JMP instruction-- the entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes.
16 Bytes 32-Kbyte Level-One Instruction Cache 16 Bytes Branch-Target Cache 16 x 16 Bytes
Instruction Fetch
2:1
Branch Target Address Adders Return Address Stack 16 x 16 Bytes Fetch Unit 16 Instruction Bytes plus 16 Sets of Predecode Bits
Instruction Buffer
Figure 3. The Instruction Buffer Chapter 2 Internal Architecture 13
Preliminary Information AMD-K6(R) Processor Data Sheet
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Instruction Decode
The AMD-K6 processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates RISC86 operations from these x86 instructions. RISC86 operations are fixed-format internal instructions. Most RISC86 operations execute in a single clock. RISC86 operations are combined to perform every function of the x86 instruction set. Some x86 instructions are decoded into as few as zero RISC86 opcodes -- for instance a NOP -- or one RISC86 operation -- a register-to-register add. More complex x86 instructions are decoded into several RISC86 operations.
Instruction Buffer
Short Decoder #1 Short Decoder #2
Long Decoder On-Chip ROM
Vector Decoder
RISC86(R) Sequencer
Vector Address
4 RISC86 Operations
Figure 4. AMD-K6(R) Processor Decode Logic
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AMD-K6(R) Processor Data Sheet
The AMD-K6 processor uses a combination of decoders to convert x86 instructions into RISC86 operations. The hardware consists of three sets of decoders--two parallel short decoders, one long decoder, and one vectoring decoder. The parallel short decoders translate the most commonly-used x86 instructions ( moves, shifts, branches, ALU, MMX, FPU) into zero, one, or two RISC86 operations each. The short decoders only operate on x86 instructions that are up to seven bytes long. In addition, they are designed to decode up to two x86 instructions per clock. The commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long, and semi-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. The long decoder only performs one decode per clock and generates up to four RISC86 operations. All other translations (complex instructions, serializing conditions, interrupts and exceptions, etc.) are handled by a combination of the vector decoder and RISC86 operation sequences fetched from an on-chip ROM. For complex operations, the vector decoder logic provides the first set of RISC86 operations and a vector (initial ROM address) to a sequence of further RISC86 operations. The same types of RISC86 operations are fetched from the ROM as those that are generated by the hardware decoders. Note: Although all three sets of decoders are simultaneously fed a copy of the instruction buffer contents, only one of the three types of decoders is used during any one decode clock. The decoders or the RISC86 sequencer always generate a group of four RISC86 operations. For decodes that cannot fill the entire group with four RISC86 operations, RISC86 NOP operations are placed in the empty locations of the grouping. For example, a long-decoded x86 instruction that converts to only three RISC86 operations is padded with a single RISC86 NOP operation and then passed to the scheduler. Up to six groups or 24 RISC86 operations can be placed in the scheduler at a time. All of the common, and a few of the uncommon, floating-point instructions (also known as ESC instructions) are hardware decoded as short decodes. This decode generates a RISC86 floating-point operation and, optionally, an associated floating-point load or store operation. Floating-point or ESC instruction decode is only allowed in the first short decoder, but non-ESC instructions, excluding MMX instructions, can be Chapter 2 Internal Architecture 15
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decoded simultaneously by the second short decoder along with an ESC instruction decode in the first short decoder. All of the MMX instructions, with the exception of the EMMS instruction, are hardware decoded as short decodes. The MMX instruction decode generates a RISC86 MMX operation and, optionally, an associated MMX load or store operation. MMX instruction decode is only allowed in the first short decoder. However, instructions other than MMX and ESC instructions can be decoded simultaneously by the second short decoder along with an MMX instruction decode in the first short decoder.
2.5
Centralized Scheduler
The scheduler is the heart of the AMD-K6 processor (see Figure 5 on page 17). It contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple RISC86 operations, and speculative execution. The scheduler's buffer can hold up to 24 RISC86 operations. This equates to a maximum of 12 x86 instructions. When possible, the scheduler can simultaneously issue a RISC86 operation to any available execution unit (store, load, branch, integer, integer/multimedia, or floating-point). In total, the scheduler can issue up to six and retire up to four RISC86 operations per clock. The main advantage of the scheduler and its operation buffer is the ability to examine an x86 instruction window equal to 12 x86 instructions at one time. This advantage is due to the fact that the scheduler operates on the RISC86 operations in parallel and allows the AMD-K6 processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. Although the scheduler can issue RISC86 operations for out-of-order execution, it always retires x86 instructions in order.
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From Decode Logic RISC86 #0 RISC86 #1 RISC86 #2 RISC86 #3
Centralized RISC86(R) Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure 5. AMD-K6(R) Processor Scheduler
2.6
Execution Units
The AMD-K6 processor contains seven execution units--store, load, integer X, integer Y, multimedia, floating-point, and branch condition. Each unit is independent and capable of handling the RISC86 operations. Table 1 on page 18 details the execution units, functions performed within these units, operation latency, and operation throughput. The store and load execution units are two-staged pipelined designs. The store unit performs data writes and register calculation for LEA/PUSH. Data memory and register writes from stores are available after one clock. The load unit performs data memory reads. Data is available from the load unit after two clocks. The I nte ger X executio n unit can operat e on a ll AL U operations, multiplies, divides (signed and unsigned), shifts, and rotates.
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The multimedia unit shares pipeline control with the Integer X unit and executes all MMX instructions. The Integer Y execution unit can operate on the basic word and doubleword ALU operations -- ADD, AND, CMP, OR, SUB, XOR, zero-extend and sign-extend operands. The branch condition unit is separate from the branch prediction logic in that it resolves conditional branches such as JCC and LOOP after the branch condition has been evaluated. Table 1. Execution Latency and Throughput of Execution Units
Function LEA/PUSH, Address Memory Store Memory Loads Integer ALU Integer X Integer Multiply Integer Shift MMX ALU Multimedia Integer Y Branch FPU MMX Shifts, Packs, Unpack MMX Multiply Basic ALU (16- & 32-bit operands) Resolves Branch Conditions FADD, FSUB, FMUL Latency Throughput 1 1 2 1 2-3 1 1 1 1-2 1 1 2 1 1 1 1 2-3 1 1 1 1-2 1 1 2
Execution Unit Store Load
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2.7
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the AMD-K6 processor. Branches in x86 code fit into two categories -- unconditional branches, which always change program flow (that is, the branches are always taken) and conditional branches, which may or may not divert program flow (that is, the branches are taken or not-taken). When a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. Typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. The AMD-K6 branch logic has been designed to handle this type of program behavior and its negative effects on instruction execution, such as stalls due to delayed instruction fetching and the draining of the processor pipeline. The branch logic contains an 8192-entry branch history table, a 16-entry by 16-byte branch target cache, a 16-entry return address stack, and a branch execution unit.
Branch History Table
The AMD-K6 processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. However, c o n d i t i o n a l b ra n che s re q u i re t h e u se o f t h e dy n a m i c branch-prediction mechanism built into the AMD-K6. A two-level adaptive history algorithm is implemented in an 8192-entry branch history table. This table stores executed branch information, predicts individual branches, and predicts the behavior of groups of branches. To accommodate the large branch history table, the AMD-K6 processor does not store predicted target addresses. Instead, the branch target addresses are calculated on-the-fly using ALUs during the decode stage. The adders calculate all possible target addresses before the instructions are fully decoded and the processor chooses which addresses are valid. To avoid a one clock cache-fetch penalty when a branch is predicted taken, a built-in branch target cache supplies the first 16 bytes of instructions directly to the instruction buffer (assuming the target address hits this cache). (See Figure 3 on page 13.) The branch target cache is organized as 16 entries of 16 bytes. In total, the branch prediction logic achieves branch prediction rates greater than 95%. Internal Architecture 19
Branch Target Cache
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Return Address Stack
The return address stack is a special device designed to optimize CALL and RET pairs. Software is typically compiled with subroutines that are frequently called from various places in a program. This is usually done to save space. Entry into the subroutine occurs with the execution of a CALL instruction. At that time, the processor pushes the address of the next instruction in memory following the CALL instruction onto the stack (allocated space in memory). When the processor encounters a RET instruction (within or at the end of the subroutine), the branch logic pops the address from the stack and begins fetching from that location. To avoid the latency of main memory accesses during CALL and RET operations, the return address stack caches the pushed addresses. The branch execution unit enables efficient speculative execution. This unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. The AMD-K6 processor does not permanently update the x86 registers or memory locations until all speculatively executed conditional branch instructions are resolved. When a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. The AMD-K6 can support up to seven outstanding branches.
Branch Execution Unit
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3
Software Environment
This chapter provides a general overview of the AMD-K6 processor's x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6 architecture and design implementation.
3.1
Registers
The AMD-K6 processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, MMX, EFLAGS, control, task, debug, test, and descriptor/memory-management registers. In addition, this chapter provides information on the AMD-K6 Model-Specific Registers (MSRs). Note: Areas of the register designated as Reserved should not be modified by software.
General-Purpose Registers
The eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions. Table 2 contains a list of the general-purpose registers and the functions for which they are used. Table 2.
Register EAX EBX ECX EDX EDI ESI ESP EBP
General-Purpose Registers
Function Commonly used as an accumulator Commonly used as a pointer Commonly used for counting in loop operations Commonly used to hold I/O information and to pass parameters Commonly used as a destination pointer by the ES segment Commonly used as a source pointer by the DS segment Used to point to the stack segment Used to point to data within the stack segment
In order to support byte and word operations, EAX, EBX, ECX, and EDX can also be used as 8-bit and 16-bit registers. The shorter registers are overlaid on the longer ones. For example, the name of the 16-bit version of EAX is AX (low 16 bits of EAX) and the 8-bit names for AX are AH (high order bits) and Chapter 3 Software Environment 21
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AL (low order bits). The same naming convention applies to EBX, ECX, and EDX. EDI, ESI, ESP, and EBP can be used as smaller 16-bit registers called DI, SI, SP, and BP respectively, but these registers do not have 8-bit versions. Figure 6 shows the EAX register with its name components, and Table 3 lists the dwo rd ( 3 2 b i t s ) g e n e ra l -p u rp o s e re g i s t e rs a n d t h e i r corresponding word (16 bits) and byte (8 bits) versions.
31 16 15 8 7 0
EAX AX AH AL
Figure 6. EAX Register with 16-Bit and 8-Bit Name Components
Table 3.
General-Purpose Register Dword, Word, and Byte Names
16-Bit Name (Word) AX BX CX DX DI SI SP BP 8-Bit Name 8-Bit Name (High-order Bits) (Low-order Bits) AH BH CH DH - - - - AL BL CL DL - - - -
32-Bit Name (Dword) EAX EBX ECX EDX EDI ESI ESP EBP
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Integer Data Types
Four types of data are used in general-purpose registers--byte, word, doubleword, and quadword integers. Figure 7 shows the format of the integer data registers.
7 Precision -- 8 Bits 0
Byte Integer
Word Integer
15 Precision -- 16 Bits 0
Doubleword Integer
31 Precision -- 32 Bits
0
Quadword Integer
63 Precision -- 64 Bits 0
Figure 7. Integer Data Types
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Segment Registers
The six 16-bit segment registers are used as pointers to areas (segments) of memory. Table 4 lists the segment registers and their functions. Figure 8 shows the format for all six segment registers. Table 4.
Segment Register CS DS ES FS GS SS
Segment Registers
Segment Register Function Code segment, where instructions are located Data segment, where data is located Data segment, where data is located Data segment, where data is located Data segment, where data is located Stack segment
15
0
Figure 8. Segment Register Segment Usage The operating system determines the type of memory model that is implemented. The segment register usage is determined by the operating system's memory model. In a Real mode memory model the segment register points to the base address in memory. In a Protected mode memory model the segment register is called a selector and it selects a segment descriptor in a descriptor table. This descriptor contains a pointer to the base of the segment, the limit of the segment, and various protection attributes. For more information on descriptor formats, see "Descriptors and Gates" on page 45. Figure 9 on page 25 shows segment usage for Real mode and Protected mode memory models.
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AMD-K6(R) Processor Data Sheet
Physical Memory
Segment Base Segment Register Real Mode Memory Model Descriptor Table Physical Memory
Base Base
Limit Limit
Base
Segment Selector
Segment Base
Protected Mode Memory Model
Figure 9. Segment Usage Instruction Pointer The instruction pointer (EIP or IP) is used in conjunction with the code segment register (CS). The instruction pointer is either a 32-bit register (EIP) or a 16-bit register (IP) that keeps track of where the next instruction resides within memory. This register cannot be directly manipulated, but can be altered by modifying return pointers when a JMP or CALL instruction is used. The floating-point execution unit in the AMD-K6 processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the IEEE 754 and 854 standards and uses several registers to meet these standards -- eight numeric floating-point registers, a status word register, a control word register, and a tag word register.
Floating-Point Registers
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The eight floating-point registers are 80 bits wide and labeled FPR0-FPR7. Figure 10 shows the format of these floating-point registers. See "Floating-Point Register Data Types" on page 28 for information on allowable floating-point data types.
79 78 Sign Exponent 64 63 Significand 0
Figure 10. Floating-Point Register The 16-bit FPU status word register contains information about the state of the floating-point unit. Figure 11 shows the format of this register.
15 14 13 12 11 10 9 8 B C 3 TOSP C 2 CC 10 7 E S 6 S F 5 4 3 2 1 D E 0 I E
PUOZ EEEE
Symbol B C3 TOSP C2 C1 C0 ES SF PE UE OE ZE DE IE
Description Bits FPU Busy 15 Condition Code 14 Top of Stack Pointer 13-11 Condition Code 10 Condition Code 9 Condition Code 8 Error Summary Status 7 Stack Fault 6 Exception Flags Precision Error 5 Underflow Error 4 Overflow Error 3 Zero Divide Error 2 Denormalized Operation Error 1 Invalid Operation Error 0 TOSP Information 000 = FPR0 111 = FPR7
Figure 11. FPU Status Word Register
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AMD-K6(R) Processor Data Sheet
The FPU control word register allows a programmer to manage the FPU processing options. Figure 12 shows the format of this register.
15 14 13 12 11 10 9 8 Y R C P C 7 6 5 4 3 2 1 0
PUOZDI MMMMMM
Reserved Symbol Y RC PC PM UM OM ZM DM IM Description Infinity Bit (80287 compatibility) Rounding Control Precision Control Exception Masks Precision Underflow Overflow Zero Divide Denormalized Operation Invalid Operation Bits 12 11-10 9-8 5 4 3 2 1 0 Precision Control Information 00b = 24 bits Single Precision Real 01b = Reserved 10b = 53 bits Double Precision Real 11b = 64 bits Extended Precision Real
Rounding Control Information 00b = Round to the nearest or even number 01b = Round down toward negative infinity 10b = Round up toward positive infinity 11b = Truncate toward zero
Figure 12. FPU Control Word Register The FPU tag word register contains information about the registers in the register stack. Figure 13 shows the format of this register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAG TAG TAG TAG TAG TAG TAG TAG (FPR7 (FPR6 (FPR5 (FPR4 (FPR3 (FPR2 (FPR1 (FPR0
Tag Values 00 = Valid 01 = Zero 10 = Special 11 = Empty
Figure 13. FPU Tag Word Register
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Floating-Point Register Data Types
Floating-point registers use four different types of data -- packed decimal, single precision real, double precision real, and extended precision real. Figures 14 and 15 show the formats for these registers.
0
79 78 S
72 71
Ignore or Zero
Precision -- 18 Digits, 72 Bits Used, 4-Bits/Digit
Description Bits Ignored on Load, Zeros on Store 78-72 Sign Bit 79
Figure 14. Packed Decimal Data Type
Single Precision Real
31 30 S
23 22 Significand
0
Biased Exponent
S = Sign Bit
Double Precision Real
63 62 S Biased Exponent
52 51 Significand
0
S = Sign Bit
Extended Precision Real
79 78 S Biased Exponent 64 63 62 I Significand 0
S = Sign Bit
I = Integer Bit
Figure 15. Precision Real Data Types
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AMD-K6(R) Processor Data Sheet
MMXTM Registers
The AMD-K6 processor implements eight 64-bit MMX registers and three packed data types for use by multimedia software. These registers are mapped on the floating-point registers. The MMX instructions refer to these registers as mm0 to mm7. Figures 16 and 17 show the format of these registers and data types. See AMD-K6(R) Processor Multimedia Technology, order# 20726 for more information.
63 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 0
Figure 16. MMXTM Registers
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Packed Bytes
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Packed Words
63 48 47 32 31 16 15 0
Packed Doublewords
63 32 31 0
Figure 17. MMXTM Data Types
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AMD-K6(R) Processor Data Sheet
EFLAGS Register
The EFLAGS register provides for three different types of flags -- system, control, and status. The system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations. Figure 18 shows the format of this register.
8 T F 7 S F 6 Z F 5 4 A F 3 2 P F 1 0 C F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 V II DP V I F AVR CMF N T I O P L OD FF I F
Reserved Symbol ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF Description Bits ID Flag 21 Virtual Interrupt Pending 20 Virtual Interrupt Flag 19 Alignment Check 18 Virtual-8086 Mode 17 Resume Flag 16 Nested Task 14 I/O Privilege Level 13-12 Overflow Flag 11 Direction Flag 10 Interrupt Flag 9 Trap Flag 8 Sign Flag 7 Zero Flag 6 Auxiliary Flag 4 Parity Flag 2 Carry Flag 0
Figure 18. EFLAGS Registers
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Control Registers
The five control registers contain system control bits and pointers. Figures 19 through 23 show the formats of these registers.
7 6 M C E 5 4 P S E 3 2 1 0
31
T DS ED
PV VM IE
Reserved Symbol MCE PSE DE TSD PVI VME Description Machine Check Enable Page Size Extensions Debugging Extensions Time Stamp Disable Protected Virtual Interrupts Virtual-8086 Mode Extensions Bit 6 4 3 2 1 0
Figure 19. Control Register 4 (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Page Directory Base
8
7
6
5
4
3
2
1
0
PP CW DT
Reserved Symbol PCD PWT Description Page Cache Disable Page Writethrough Bit 4 3
Figure 20. Control Register 3 (CR3)
31 Page Fault Linear Address
0
Figure 21. Control Register 2 (CR2)
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31 Reserved
0
Figure 22. Control Register 1 (CR1)
Symbol PG CD NW
Description Paging Cache Disable Not Writethrough 8
Bit 31 30 29 7 6 5 N E 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PCN GDW A M W P
ETEMP TSMPE
Reserved Symbol AM WP NE ET TS EM MP PE Description Alignment Mask Write Protect Numeric Error Extension Type Task Switched Emulation Monitor Co-processor Protection Enabled Bit 18 16 5 4 3 2 1 0
Figure 23. Control Register 0 (CR0)
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Debug Registers
Figures 24 through 27 show the 32-bit debug registers supported by the processor.
Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 Description Length of Breakpoint #3 Type of Transaction(s) to Trap Length of Breakpoint #2 Type of Transaction(s) to Trap Length of Breakpoint #1 Type of Transaction(s) to Trap Length of Breakpoint #0 Type of Transaction(s) to Trap Bits 31-30 29-28 27-26 25-24 23-22 21-20 19-18 17-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 G D G E
8
7
6
5 L 2
4
3
2
1
0 L 0
LGL E33
LG 21
LG 10
Reserved Symbol GD GE LE G3 L3 G2 L2 G1 L1 G0 L0 Description General Detect Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint # 3 Enabled Local Exact Breakpoint # 3 Enabled Global Exact Breakpoint # 2 Enabled Local Exact Breakpoint # 2 Enabled Global Exact Breakpoint # 1 Enabled Local Exact Breakpoint # 1 Enabled Global Exact Breakpoint # 0 Enabled Local Exact Breakpoint # 0 Enabled Bit 13 9 8 7 6 5 4 3 2 1 0
Figure 24. Debug Register DR7
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AMD-K6(R) Processor Data Sheet
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BBB TSD
8
7
6
5
4
3 B 3
2 B 2
1 B 1
0 B 0
Reserved Symbol BT BS BD B3 B2 B1 B0 Description Breakpoint Task Switch Breakpoint Single Step Breakpoint Debug Access Detected Breakpoint #3 Condition Detected Breakpoint #2 Condition Detected Breakpoint #1 Condition Detected Breakpoint #0 Condition Detected Bit 15 14 13 3 2 1 0
Figure 25. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0
Figure 26. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 3 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 2 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 1 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 0 32-bit Linear Address 8 7 6 5 4 3 2 1 0
Figure 27. Debug Registers DR3, DR2, DR1, and DR0
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AMD-K6(R) Processor Data Sheet
Model-Specific Registers (MSR)
The AMD-K6 processor provides five MSRs. The value in the ECX register selects the MSR to be addressed by the RDMSR and WRMSR instructions. The values in EAX and EDX are used as inputs and outputs by the RDMSR and WRMSR instructions. Table 5 lists the MSRs and the corresponding value of the ECX register. Figures 28 through 32 show the MSR formats. Table 5. Model-Specific Registers (MSRs)
Model-Specific Register Machine Check Address Register (MCAR) Machine Check Type Register (MCTR) Test Register 12 (TR12) Time Stamp Counter (TSC) Write Handling Control Register (WHCR) Value of ECX 00h 01h 0Eh 10h C000_0082h
For mo re info rma tio n abo ut the RD MSR and WRMSR instructions, see the AMD K86TM Family BIOS and Software Tools Development Guide, order# 21062. MCAR and MCTR. The AMD-K6 processor does not support the generation of a machine check exception. However, the processor does provide a 64-bit Machine Check Address Register (MCAR), a 64-bit Machine Check Type Register (MCTR), and a Machine Check Enable (MCE) bit in CR4. Because the processor does not support machine check exceptions, the contents of the MCAR and MCTR are only affected by the WRMSR instruction and by RESET being sampled asserted (where all bits in each register are reset to 0).
63 MCAR 0
Figure 28. Machine-Check Address Register (MCAR)
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63
5
4 MCTR
0
Reserved
Figure 29. Machine-Check Type Register (MCTR) Test Register 12 (TR12). Test register 12 provides a method for disabling the L1 caches. Figure 30 shows the format of TR12.
63 43 C I Symbol Description CI Cache Inhibit Bit Bit 3 2 1 0
Reserved
Figure 30. Test Register 12 (TR12) Time Stamp Counter. Wi t h e a ch p ro c e s s o r c l o ck cy c l e , t h e processor increments the 64-bit time stamp counter (TSC) MSR. Figure 31 shows the format of the TSC.
63 TSC 0
Figure 31. Time Stamp Counter (TSC)
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AMD-K6(R) Processor Data Sheet
Write Handling Control Register (WHCR). The Write Handling Control Register (WHCR) is a MSR that contains three fields -- the WCDE bit, Write Allocate Enable Limit (WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit. Figure 32 shows the format of WHCR. See "Write Allocate" on page 177 for more information.
63 9 8 0 7 WAELIM 1 0
W A E 1 5 M
Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program to 0 8 Write Allocate Enable Limit 7-1 Write Allocate Enable 15-to-16-Mbyte 0
Note: Hardware RESET initializes this MSR to all zeros.
Figure 32. Write Handling Control Register (WHCR) Memory Management Registers Table 6. Th e A M D -K 6 p ro c e s s o r c o n t ro l s s e g m e n t e d m e m o ry management with the registers listed in Table 6. Figure 33 on page 40 shows the formats of these registers.
Memory Management Registers
Register Name Function Contains a pointer to the base of the Global Descriptor Table Contains a pointer to the base of the Interrupt Descriptor Table Contains a pointer to the Local Descriptor Table of the current task Contains a pointer to the Task State Segment of the current task
Global Descriptor Table Register Interrupt Descriptor Table Register Local Descriptor Table Register Task Register
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Global and Interrupt Descriptor Table Registers
47 32-Bit Linear Base Address 16 15 16-Bit Limit 0
Local Descriptor Table Register and Task Register
15 Selector
0
63 32-Bit Linear Base Address
32 31 32-Bit Limit
0
15 Attributes
0
Figure 33. Memory Management Registers
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AMD-K6(R) Processor Data Sheet
Task State Segment
31
Figure 34 shows the format of the Task State Segment (TSS).
0 I/O Permission Bitmap (IOPB) (up to 8 Kbytes) TSS Limit from TR
Interrupt Redirection Bitmap (IRB) (eight 32-bit locations)
Operating System Data Structure
Base Address of IOPB 0000h 0000h 0000h 0000h 0000h 0000h 0000h EDI ESI EBP ESP EBX EDX ECX EAX EFLAGS EIP CR3 0000h ESP2 0000h ESP1 0000h ESP0 0000h
0000h LDT Selector GS FS DS SS CS ES
T
64h
SS2 SS1 SS0 Link (Prior TSS Selector) 0
Figure 34. Task State Segment (TSS) Chapter 3 Software Environment 41
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Paging
The AMD-K6 processor can address up to 4 Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set up in the Page Directory Entries (PDE) and Page Table Entries (PTE). The processor can access both 4-Kbyte pages and 4-Mbyte pages, and the page sizes can be intermixed within a page directory. When the Page Size Extension (PSE) bit in CR4 is set, the processor translates linear addresses using either the 4-Kbyte Translation Lookaside Buffer (TLB) or the 4-Mbyte TLB, depending on the state of the page size (PS) bit in the page directory entry. Figures 35 and 36 show how 4-Kbyte and 4-Mbyte page translations work.
4-Kbyte Page Frame
Page Directory
Page Table
PTE Physical Address PDE
CR3
31 Page Directory Offset
22 21 Page Table Offset
12 11 Page Offset
0
Linear Address
Figure 35. 4-Kbyte Paging Mechanism
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4-Mbyte Page Frame
Page Directory
Physical Address PDE
CR3
31 Page Directory Offset
22 21 Page Offset
0
Linear Address
Figure 36. 4-Mbyte Paging Mechanism Figures 37 through 39 show the formats of the PDE and PTE. These entries contain information regarding the location of pages and their status.
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31 Page Table Base Address
12 11 10 9 8 A V L
7 0
6
5 A
4
3
2
1
0
P P UW CW/ /P DTSR
Symbol AVL PS A PCD PWT U/S W/R P
Description Available to Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9 8 7 6 5 4 3 2 1 0
Figure 37. Page Directory Entry 4-Kbyte Page Table (PDE)
31 Physical Page Base Address
22 21 Reserved
12 11 10 9 8 A V L
7 1
6
5 A
4
3
2
1
0
P P UW CW/ /P DTSR
Symbol AVL PS A PCD PWT U/S W/R P
Description Available to Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9 8 7 6 5 4 3 2 1 0
Figure 38. Page Directory Entry 4-Mbyte Page Table (PDE)
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31 Physical Page Base Address
12 11 10 9 8 A V L
7
6
5
4
3
2
1
0
DA
P P UW CW/ /P DTSR
Symbol AVL D A PCD PWT U/S W/R P
Description Available to Software Reserved Dirty Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9 8-7 6 5 4 3 2 1 0
Figure 39. Page Table Entry (PTE) Descriptors and Gates There are various types of structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and gates. These structures are called descriptors. Figure 40 on page 46 shows the application segment descriptor format. Table 7 contains information describing the memory segment type to which the descriptor points. The application segment descriptor is used to point to either a data or code segment. Figure 41 on page 47 shows the system segment descriptor format. Table 8 contains information describing the type of segment or gate to which the descriptor points. The system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. The AMD-K6 processor uses gates to transfer control between executable segments with different privilege levels. Figure 42 on page 48 shows the format of the gate descriptor types. Table 8 contains information describing the type of segment or gate to which the descriptor points.
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Reserved
Symbol G D AVL P DPL DT Type 8 7
Description Granularity 32-Bit/16-Bit Available to Software Present/Valid Bit Descriptor Privilege Level Descriptor Type See Table 7 6 5 4 3 2 1 0
Bits 23 22 20 15 14-13 12 11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Base Address 31-24 GD A V L Segment Limit P DPL 1 Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure 40. Application Segment Descriptor
Table 7.
0 1 2 3 4 5 6 7 8 9 A B C D E F
Application Segment Types
Description Read-Only Read-Only--Accessed Read/Write Data Read/Write--Accessed Read-Only--Expand-down Read-Only--Expand-down, Accessed Read/Write--Expand-down Read/Write--Expand-down, Accessed Execute-Only Execute-Only--Accessed Execute/Read Code Execute/Read--Accessed Execute-Only--Conforming Execute-Only--Conforming, Accessed Execute/Read-Only--Conforming Execute/Read-Only--Conforming, Accessed
Type Data/Code
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Reserved
Symbol G X AVL P DPL DT Type 8 7
Description Granularity Not Needed Availability to Software Present/Valid Bit Descriptor Privilege Level Descriptor Type See Table 8 6 5 4 3 2 1 0
Bits 23 22 20 15 14-13 12 11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Base Address 31-24 GX A V L Segment Limit P DPL 0 Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure 41. System Segment Descriptor
Table 8.
Type 0 1 2 3 4 5 6 7 8 9 A B C D E F
System Segment and Gate Types
Description
Reserved Available 16-bit TSS LDT Busy 16-bit TSS 16-bit Call Gate Task Gate 16-bit Interrupt Gate 16-bit Trap Gate Reserved Available 32-bit TSS Reserved Busy 32-bit TSS 32-bit Call Gate Reserved 32-bit Interrupt Gate 32-bit Trap Gate
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Reserved
Symbol P DPL DT Type 8 7 6 5
Description Present/Valid Bit Descriptor Privilege Level Descriptor Type See Table 8 4 3 2 1 0
Bits 15 14-13 12 11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Offset 31-16 P DPL 0 Type
Segment Selector
Offset 15-0
Figure 42. Gate Descriptor Exceptions and Interrupts Table 9.
Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 0-255
Table 9 summarizes the exceptions and interrupts.
Summary of Exceptions and Interrupts
Interrupt Type Divide by Zero Error Debug Breakpoint Overflow Bounds Check Invalid Opcode Device Not Available Double Fault Reserved - Interrupt 13 Invalid TSS Segment Not Present Stack Segment General Protection Page Fault Floating-Point Error Alignment Check Software Interrupt DIV, IDIV Debug trap or fault Int 3 INTO BOUND Invalid instruction ESC and WAIT Fault occurs while handling a fault -- Task switch to an invalid segment Instruction loads a segment and present bit is 0 (invalid segment) Stack operation causes limit violation or present bit is 0 Segment related or miscellaneous invalid actions Page protection violation or a reference to missing page Arithmetic error generated by floating-point instruction Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.) INT n Cause
Non-Maskable Interrupt NMI signal sampled asserted
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3.2
Instructions Supported by the AMD-K6(R) Processor
This section documents all of the x86 instructions supported by the AMD-K6 processor. The following tables show the instruction mnemonic, opcode, modR/M byte, decode type, and RISC86 operation(s) for each instruction. Tables 10 through 12 define the integer, floating-point, and MMX instructions, respectively. The first column in these tables indicates the instruction mnemonic and operand types with the following notations:
s
s
s
s
s s s s s s s s s s s s s s s s
s
reg8--byte integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modR/M byte mreg8--byte integer register defined by bits 2, 1, and 0 of the modR/M byte reg16/32--word and doubleword integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modR/M byte mreg16/32--word and doubleword integer register defined by bits 2, 1, and 0 of the modR/M byte mem8--byte integer value in memory mem16/32--word or doubleword integer value in memory mem32/48--doubleword or 48-bit integer value in memory mem48--48-bit integer value in memory mem64--64-bit value in memory imm8--8-bit immediate value imm16/32--16-bit or 32-bit immediate value disp8--8-bit displacement value disp16/32--16-bit or 32-bit displacement value disp32/48--doubleword or 48-bit displacement value eXX--register width depending on the operand size mem32real--32-bit floating-point value in memory mem64real--64-bit floating-point value in memory mem80real--80-bit floating-point value in memory mmreg--MMX register mmreg1--MMX register defined by bits 5, 4, and 3 of the modR/M byte mmreg2--MMX register defined by bits 2, 1, and 0 of the modR/M byte Software Environment 49
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The second and third columns list all applicable opcode bytes. The fourth column lists the modR/M byte when used by the instruction. The modR/M byte defines the instruction as a register or memory form. If modR/M bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. The fifth column lists the type of instruction decode -- short, long, and vector. The AMD-K6 decode logic can process two short, one long, or one vector decode per clock. The sixth column lists the type of RISC86 operation(s) required for the instruction. The operation types and corresponding execution units are as follows:
s s s s s s s s
load, fload, mload--load unit store, fstore, mstore--store unit alu--either of the integer execution units alux--integer X execution unit only branch--branch condition unit float--floating-point execution unit meu--multimedia execution unit for MMX software limm--load immediate, instruction control unit
Table 10. Integer Instructions
Instruction Mnemonic AAA AAD AAM AAS ADC mreg8, reg8 ADC mem8, reg8 ADC mreg16/32, reg16/32 ADC mem16/32, reg16/32 ADC reg8, mreg8 ADC reg8, mem8 ADC reg16/32, mreg16/32 ADC reg16/32, mem16/32 ADC AL, imm8 First Byte 37h D5h D4h 3Fh 10h 10h 11h 11h 12h 12h 13h 13h 14h 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx 0Ah 0Ah Second Byte ModR/M Byte Decode Type vector vector vector vector short long short long short short short short short alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic ADC EAX, imm16/32 ADC mreg8, imm8 ADC mem8, imm8 ADC mreg16/32, imm16/32 ADC mem16/32, imm16/32 ADC mreg16/32, imm8 (signed ext.) ADC mem16/32, imm8 (signed ext.) ADD mreg8, reg8 ADD mem8, reg8 ADD mreg16/32, reg16/32 ADD mem16/32, reg16/32 ADD reg8, mreg8 ADD reg8, mem8 ADD reg16/32, mreg16/32 ADD reg16/32, mem16/32 ADD AL, imm8 ADD EAX, imm16/32 ADD mreg8, imm8 ADD mem8, imm8 ADD mreg16/32, imm16/32 ADD mem16/32, imm16/32 ADD mreg16/32, imm8 (signed ext.) ADD mem16/32, imm8 (signed ext.) AND mreg8, reg8 AND mem8, reg8 AND mreg16/32, reg16/32 AND mem16/32, reg16/32 AND reg8, mreg8 AND reg8, mem8 AND reg16/32, mreg16/32 AND reg16/32, mem16/32 AND AL, imm8 AND EAX, imm16/32 First Byte 15h 80h 80h 81h 81h 83h 83h 00h 00h 01h 01h 02h 02h 03h 03h 04h 05h 80h 80h 81h 81h 83h 83h 20h 20h 21h 21h 22h 22h 23h 23h 24h 25h Second Byte ModR/M Byte xx-xxx-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx Decode Type short short long short long short long short long short long short short short short short short short long short long short long short long short long short short short short short short alu alux load, alux, store alu load, alu, store alux load, alux, store alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu alux load, alux, store alu load, alu, store alux load, alux, store alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic AND mreg8, imm8 AND mem8, imm8 AND mreg16/32, imm16/32 AND mem16/32, imm16/32 AND mreg16/32, imm8 (signed ext.) AND mem16/32, imm8 (signed ext.) ARPL mreg16, reg16 ARPL mem16, reg16 BOUND BSF reg16/32, mreg16/32 BSF reg16/32, mem16/32 BSR reg16/32, mreg16/32 BSR reg16/32, mem16/32 BSWAP EAX BSWAP ECX BSWAP EDX BSWAP EBX BSWAP ESP BSWAP EBP BSWAP ESI BSWAP EDI BT mreg16/32, reg16/32 BT mem16/32, reg16/32 BT mreg16/32, imm8 BT mem16/32, imm8 BTC mreg16/32, reg16/32 BTC mem16/32, reg16/32 BTC mreg16/32, imm8 BTC mem16/32, imm8 BTR mreg16/32, reg16/32 BTR mem16/32, reg16/32 BTR mreg16/32, imm8 BTR mem16/32, imm8 First Byte 80h 80h 81h 81h 83h 83h 63h 63h 62h 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh BCh BCh BDh BDh C8h C9h CAh CBh CCh CDh CEh CFh A3h A3h BAh BAh BBh BBh BAh BAh B3h B3h BAh BAh 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx mm-110-xxx Second Byte ModR/M Byte 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short long short long short long vector vector vector vector vector vector vector long long long long long long long long vector vector vector vector vector vector vector vector vector vector vector vector alu alu alu alu alu alu alu alu alux load, alux, store alu load, alu, store alux load, alux, store RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic BTS mreg16/32, reg16/32 BTS mem16/32, reg16/32 BTS mreg16/32, imm8 BTS mem16/32, imm8 CALL full pointer CALL near imm16/32 CALL mem16:16/32 CALL near mreg32 (indirect) CALL near mem32 (indirect) CBW/CWDE EAX CLC CLD CLI CLTS CMC CMP mreg8, reg8 CMP mem8, reg8 CMP mreg16/32, reg16/32 CMP mem16/32, reg16/32 CMP reg8, mreg8 CMP reg8, mem8 CMP reg16/32, mreg16/32 CMP reg16/32, mem16/32 CMP AL, imm8 CMP EAX, imm16/32 CMP mreg8, imm8 CMP mem8, imm8 CMP mreg16/32, imm16/32 CMP mem16/32, imm16/32 CMP mreg16/32, imm8 (signed ext.) CMP mem16/32, imm8 (signed ext.) CMPSB mem8,mem8 CMPSW mem16, mem32 First Byte 0Fh 0Fh 0Fh 0Fh 9Ah E8h FFh FFh FFh 98h F8h FCh FAh 0Fh F5h 38h 38h 39h 39h 3Ah 3Ah 3Bh 3Bh 3Ch 3Dh 80h 80h 81h 81h 83h 83h A6h A7h 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 06h 11-011-xxx 11-010-xxx mm-010-xxx Second Byte ABh ABh BAh BAh ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-101-xxx mm-101-xxx Decode Type vector vector vector vector vector short vector vector vector vector vector vector vector vector vector short short short short short short short short short short short short short short long long vector vector alux load, alux alu load, alu alux load, alux alu load, alu alux alu alux load, alux alu load, alu load, alu load, alu store RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic CMPSD mem32, mem32 CMPXCHG mreg8, reg8 CMPXCHG mem8, reg8 CMPXCHG mreg16/32, reg16/32 CMPXCHG mem16/32, reg16/32 CMPXCH8B EDX:EAX CMPXCH8B mem64 CPUID CWD/CDQ EDX, EAX DAA DAS DEC EAX DEC ECX DEC EDX DEC EBX DEC ESP DEC EBP DEC ESI DEC EDI DEC mreg8 DEC mem8 DEC mreg16/32 DEC mem16/32 DIV AL, mreg8 DIV AL, mem8 DIV EAX, mreg16/32 DIV EAX, mem16/32 IDIV mreg8 IDIV mem8 IDIV EAX, mreg16/32 IDIV EAX, mem16/32 IMUL reg16/32, imm16/32 IMUL reg16/32, mreg16/32, imm16/32 First Byte A7h 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 99h 27h 2Fh 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh FEh FEh FFh FFh F6h F6h F7h F7h F6h F6h F7h F7h 69h 69h 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx 11-xxx-xxx B0h B0h B1h B1h C7h C7h A2h 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short vector long vector long vector vector vector vector vector vector vector vector vector vector load, alu, store load, alux, store alu alu alu alu alu alu alu alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic IMUL reg16/32, mem16/32, imm16/32 IMUL reg16/32, imm8 (sign extended) IMUL reg16/32, mreg16/32, imm8 (signed) IMUL reg16/32, mem16/32, imm8 (signed) IMUL AX, AL, mreg8 IMUL AX, AL, mem8 IMUL EDX:EAX, EAX, mreg16/32 IMUL EDX:EAX, EAX, mem16/32 IMUL reg16/32, mreg16/32 IMUL reg16/32, mem16/32 INC EAX INC ECX INC EDX INC EBX INC ESP INC EBP INC ESI INC EDI INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 INVD INVLPG JO short disp8 JB/JNAE short disp8 JNO short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 First Byte 69h 6Bh 6Bh 6Bh F6h F6h F7h F7h 0Fh 0Fh 40h 41h 42h 43h 44h 45h 46h 47h FEh FEh FFh FFh 0Fh 0Fh 70h 71h 71h 73h 74h 75h 76h 08h 01h mm-111-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx AFh AFh Second Byte ModR/M Byte mm-xxx-xxx 11-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx Decode Type vector vector vector vector vector vector vector vector vector vector short short short short short short short short vector long vector long vector vector short short short short short short short branch branch branch branch branch branch branch load, alu, store load, alux, store alu alu alu alu alu alu alu alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic JNBE/JA short disp8 JS short disp8 JNS short disp8 JP/JPE short disp8 JNP/JPO short disp8 JL/JNGE short disp8 JNL/JGE short disp8 JLE/JNG short disp8 JNLE/JG short disp8 JCXZ/JEC short disp8 JO near disp16/32 JNO near disp16/32 JB/JNAE near disp16/32 JNB/JAE near disp16/32 JZ/JE near disp16/32 JNZ/JNE near disp16/32 JBE/JNA near disp16/32 JNBE/JA near disp16/32 JS near disp16/32 JNS near disp16/32 JP/JPE near disp16/32 JNP/JPO near disp16/32 JL/JNGE near disp16/32 JNL/JGE near disp16/32 JLE/JNG near disp16/32 JNLE/JG near disp16/32 JMP near disp16/32 (direct) JMP far disp32/48 (direct) JMP disp8 (short) JMP far mreg32 (indirect) JMP far mem32 (indirect) JMP near mreg16/32 (indirect) JMP near mem16/32 (indirect) First Byte 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh E3h 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh E9h EAh EBh EFh EFh FFh FFh 11-101-xxx mm-101-xxx 11-100-xxx mm-100-xxx 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh Second Byte ModR/M Byte Decode Type short short short short short short short short short vector short short short short short short short short short short short short short short short short short vector short vector vector vector vector branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch RISC86(R) Opcodes branch branch branch branch branch branch branch branch branch
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Table 10. Integer Instructions (continued)
Instruction Mnemonic LAHF LAR reg16/32, mreg16/32 LAR reg16/32, mem16/32 LDS reg16/32, mem32/48 LEA reg16/32, mem16/32 LEAVE LES reg16/32, mem32/48 LFS reg16/32, mem32/48 LGDT mem48 LGS reg16/32, mem32/48 LIDT mem48 LLDT mreg16 LLDT mem16 LMSW mreg16 LMSW mem16 LODSB AL, mem8 LODSW AX, mem16 LODSD EAX, mem32 LOOP disp8 LOOPE/LOOPZ disp8 LOOPNE/LOOPNZ disp8 LSL reg16/32, mreg16/32 LSL reg16/32, mem16/32 LSS reg16/32, mem32/48 LTR mreg16 LTR mem16 MOV mreg8, reg8 MOV mem8, reg8 MOV mreg16/32, reg16/32 MOV mem16/32, reg16/32 MOV reg8, mreg8 MOV reg8, mem8 MOV reg16/32, mreg16/32 First Byte 9Fh 0Fh 0Fh C5h 8Dh C9h C4h 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh ACh ADh ADh E2h E1h E0h 0Fh 0Fh 0Fh 0Fh 0Fh 88h 88h 89h 89h 8Ah 8Ah 8Bh 03h 03h B2h 00h 00h 11-xxx-xxx mm-xxx-xxx mm-xxx-xxx 11-011-xxx mm-011-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx B4h 01h B5h 01h 00h 00h 01h 01h mm-011-xxx 11-010-xxx mm-010-xxx 11-100-xxx mm-100-xxx mm-010-xxx mm-xxx-xxx 02h 02h 11-xxx-xxx mm-xxx-xxx mm-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector short long vector vector vector vector vector vector vector vector vector long long long short vector vector vector vector vector vector vector short short short short short short short alux store alu store alux load alu load, alux load, alu load, alu alu, branch load, alu load, alu, alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic MOV reg16/32, mem16/32 MOV mreg16, segment reg MOV mem16, segment reg MOV segment reg, mreg16 MOV segment reg, mem16 MOV AL, mem8 MOV EAX, mem16/32 MOV mem8, AL MOV mem16/32, EAX MOV AL, imm8 MOV CL, imm8 MOV DL, imm8 MOV BL, imm8 MOV AH, imm8 MOV CH, imm8 MOV DH, imm8 MOV BH, imm8 MOV EAX, imm16/32 MOV ECX, imm16/32 MOV EDX, imm16/32 MOV EBX, imm16/32 MOV ESP, imm16/32 MOV EBP, imm16/32 MOV ESI, imm16/32 MOV EDI, imm16/32 MOV mreg8, imm8 MOV mem8, imm8 MOV reg16/32, imm16/32 MOV mem16/32, imm16/32 MOVSB mem8,mem8 MOVSD mem16, mem16 MOVSW mem32, mem32 MOVSX reg16/32, mreg8 First Byte 8Bh 8Ch 8Ch 8Eh 8Eh A0h A1h A2h A3h B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C6h C6h C7h C7h A4h A5h A5h 0Fh BEh 11-xxx-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx Second Byte ModR/M Byte mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short long vector vector vector short short short short short short short short short short short short short short short short short short short short short long short long long long long short load load store store limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm store limm store load, store, alux, alux load, store, alu, alu load, store, alu, alu alu load load RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic MOVSX reg16/32, mem8 MOVSX reg32, mreg16 MOVSX reg32, mem16 MOVZX reg16/32, mreg8 MOVZX reg16/32, mem8 MOVZX reg32, mreg16 MOVZX reg32, mem16 MUL AL, mreg8 MUL AL, mem8 MUL EAX, mreg16/32 MUL EAX, mem16/32 NEG mreg8 NEG mem8 NEG mreg16/32 NEG mem16/32 NOP (XCHG AX, AX) NOT mreg8 NOT mem8 NOT mreg16/32 NOT mem16/32 OR mreg8, reg8 OR mem8, reg8 OR mreg16/32, reg16/32 OR mem16/32, reg16/32 OR reg8, mreg8 OR reg8, mem8 OR reg16/32, mreg16/32 OR reg16/32, mem16/32 OR AL, imm8 OR EAX, imm16/32 OR mreg8, imm8 OR mem8, imm8 OR mreg16/32, imm16/32 First Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh F6h F6h F7h F7h F6h F6h F7h F7h 90h F6h F6h F7h F7h 08h 08h 09h 09h 0Ah 0Ah 0Bh 0Bh 0Ch 0Dh 80h 80h 81h 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-001-xxx mm-001-xxx 11-001-xxx Second Byte BEh BFh BFh B6h B6h B7h B7h ModR/M Byte mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx Decode Type short short short short short short short vector vector vector vector short vector short vector short short vector short vector short long short long short short short short short short short long short alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu alux load, alux, store alu alu limm alux alu alux alu load, alu alu load, alu alu load, alu RISC86(R) Opcodes load, alu
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Table 10. Integer Instructions (continued)
Instruction Mnemonic OR mem16/32, imm16/32 OR mreg16/32, imm8 (signed ext.) OR mem16/32, imm8 (signed ext.) POP ES POP SS POP DS POP FS POP GS POP EAX POP ECX POP EDX POP EBX POP ESP POP EBP POP ESI POP EDI POP mreg POP mem POPA/POPAD POPF/POPFD PUSH ES PUSH CS PUSH FS PUSH GS PUSH SS PUSH DS PUSH EAX PUSH ECX PUSH EDX PUSH EBX PUSH ESP PUSH EBP PUSH ESI First Byte 81h 83h 83h 07h 17h 1Fh 0Fh 0Fh 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 8Fh 8Fh 61h 9Dh 06h 0Eh 0Fh 0Fh 16h 1Eh 50h 51h 52h 53h 54h 55h 56h A0h A8h 11-000-xxx mm-000-xxx A1h A9h Second Byte ModR/M Byte mm-001-xxx 11-001-xxx mm-001-xxx Decode Type long short long vector vector vector vector vector short short short short short short short short short long vector vector long vector vector vector vector long short short short short short short short load, store store store store store store store store load, store load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, store, alu alux load, alux, store RISC86(R) Opcodes load, alu, store
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Table 10. Integer Instructions (continued)
Instruction Mnemonic PUSH EDI PUSH imm8 PUSH imm16/32 PUSH mreg16/32 PUSH mem16/32 PUSHA/PUSHAD PUSHF/PUSHFD RCL mreg8, imm8 RCL mem8, imm8 RCL mreg16/32, imm8 RCL mem16/32, imm8 RCL mreg8, 1 RCL mem8, 1 RCL mreg16/32, 1 RCL mem16/32, 1 RCL mreg8, CL RCL mem8, CL RCL mreg16/32, CL RCL mem16/32, CL RCR mreg8, imm8 RCR mem8, imm8 RCR mreg16/32, imm8 RCR mem16/32, imm8 RCR mreg8, 1 RCR mem8, 1 RCR mreg16/32, 1 RCR mem16/32, 1 RCR mreg8, CL RCR mem8, CL RCR mreg16/32, CL RCR mem16/32, CL RET near imm16 RET near First Byte 57h 6Ah 68h FFh FFh 60h 9Ch C0h C0h C1h C1h D0h D0h D1h D1h D2h D2h D3h D3h C0h C0h C1h C1h D0h D0h D1h D1h D2h D2h D3h D3h C2h C3h 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-110-xxx mm-110-xxx Second Byte ModR/M Byte Decode Type short long long vector long vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector load, store store store store RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic RET far imm16 RET far ROL mreg8, imm8 ROL mem8, imm8 ROL mreg16/32, imm8 ROL mem16/32, imm8 ROL mreg8, 1 ROL mem8, 1 ROL mreg16/32, 1 ROL mem16/32, 1 ROL mreg8, CL ROL mem8, CL ROL mreg16/32, CL ROL mem16/32, CL ROR mreg8, imm8 ROR mem8, imm8 ROR mreg16/32, imm8 ROR mem16/32, imm8 ROR mreg8, 1 ROR mem8, 1 ROR mreg16/32, 1 ROR mem16/32, 1 ROR mreg8, CL ROR mem8, CL ROR mreg16/32, CL ROR mem16/32, CL SAHF SAR mreg8, imm8 SAR mem8, imm8 SAR mreg16/32, imm8 SAR mem16/32, imm8 SAR mreg8, 1 SAR mem8, 1 First Byte CAh CBh C0h C0h C1h C1h D0h D0h D1h D1h D2h D2h D3h D3h C0h C0h C1h C1h D0h D0h D1h D1h D2h D2h D3h D3h 9Eh C0h C0h C1h C1h D0h D0h 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector short vector short vector short vector alux alu alux RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic SAR mreg16/32, 1 SAR mem16/32, 1 SAR mreg8, CL SAR mem8, CL SAR mreg16/32, CL SAR mem16/32, CL SBB mreg8, reg8 SBB mem8, reg8 SBB mreg16/32, reg16/32 SBB mem16/32, reg16/32 SBB reg8, mreg8 SBB reg8, mem8 SBB reg16/32, mreg16/32 SBB reg16/32, mem16/32 SBB AL, imm8 SBB EAX, imm16/32 SBB mreg8, imm8 SBB mem8, imm8 SBB mreg16/32, imm16/32 SBB mem16/32, imm16/32 SBB mreg8, imm8 (signed ext.) SBB mem8, imm8 (signed ext.) SCASB AL, mem8 SCASW AX, mem16 SCASD EAX, mem32 SETO mreg8 SETO mem8 SETNO mreg8 SETNO mem8 SETB/SETNAE mreg8 SETB/SETNAE mem8 SETNB/SETAE mreg8 SETNB/SETAE mem8 First Byte D1h D1h D2h D2h D3h D3h 18h 18h 19h 19h 1Ah 1Ah 1Bh 1Bh 1Ch 1Dh 80h 80h 81h 81h 83h 83h AEh AFh AFh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 90h 90h 91h 91h 92h 92h 93h 93h 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx Decode Type short vector short vector short vector short long short long short short short short short short short long short long short long vector vector vector vector vector vector vector vector vector vector vector alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu alux load, alux, store alu load, alu, store alux load, alux, store alu alux alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic SETZ/SETE mreg8 SETZ/SETE mem8 SETNZ/SETNE mreg8 SETNZ/SETNE mem8 SETBE/SETNA mreg8 SETBE/SETNA mem8 SETNBE/SETA mreg8 SETNBE/SETA mem8 SETS mreg8 SETS mem8 SETNS mreg8 SETNS mem8 SETP/SETPE mreg8 SETP/SETPE mem8 SETNP/SETPO mreg8 SETNP/SETPO mem8 SETL/SETNGE mreg8 SETL/SETNGE mem8 SETNL/SETGE mreg8 SETNL/SETGE mem8 SETLE/SETNG mreg8 SETLE/SETNG mem8 SETNLE/SETG mreg8 SETNLE/SETG mem8 SGDT mem48 SIDT mem48 SHL/SAL mreg8, imm8 SHL/SAL mem8, imm8 SHL/SAL mreg16/32, imm8 SHL/SAL mem16/32, imm8 SHL/SAL mreg8, 1 SHL/SAL mem8, 1 SHL/SAL mreg16/32, 1 First Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh C0h C0h C1h C1h D0h D0h D1h Second Byte 94h 94h 95h 95h 96h 96h 97h 97h 98h 98h 99h 99h 9Ah 9Ah 9Bh 9Bh 9Ch 9Ch 9Dh 9Dh 9Eh 9Eh 9Fh 9Fh 01h 01h ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx mm-000-xxx mm-001-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector short vector short vector short vector short alu alux alu alux RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic SHL/SAL mem16/32, 1 SHL/SAL mreg8, CL SHL/SAL mem8, CL SHL/SAL mreg16/32, CL SHL/SAL mem16/32, CL SHR mreg8, imm8 SHR mem8, imm8 SHR mreg16/32, imm8 SHR mem16/32, imm8 SHR mreg8, 1 SHR mem8, 1 SHR mreg16/32, 1 SHR mem16/32, 1 SHR mreg8, CL SHR mem8, CL SHR mreg16/32, CL SHR mem16/32, CL SHLD mreg16/32, reg16/32, imm8 SHLD mem16/32, reg16/32, imm8 SHLD mreg16/32, reg16/32, CL SHLD mem16/32, reg16/32, CL SHRD mreg16/32, reg16/32, imm8 SHRD mem16/32, reg16/32, imm8 SHRD mreg16/32, reg16/32, CL SHRD mem16/32, reg16/32, CL SLDT mreg16 SLDT mem16 SMSW mreg16 SMSW mem16 STC STD STI STOSB mem8, AL First Byte D1h D2h D2h D3h D3h C0h C0h C1h C1h D0h D0h D1h D1h D2h D2h D3h D3h 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh F9h FDh FBh AAh A4h A4h A5h A5h ACh ACh ADh ADh 00h 00h 01h 01h Second Byte ModR/M Byte mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx Decode Type vector short vector short vector short vector short vector short vector short vector short vector short vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector long store, alux alu alux alu alux alu alux alu alux RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic STOSW mem16, AX STOSD mem32, EAX STR mreg16 STR mem16 SUB mreg8, reg8 SUB mem8, reg8 SUB mreg16/32, reg16/32 SUB mem16/32, reg16/32 SUB reg8, mreg8 SUB reg8, mem8 SUB reg16/32, mreg16/32 SUB reg16/32, mem16/32 SUB AL, imm8 SUB EAX, imm16/32 SUB mreg8, imm8 SUB mem8, imm8 SUB mreg16/32, imm16/32 SUB mem16/32, imm16/32 SUB mreg16/32, imm8 (signed ext.) SUB mem16/32, imm8 (signed ext.) TEST mreg8, reg8 TEST mem8, reg8 TEST mreg16/32, reg16/32 TEST mem16/32, reg16/32 TEST AL, imm8 TEST EAX, Imm16/32 TEST mreg8, imm8 TEST mem8, imm8 TEST mreg8, imm16/32 TEST mem8, imm16/32 VERR mreg16 VERR mem16 VERW mreg16 First Byte ABh ABh 0Fh 0Fh 28h 28h 29h 29h 2Ah 2Ah 2Bh 2Bh 2Ch 2Dh 80h 80h 81h 81h 83h 83h 84h 84h 85h 85h A8h A9h F6h F6h F7h F7h 0Fh 0Fh 0Fh 00h 00h 00h 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx 11-101-xxx 00h 00h 11-001-xxx mm-001-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type long long vector vector short long short long short short short short short short short long short long short long short vector short vector long long long long long long vector vector vector alux alu alux load, alux alu load, alu alu alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu alux load, alux, store alu load, alu, store alux load, alux, store alux RISC86(R) Opcodes store, alu store, alu
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Table 10. Integer Instructions (continued)
Instruction Mnemonic VERW mem16 WAIT WBINVD XADD mreg8, reg8 XADD mem8, reg8 XADD mreg16/32, reg16/32 XADD mem16/32, reg16/32 XCHG reg8, mreg8 XCHG reg8, mem8 XCHG reg16/32, mreg16/32 XCHG reg16/32, mem16/32 XCHG EAX, EAX XCHG EAX, ECX XCHG EAX, EDX XCHG EAX, EBX XCHG EAX, ESP XCHG EAX, EBP XCHG EAX, ESI XCHG EAX, EDI XLAT XOR mreg8, reg8 XOR mem8, reg8 XOR mreg16/32, reg16/32 XOR mem16/32, reg16/32 XOR reg8, mreg8 XOR reg8, mem8 XOR reg16/32, mreg16/32 XOR reg16/32, mem16/32 XOR AL, imm8 XOR EAX, imm16/32 XOR mreg8, imm8 XOR mem8, imm8 XOR mreg16/32, imm16/32 First Byte 0Fh 9Bh 0Fh 0Fh 0Fh 0Fh 0Fh 86h 86h 87h 87h 90h 91h 92h 93h 94h 95h 96h 97h D7h 30h 30h 31h 31h 32h 32h 33h 33h 34h 35h 80h 80h 81h 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx xx-xxx-xxx xx-xxx-xxx 11-110-xxx mm-110-xxx 11-110-xxx 09h C0h C0h C1h C1h 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte 00h ModR/M Byte mm-101-xxx Decode Type vector vector vector vector vector vector vector vector vector vector vector short long long long long long long long vector short long short long short short short short short short short long short alux load, alux, store alu load, alu, store alux load, alux alu load, alu alux alu alux load, alux, store alu limm alu, alu, alu alu, alu, alu alu, alu, alu alu, alu, alu alu, alu, alu alu, alu, alu alu, alu, alu RISC86(R) Opcodes
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Table 10. Integer Instructions (continued)
Instruction Mnemonic XOR mem16/32, imm16/32 XOR mreg16/32, imm8 (signed ext.) XOR mem16/32, imm8 (signed ext.) First Byte 81h 83h 83h Second Byte ModR/M Byte mm-110-xxx 11-110-xxx mm-110-xxx Decode Type long short long alux load, alux, store RISC86(R) Opcodes load, alu, store
Table 11. Floating-Point Instructions
Instruction Mnemonic F2XM1 FABS FADD ST(0), ST(i) FADD ST(0), mem32real FADD ST(i), ST(0) FADD ST(0), mem64real FADDP ST(i), ST(0) FBLD FBSTP FCHS FCLEX FCOM ST(0), ST(i) FCOM ST(0), mem32real FCOM ST(0), mem64real FCOMP ST(0), ST(i) FCOMP ST(0), mem32real FCOMP ST(0), mem64real FCOMPP FCOS ST(0) FDECSTP FDIV ST(0), ST(i) (single precision) FDIV ST(0), ST(i) (double precision) FDIV ST(0), ST(i) (extended precision)
Note:
First Byte D9h D9h D8h D8h DCh DCh DEh DFh DFh D9h DBh D8h D8h DCh D8h D8h DCh DEh D9h D9h D8h D8h D8h
Second Byte F0h F1h
ModR/M Byte
Decode Type short short
RISC86(R) Opcodes float float float fload, float float fload, float float
Note
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-100-xxx mm-110-xxx E0h E2h 11-010-xxx mm-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx mm-011-xxx 11-011-001 FFh F6h 11-110-xxx 11-110-xxx 11-110-xxx
short short short short short vector vector short vector short short short short short short short short short short short short
* * * * *
float float fload, float fload, float float fload, float fload, float float float float float float float * * * * *
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 11. Floating-Point Instructions (continued)
Instruction Mnemonic FDIV ST(i), ST(0) (single precision) FDIV ST(i), ST(0) (double precision) FDIV ST(i), ST(0) (extended precision) FDIV ST(0), mem32real FDIV ST(0), mem64real FDIVP ST(0), ST(i) FDIVR ST(0), ST(i) FDIVR ST(I), ST(0) FDIVR ST(0), mem32real FDIVR ST(0), mem64real FDIVRP ST(i), ST(0) FFREE ST(I) FIADD ST(0), mem32int FIADD ST(0), mem16int FICOM ST(0), mem32int FICOM ST(0), mem16int FICOMP ST(0), mem32int FICOMP ST(0), mem16int FIDIV ST(0), mem32int FIDIV ST(0), mem16int FIDIVR ST(0), mem32int FIDIVR ST(0), mem16int FILD mem16int FILD mem32int FILD mem64int FIMUL ST(0), mem32int FIMUL ST(0), mem16int FINCSTP FINIT FIST mem16int FIST mem32int
Note:
First Byte DCh DCh DCh D8h DCh DEh D8h DCh D8h DCh DEh DDh DAh DEh DAh DEh DAh DEh DAh DEh DAh DEh DFh DBh DFh DAh DEh D9h DBh DFh DBh
Second Byte
ModR/M Byte 11-111-xxx 11-111-xxx 11-111-xxx mm-110-xxx mm-110-xxx 11-111-xxx 11-110-xxx 11-111-xxx mm-111-xxx mm-111-xxx 11-110-xxx 11-000-xxx mm-000-xxx mm-000-xxx mm-010-xxx mm-010-xxx mm-011-xxx mm-011-xxx mm-110-xxx mm-110-xxx mm-111-xxx mm-111-xxx mm-000-xxx mm-000-xxx mm-101-xxx mm-001-xxx mm-001-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short vector
RISC86(R) Opcodes float float float fload, float fload, float float float float fload, float fload, float float float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float float fload, float fload, float
Note * * *
* * *
* *
F7h E3h mm-010-xxx mm-010-xxx
short short
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 11. Floating-Point Instructions (continued)
Instruction Mnemonic FISTP mem16int FISTP mem32int FISTP mem64int FISUB ST(0), mem32int FISUB ST(0), mem16int FISUBR ST(0), mem32int FISUBR ST(0), mem16int FLD ST(i) FLD mem32real FLD mem64real FLD mem80real FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL ST(0), ST(i) FMUL ST(i), ST(0) FMUL ST(0), mem32real FMUL ST(0), mem64real FMULP ST(0), ST(i) FNOP FPATAN FPREM FPREM1 FPTAN FRNDINT
Note:
First Byte DFh DBh DFh DAh DEh DAh DEh D9h D9h DDh DBh D9h D9h D9h D9h D9h D9h D9h D9h D9h D8h DCh D8h DCh DEh D9h D9h D9h D9h D9h D9h
Second Byte
ModR/M Byte mm-011-xxx mm-011-xxx mm-111-xxx mm-100-xxx mm-100-xxx mm-101-xxx mm-101-xxx 11-000-xxx mm-000-xxx mm-000-xxx mm-101-xxx
Decode Type short short short short short short short short short short vector short
RISC86(R) Opcodes fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float float float float float float float float float fload, float fload, float float float float float float float
Note
*
E8h mm-101-xxx mm-100-xxx EAh E9h ECh EDh EBh EEh 11-001-xxx 11-001-xxx mm-001-xxx mm-001-xxx 11-001-xxx D0h F3h F8h F5h F2h FCh
vector short short short short short short short short short short short short short short short short vector short
* *
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 11. Floating-Point Instructions (continued)
Instruction Mnemonic FRSTOR FSAVE FSCALE FSIN FSINCOS FSQRT (single precision) FSQRT (double precision) FSQRT (extended precision) FST mem32real FST mem64real FST ST(i) FSTCW FSTENV FSTP mem32real FSTP mem64real FSTP mem80real FSTP ST(i) FSTSW AX FSTSW mem16 FSUB ST(0), mem32real FSUB ST(0), mem64real FSUB ST(0), ST(i) FSUB ST(i), ST(0) FSUBP ST(0), ST(I) FSUBR ST(0), mem32real FSUBR ST(0), mem64real FSUBR ST(0), ST(I) FSUBR ST(i), ST(0) FSUBRP ST(i), ST(0) FTST FUCOM
Note:
First Byte DDh DDh D9h D9h D9h D9h D9h D9h D9h DDh DDh D9h D9h D9h DDh D9h DDh DFh DDh D8h DCh D8h DCh DEh D8h DCh D8h DCh DEh D9h DDh
Second Byte
ModR/M Byte mm-100-xxx mm-110-xxx
Decode Type vector vector short short vector short short short
RISC86(R) Opcodes
Note
FDh FEh FBh FAh FAh FAh mm-010-xxx mm-010-xxx 11-010xxx mm-111-xxx mm-110-xxx mm-011-xxx mm-011-xxx mm-111-xxx 11-011-xxx E0h mm-111-xxx mm-100-xxx mm-100-xxx 11-100-xxx 11-101-xxx 11-101-xxx mm-101-xxx mm-101-xxx 11-100-xxx 11-101-xxx 11-100-xxx E4h 11-100-xxx
float float float float float fstore fstore fstore
short short short vector vector short short vector short vector vector short short short short short short short short short short short short
fstore fstore float
fload, float fload, float float float float fload, float fload, float float float float float float
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 11. Floating-Point Instructions (continued)
Instruction Mnemonic FUCOMP FUCOMPP FXAM FXCH FXTRACT FYL2X FYL2XP1 FWAIT
Note:
First Byte DDh DAh D9h D9h D9h D9h D9h 9Bh
Second Byte E9h E5h
ModR/M Byte 11-101-xxx
Decode Type short short short
RISC86(R) Opcodes float float float float float float
Note
11-001-xxx F4h F1h F9h
short vector short short vector
*
The last three bits of the modR/M byte select the stack entry ST(i).
Table 12. MMXTM Instructions
Instruction Mnemonic EMMS MOVD mmreg, mreg32 MOVD mmreg, mem32 MOVD mreg32, mmreg MOVD mem32, mmreg MOVQ mmreg1, mmreg2 MOVQ mmreg, mem64 MOVQ mmreg1, mmreg2 MOVQ mem64, mmreg PACKSSDW mmreg1, mmreg2 PACKSSDW mmreg, mem64 PACKSSWB mmreg1, mmreg2 PACKSSWB mmreg, mem64 PACKUSWB mmreg1, mmreg2 PACKUSWB mmreg, mem64 PADDB mmreg1, mmreg2 PADDB mmreg, mem64
Note:
Prefix First Byte(s) Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 77h 6Eh 6Eh 7Eh 7Eh 6Fh 6Fh 7Fh 7Fh 6Bh 6Bh 63h 64h 67h 67h FCh FCh
ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode Type vector short short short short short short short short short short short short short short short short
RISC86(R) Opcodes store, mload mload mstore, load mstore meu mload meu mstore meu mload, meu meu mload, meu meu mload, meu meu mload, meu
Note
* *
*
Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 12. MMXTM Instructions (continued)
Instruction Mnemonic PADDD mmreg1, mmreg2 PADDD mmreg, mem64 PADDSB mmreg1, mmreg2 PADDSB mmreg, mem64 PADDSW mmreg1, mmreg2 PADDSW mmreg, mem64 PADDUSB mmreg1, mmreg2 PADDUSB mmreg, mem64 PADDUSW mmreg1, mmreg2 PADDUSW mmreg, mem64 PADDW mmreg1, mmreg2 PADDW mmreg, mem64 PAND mmreg1, mmreg2 PAND mmreg, mem64 PANDN mmreg1, mmreg2 PANDN mmreg, mem64 PCMPEQB mmreg1, mmreg2 PCMPEQB mmreg, mem64 PCMPEQD mmreg1, mmreg2 PCMPEQD mmreg, mem64 PCMPEQW mmreg1, mmreg2 PCMPEQW mmreg, mem64 PCMPGTB mmreg1, mmreg2 PCMPGTB mmreg, mem64 PCMPGTD mmreg1, mmreg2 PCMPGTD mmreg, mem64 PCMPGTW mmreg1, mmreg2 PCMPGTW mmreg, mem64 PMADDWD mmreg1, mmreg2 PMADDWD mmreg, mem64 PMULHW mmreg1, mmreg2
Note:
Prefix First Byte(s) Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh FEh FEh ECh ECh EDh EDh DCh DCh DDh DDh FDh FDh DBh DBh DFh DFh 74h 74h 76h 76h 75h 75h 64h 64h 66h 66h 65h 65h F5h F5h E5h
ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short
RISC86(R) Opcodes meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu
Note
*
Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 12. MMXTM Instructions (continued)
Instruction Mnemonic PMULHW mmreg, mem64 PMULLW mmreg1, mmreg2 PMULLW mmreg, mem64 POR mmreg1, mmreg2 POR mmreg, mem64 PSLLW mmreg1, mmreg2 PSLLW mmreg, mem64 PSLLW mmreg, imm8 PSLLD mmreg1, mmreg2 PSLLD mmreg, mem64 PSLLD mmreg, imm8 PSLLQ mmreg1, mmreg2 PSLLQ mmreg, mem64 PSLLQ mmreg, imm8 PSRAW mmreg1, mmreg2 PSRAW mmreg, mem64 PSRAW mmreg, imm8 PSRAD mmreg1, mmreg2 PSRAD mmreg, mem64 PSRAD mmreg, imm8 PSRAQ mmreg1, mmreg2 PSRAQ mmreg, mem64 PSRAQ mmreg, imm8 PSRLW mmreg1, mmreg2 PSRLW mmreg, mem64 PSRLW mmreg, imm8 PSRLD mmreg1, mmreg2 PSRLD mmreg, mem64 PSRLD mmreg, imm8 PSRLQ mmreg1, mmreg2 PSRLQ mmreg, mem64
Note:
Prefix First Byte(s) Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh E5h D5h D5h EBh EBh F1h F1h 71h F2h F2h 72h F3h F3h 73h E1h E1h 71h E2h E2h 72h E3h E3h 73h D1h D1h 71h D2h D2h 72h D3h D3h
ModR/M Byte mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx 11-xxx-xxx 11-110-xxx 11-xxx-xxx 11-xxx-xxx 11-110-xxx 11-xxx-xxx 11-xxx-xxx 11-110-xxx 11-xxx-xxx 11-xxx-xxx 11-100-xxx 11-xxx-xxx 11-xxx-xxx 11-100-xxx 11-xxx-xxx 11-xxx-xxx 11-100-xxx 11-xxx-xxx 11-xxx-xxx 11-010-xxx 11-xxx-xxx 11-xxx-xxx 11-010-xxx 11-xxx-xxx 11-xxx-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short
RISC86(R) Opcodes mload, meu meu mload, meu meu mload, meu meu mload, meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu meu
Note
*
Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 12. MMXTM Instructions (continued)
Instruction Mnemonic PSRLQ mmreg, imm8 PSUBB mmreg1, mmreg2 PSUBB mmreg, mem64 PSUBD mmreg1, mmreg2 PSUBD mmreg, mem64 PSUBSB mmreg1, mmreg2 PSUBSB mmreg, mem64 PSUBSW mmreg1, mmreg2 PSUBSW mmreg, mem64 PSUBUSB mmreg1, mmreg2 PSUBUSB mmreg, mem64 PSUBUSW mmreg1, mmreg2 PSUBUSW mmreg, mem64 PSUBW mmreg1, mmreg2 PSUBW mmreg, mem64 PUNPCKHBW mmreg1, mmreg2 PUNPCKHBW mmreg, mem64 PUNPCKHWD mmreg1, mmreg2 PUNPCKHWD mmreg, mem64 PUNPCKHDQ mmreg1, mmreg2 PUNPCKHDQ mmreg, mem64 PUNPCKLBW mmreg1, mmreg2 PUNPCKLBW mmreg, mem64 PUNPCKLWD mmreg1, mmreg2 PUNPCKLWD mmreg, mem64 PUNPCKLDQ mmreg1, mmreg2 PUNPCKLDQ mmreg, mem64 PXOR mmreg1, mmreg2 PXOR mmreg, mem64
Note:
Prefix First Byte(s) Byte 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 73h F8h F8h FAh FAh E8h E8h E9h E9h D8h D8h D9h D9h F9h F9h 68h 68h 69h 69h 6Ah 6Ah 60h 60h 61h 61h 62h 62h EFh EFh
ModR/M Byte 11-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short short
RISC86(R) Opcodes meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu meu mload, meu
Note
*
Bits 2, 1, and 0 of the modR/M byte select the integer register.
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4
Logic Symbol Diagram
Clock Voltage Detection
CLK
BF[2:0]
VCC2DET
Bus Arbitration
AHOLD BOFF# BREQ HLDA HOLD
BRDY# BRDYC# D[63:0] DP[7:0] PCHK#
Data and Data Parity
Address and Address Parity
A20M# A[31:3] AP ADS# ADSC# APCHK# BE[7:0]#
EADS# HIT# HITM# INV
Inquire Cycles
Cycle Definition and Control
D/C# EWBE# LOCK# M/IO# NA# SCYC W/R#
AMD-K6(R)
Processor
FERR# IGNNE#
Floating-Point Error Handling
Cache Control
CACHE# KEN# PCD PWT WB/WT#
FLUSH# INIT INTR NMI RESET SMI# SMIACT# STPCLK#
External Interrupts, SMM, Reset and Initialization
TCK
TDI
TDO
TMS TRST#
JTAG Test
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Logic Symbol Diagram
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5
5.1
Summary
Signal Descriptions
A20M# (Address Bit 20 Mask)
Input
A20M# is used to simulate the behavior of the 8086 when running in Real mode. The assertion of A20M # causes the processor to force bit 20 of the physical address to 0 prior to accessing the cache or driving out a memory bus cycle. The clearing of address bit 20 maps addresses that wrap above 1 Mbyte to addresses below 1 Mbyte. The processor samples A20M # as a level-sensitive input on every clock edge. The system logic can drive the signal either s y n ch ro n o u s ly o r a s y n ch ro n o u s ly. I f i t i s a s s e r t e d asynchronously, it must be asserted for a minimum pulse width of two clocks. The following list explains the effects of the processor sampling A20M# asserted under various conditions:
s
Sampled
s
s
s
s
Inquire cycles and writeback cycles are not affected by the state of A20M#. The assertion of A20M# in System Management Mode (SMM) is ignored. When A20M# is sampled asserted in Protected mode, it causes unpredictable processor operation. A20M# is only defined in Real mode. To ensure that A20M# is recognized before the first ADS# occurs following the negation of RESET, A20M# must be sampled asserted on the same clock edge that RESET is sampled negated or on one of the two subsequent clock edges. To ensure A20M# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts A20M# and the targeted instruction.
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5.2
Summary
A[31:3] (Address Bus)
A[31:5] Bidirectional, A[4:3] Output
A[31:3] contain the physical address for the current bus cycle. The processor drives addresses on A[31:3] during memory and I/O cycles, and cycle definition information during special bus cycles. The processor samples addresses on A[31:5] during inquire cycles. As Outputs: A[31:3] are driven valid off the same clock edge as ADS # and remain in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. A[31:3] are driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. The processor continues to drive the address bus while the bus is idle. As Inputs: The processor samples A[31:5] during inquire cycles on the clock edge on which EADS# is sampled asserted. Even though A4 and A3 are not used during the inquire cycle, they must be driven to a valid state and must meet the same timings as A[31:5]. A[31:3] are floated off the clock edge that AHOLD or BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. The processor resumes driving A[31:3] off the clock edge on which the processor samples AHOLD or BOFF# negated and off the clock edge on which the processor negates HLDA.
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5.3
Summary
ADS# (Address Strobe)
Output
The assertion of ADS # indicates the beginning of a new bus cycle. The address bus and all cycle definition signals corresponding to this bus cycle are driven valid off the same clock edge as ADS#. ADS # is asserted for one clock at the beginning of each bus cycle. For non-pipelined cycles, ADS# can be asserted as early as the clock edge after the clock edge on which the last expected BRDY# of the cycle is sampled asserted, resulting in a single idle state between cycles. For pipelined cycles if the processor is prepared to start a new cycle, ADS# can be asserted as early as one clock edge after NA# is sampled asserted. If AHOLD is sampled asserted, ADS# is only driven in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. The processor floats ADS # off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD.
Driven and Floated
5.4
Summary
ADSC# (Address Strobe Copy)
Output
ADSC # has the identical function and timing as ADS#. In the event ADS# becomes too heavily loaded due to a large fanout in a system, ADSC # can be used to split the load across two outputs, which improves timing.
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5.5
Summary
AHOLD (Address Hold)
Input
AHOLD can be asserted by the system to initiate one or more inquire cycles. To allow the system to drive the address bus during an inquire cycle, the processor floats A[31:3] and AP off the clock edge on which AHOLD is sampled asserted. The data bus and all other control and status signals remain under the control of the processor and are not floated. This allows a bus cycle that is in progress when AHOLD is sampled asserted to continue to completion. The processor resumes driving the address bus off the clock edge on which AHOLD is sampled negated. If AHOLD is sampled asserted, ADS# is only asserted in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line.
Sampled
The processor samples AHOLD on every clock edge. AHOLD is recognized while INIT and RESET are sampled asserted.
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5.6
Summary
AP (Address Parity)
Bidirectional
AP contains the even parity bit for cache line addresses driven and sampled on A[31:5]. Even parity means that the total number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not used for the generation or checking of address parity because these bits are not required to address a cache line.) AP is driven by the processor during processor-initiated cycles and is sampled by the processor during inquire cycles. If AP does not reflect even parity during an inquire cycle, the processor asserts APCHK # to indicate an address bus parity check. The processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. As an Output: The processor drives AP valid off the clock edge on which ADS# is asserted until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. AP is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. The processor continues to drive AP while the bus is idle. As an Input: The processor samples AP during inquire cycles on the clock edge on which EADS# is sampled asserted. The processor floats AP off the clock edge that AHOLD or BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. The processor resumes driving AP off the clock edge on which the processor samples AHOLD or BOFF # negated and off the clock edge on which the processor negates HLDA.
Driven, Sampled, and Floated
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5.7
Summary
APCHK# (Address Parity Check)
Output
If the processor detects an address parity error during an inquire cycle, APCHK# is asserted for one clock. The processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. The processor ensures that APCHK # does not glitch, enabling the signal to be used as a clocking source for system logic.
Driven
APCHK# is driven valid the clock edge after the clock edge on which the processor samples EADS# asserted. It is negated off the next clock edge. APCHK# is always driven except in Tri-State Test mode.
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5.8
Summary
BE[7:0]# (Byte Enables)
Output
BE[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. The byte enables can be used to derive address bits A[2:0], which are not physically part of the processor's address bus. The processor checks and generates valid data parity for the data bytes that are valid as defined by the byte enables. The eight byte enables correspond to the eight bytes of the data bus as follows:
s s s s
BE7#: D[63:56] BE6#: D[55:48] BE5#: D[47:40] BE4#: D[39:32]
s s s s
BE3#: D[31:24] BE2#: D[23:16] BE1#: D[15:8] BE0#: D[7:0]
The processor expects data to be driven by the system logic on all eight bytes of the data bus during a burst cache-line read cycle, independent of the byte enables that are asserted. The byte enables are also used to distinguish between special bus cycles as defined in Table 19 on page 119. Driven and Floated BE[7:0]# are driven off the same clock edge as ADS # and remain in the same state until the clock edge on which NA# or the last expected BRDY # of the cycle is sampled asserted. BE[7:0]# are driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. The processor floats BE[7:0]# off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. Unlike the address bus, BE[7:0]# are not floated in response to AHOLD.
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5.9
Summary
BF[2:0] (Bus Frequency)
Inputs, Internal Pullups
BF[2:0] determine the internal operating frequency of the processor. The frequency of the CLK input signal is multiplied internally by a ratio determined by the state of these signals as defined in Table 13. BF[2:0] have weak internal pullups and default to the 3.5 multiplier if left unconnected. Table 13. Processor-to-Bus Clock Ratios
State of BF[2:0] Inputs 100b 101b 110b 111b 000b 001b 010b 011b Processor-Clock to Bus-Clock Ratio 2.5x 3.0x 2.0x 3.5x 4.5x 5.0x 4.0x 5.5x
Sampled
BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
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5.10
Summary
BOFF# (Backoff)
Input
If BOFF # is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #, D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and W/R#. These signals remain floated until BOFF# is sampled negated. This allows an alternate bus master or the system to control the bus. When BOFF# is sampled negated, any processor cycle that was aborted due to the assertion of BOFF # is restarted from the beginning of the cycle, regardless of the number of transfers that were completed. If BOFF# is sampled asserted on the same clock edge as BRDY# of a bus cycle of any length, then BOFF# takes precedence over the BRDY #. In this case, the cycle is aborted and restarted after BOFF# is sampled negated.
Sampled
BOFF# is sampled on every clock edge. The processor floats its bus signals off the clock edge on which BOFF # is sampled asserted. These signals remain floated until the clock edge on which BOFF# is sampled negated. BOFF # is recognized while INIT and RESET are sampled asserted.
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5.11
Summary
BRDY# (Burst Ready)
Input, Internal Pullup
BRDY# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the data bus has been latched during a write cycle. If necessary, the system logic can insert bus cycle wait states by negating BRDY# until it is ready to continue the data transfer. BRDY # is also used to indicate the completion of special bus cycles. BRDY# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ADS #. BRDY# is ignored while the bus is idle. The processor samples the following inputs on the clock edge on which BRDY # is sampled asserted: D[63:0], DP[7:0], and KEN # during read cycles, EWBE# during write cycles, and WB/WT# during read and write cycles. If NA # is sampled asserted prior to BRDY #, then KEN # and WB/WT # are sampled on the clock edge on which NA# is sampled asserted. The number of times the processor expects to sample BRDY # asserted depends on the type of bus cycle, as follows:
s
Sampled
s
One time for a single-transfer cycle, a special bus cycle, or each of two cycles in an interrupt acknowledge sequence Four times for a burst cycle (once for each data transfer)
BRDY # can be held asserted for four consecutive clocks throughout the four transfers of the burst, or it can be negated to insert wait states.
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5.12
Summary
BRDYC# (Burst Ready Copy)
Input, Internal Pullup
BRDYC # has the identical function as BRDY #. In the event BRDY # becomes too heavily loaded due to a large fanout or loading in a system, BRDYC # can be used to reduce this loading, which improves timing. In addition, BRDYC # is sampled when RESET is negated to configure the drive strength of A[20:3], ADS #, HITM #, and W/R #. If BRDYC# is 0 during the falling transition of RESET, these particular outputs are configured using higher drive strengths than the standard strength. If BRDYC# is 1 during the falling transition of RESET, the standard strength is selected.
Sampled
BRDYC# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ADS#. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC # must meet the specified hold time relative to the negation of RESET. If RESET is driven asynchronously, the minimum setup and hold time for BRDYC # relative to the negation of RESET is two clocks.
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5.13
Summary
BREQ (Bus Request)
Output
BREQ is asserted by the processor to request the bus in order to complete an internally pending bus cycle. The system logic can use BREQ to arbitrate among the bus participants. If the processor does not own the bus, BREQ is asserted until the processor gains access to the bus in order to begin the pending cycle or until the processor no longer needs to run the pending cycle. If the processor currently owns the bus, BREQ is asserted with ADS#. The processor asserts BREQ for each assertion of ADS# but does not necessarily assert ADS# for each assertion of BREQ. BREQ is asserted off the same clock edge on which ADS # is asserted. BREQ can also be asserted off any clock edge, independent of the assertion of ADS#. BREQ can be negated one clock edge after it is asserted. The processor always drives BREQ except in Tri-State Test mode.
Driven
5.14
Summary
CACHE# (Cacheable Access)
Output
For reads, CACHE# is asserted to indicate the cacheability of the current bus cycle. In addition, if the processor samples KEN # assert ed, which indicates t he driven address is cacheable, the cycle is a 32-byte burst read cycle. For write cycles, CACHE# is asserted to indicate the current bus cycle is a modified cache-line writeback. KEN # is ignored during writebacks. If CACHE# is not asserted, or if KEN # is sampled negated during a read cycle, the cycle is not cacheable and defaults to a single-transfer cycle. CACHE# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. CACHE # is floated off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD.
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5.15
Summary
CLK (Clock)
Input
The CLK signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal frequency multiplier applied to CLK to obtain the processor's core operating frequency. (See "BF[2:0] (Bus Frequency)" on page 86 for a list of the processor-to-bus clock ratios.) The CLK signal must be stable a minimum of 1.0 ms prior to the negation of RESET to ensure the proper operation of the processor. See "CLK Switching Characteristics" on page 241 for details regarding the CLK specifications.
Sampled
5.16
Summary
D/C# (Data/Code)
Output
The processor drives D/C # during a memory bus cycle to indicate whether it is addressing data or executable code. D/C# is also used to define other bus cycles, including interrupt acknowledge and special cycles. (See Table 19 on page 119 for more details.) D/C# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA # or the last expected BRDY # of the cycle is sampled asserted. D/C # is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. D/C # is floated off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD.
Driven and Floated
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Summary
D[63:0] (Data Bus)
Bidirectional
D[63:0] represent the processor's 64-bit data bus. Each of the eight bytes of data that comprise this bus is qualified as valid by its corresponding byte enable. (See "BE[7:0]# (Byte Enables)" on page 85.) As Outputs: For single-transfer write cycles, the processor drives D[63:0] with valid data one clock edge after the clock edge on which ADS# is asserted and D[63:0] remain in the same state until the clock edge on which BRDY# is sampled asserted. If the cycle is a writeback--in which case four, 8-byte transfers occur--D[63:0] are driven one clock edge after the clock edge on which ADS# is asserted and are subsequently changed off the clock edge on which each BRDY# assertion of the burst cycle is sampled. If the assertion of ADS# represents a pipelined write cycle that follows a read cycle, the processor does not drive D[63:0] until it is certain that contention on the data bus will not occur. In this case, D[63:0] are driven the clock edge after the last expected BRDY# of the previous cycle is sampled asserted. As Inputs: During read cycles, the processor samples D[63:0] on the clock edge on which BRDY# is sampled asserted. The processor always floats D[63:0] except when they are being driven during a write cycle as described above. In addition, D[63:0] are floated off the clock edge that BOFF # is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD.
Driven, Sampled, and Floated
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5.18
Summary
DP[7:0] (Data Parity)
Bidirectional
DP[7:0] are even parity bits for each valid byte of data -- as defined by BE[7:0]#--driven and sampled on the D[63:0] data bus. (Even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) DP[7:0] are driven by the processor during write cycles and sampled by the processor during read cycles. If the processor detects bad parity on any valid byte of data during a read cycle, PCHK# is asserted for one clock beginning the clock edge after BRDY # is sampled asserted. The processor does not take an internal exception as the result of detecting a data parity check, and system logic must respond appropriately to the assertion of this signal. The eight data parity bits correspond to the eight bytes of the data bus as follows:
s s s s
DP7: D[63:56] DP6: D[55:48] DP5: D[47:40] DP4: D[39:32]
s s s s
DP3: D[31:24] DP2: D[23:16] DP1: D[15:8] DP0: D[7:0]
For systems that do not support data parity, DP[7:0] should be connected to VCC3 through pullup resistors. Driven, Sampled, and Floated As Outputs: For single-transfer write cycles, the processor drives DP[7:0] with valid parity one clock edge after the clock edge on which ADS# is asserted and DP[7:0] remain in the same state until the clock edge on which BRDY# is sampled asserted. If the cycle is a writeback, DP[7:0] are driven one clock edge after the clock edge on which ADS# is asserted and are subsequently changed off the clock edge on which each BRDY# assertion of the burst cycle is sampled. As Inputs: During read cycles, the processor samples DP[7:0] on the clock edge BRDY# is sampled asserted. The processor always floats DP[7:0] except when they are being driven during a write cycle as described above. In addition, DP[7:0] are floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. Chapter 5 Signal Descriptions 93
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5.19
Summary
EADS# (External Address Strobe)
Input
System logic asserts EADS # during a cache inquire cycle to indicate that the address bus contains a valid address. EADS# can only be driven after the system logic has taken control of the address bus by asserting AHOLD or BOFF# or by receiving HLDA. The processor responds to the sampling of EADS# and the address bus by driving HIT#, which indicates if the inquired cache line exists in the processor's cache, and HITM#, which indicates if it is in the modified state. If AHOLD or BOFF# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling EADS # two clock edges after AHOLD or BOFF # is sampled asserted. If the system logic asserts HOLD in order to execute a cache inquire cycle, the processor begins sampling EADS# two clock edges after the clock edge HLDA is asserted by the processor. EADS# is ignored during the following conditions:
s
Sampled
s
s s
One clock edge after the clock edge on which EADS# is sampled asserted Two clock edges after the clock edge on which ADS# is asserted When the processor is driving the address bus When the processor asserts HITM#
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Summary
EWBE# (External Write Buffer Empty)
Input
The system logic can negate EWBE# to the processor to indicate that its external write buffers are full and that additional data cannot be stored at this time. This causes the processor to delay the following activities until EWBE# is sampled asserted:
s
The commitment of write hit cycles to cache lines in the modified state or exclusive state in the processor's cache The decode and execution of an instruction that follows a currently-executing serializing instruction The assertion or negation of SMIACT# The entering of the Halt state and the Stop Grant state
s
s s
Negating EWBE# does not prevent the completion of any type of cycle that is currently in progress. Sampled The processor samples EWBE# on each clock edge that BRDY# is sampled asserted during all memory write cycles (except writeback cycles), I/O write cycles, and special bus cycles. If EWBE# is sampled negated, it is sampled on every clock edge until it is asserted, and then it is ignored until BRDY # is sampled asserted in the next write cycle or special cycle.
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5.21
Summary
FERR# (Floating-Point Error)
Output
The assertion of FERR # indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. This signal is provided to allow the system logic to handle this exception in a manner consistent with IBM-compatible PC/AT systems. See "Handling Floating-Point Exceptions" on page 189 for a system logic implementation that supports floating-point exceptions. The state of the numeric error (NE) bit in CR0 does not affect the FERR# signal. The processor ensures that FERR# does not glitch, enabling the signal to be used as a clocking source for system logic.
Driven
The processor asserts FERR # on the instruction boundary of the next floating-point instruction, MMX instruction, or WAIT instruction that occurs following the floating-point instruction that caused the unmasked floating-point exception--that is, FERR # is not asserted at the time the exception occurs. The IGNNE# signal does not affect the assertion of FERR#. FERR# is negated during the following conditions:
s
s
s
Following the successful execution of the floating-point instructions FCLEX, FINIT, FSAVE, and FSTENV Under certain circumstances, following the successful execution of the floating-point instructions FLDCW, FLDENV, and FRSTOR, which load the floating-point status word or the floating-point control word Following the falling transition of RESET
FERR# is always driven except in Tri-State Test mode. See "IGNNE# (Ignore Numeric Exception)" on page 100 for more details on floating-point exceptions.
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5.22
Summary
FLUSH# (Cache Flush)
Input
In response to sampling FLUSH# asserted, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle. (See Table 19 on page 119 for the bus definition of special cycles.) In addition, FLUSH # is sampled when RESET is negated to determine if the processor enters Tri-State Test mode. If FLUSH # is 0 during the falling transition of RESET, the processor enters Tri-State Test mode instead of performing the normal RESET functions.
Sampled
FLUSH # is sampled and latched as a falling edge-sensitive signal. During normal operation (not RESET), FLUSH # is sampled on every clock edge but is not recognized until the next instruction boundary. If FLUSH# is asserted synchronously, it can be asserted for a minimum of one clock. If FLUSH # is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. FLUSH# is also sampled during the falling transition of RESET. If RESET and FLUSH# are driven synchronously, FLUSH# is sampled on the clock edge prior to the clock edge on which RESET is sampled negated. If RESET is driven asynchronously, the minimum setup and hold time for FLUSH#, relative to the negation of RESET, is two clocks.
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5.23
Summary
HIT# (Inquire Cycle Hit)
Output
The processor asserts HIT# during an inquire cycle to indicate that the cache line is valid within the processor's instruction or data cache (also known as a cache hit). The cache line can be in the modified, exclusive, or shared state. HIT # is always driven -- except in Tri-State Test mode -- and only changes state the clock edge after the clock edge on which EADS# is sampled asserted. It is driven in the same state until the next inquire cycle.
Driven
5.24
Summary
HITM# (Inquire Cycle Hit To Modified Line)
Output
The processor asserts HITM # during an inquire cycle to indicate that the cache line exists in the processor's data cache in the modified state. The processor performs a writeback cycle as a result of this cache hit. If an inquire cycle hits a cache line that is currently being written back, the processor asserts HITM # but does not execute another writeback cycle. The system logic must not expect the processor to assert ADS# each time HITM# is asserted. HITM# is always driven--except in Tri-State Test mode--and, in particular, is driven to represent the result of an inquire cycle the clock edge after the clock edge on which EADS# is sampled asserted. If HITM # is negated in response to the inquire address, it remains negated until the next inquire cycle. If HITM# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last BRDY # of the writeback is sampled asserted.
Driven
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5.25
Summary
HLDA (Hold Acknowledge)
Output
When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an acknowledgment that these events have been completed. The processor does not assert HLDA until the completion of a locked sequence of cycles. While HLDA is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor. The following signals are floated when HLDA is asserted: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #, D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and W/R#. The processor ensures that HLDA does not glitch.
Driven
HLDA is always driven except in Tri-State Test mode. If a processor cycle is in progress while HOLD is sampled asserted, HLDA is asserted one clock edge after the last BRDY # of the cycle is sampled asserted. If the bus is idle, HLDA is asserted one clock edge after HOLD is sampled asserted. HLDA is negated one clock edge after the clock edge on which HOLD is sampled negated. The assertion of HLDA is independent of the sampled state of BOFF#. The processor floats the bus every clock in which HLDA is asserted.
5.26
Summary
HOLD (Bus Hold Request)
Input
The system logic can assert HOLD to gain control of the processor's bus. When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an acknowledgment that these events have been completed. The processor samples HOLD on every clock edge. If a processor cycle is in progress while HOLD is sampled asserted, HLDA is asserted one clock edge after the last BRDY # of the cycle is sampled asserted. If the bus is idle, HLDA is asserted one clock edge after HOLD is sampled asserted. HOLD is recognized while INIT and RESET are sampled asserted. Signal Descriptions 99
Sampled
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5.27
Summary
IGNNE# (Ignore Numeric Exception)
Input
IGNNE#, in conjunction with the numeric error (NE) bit in CR0, is used by the system logic to control the effect of an unmasked floating-point exception on a previous floating-point instruction during the execution of a floating-point instruction, MMX instruction, or the WAIT instruction--hereafter referred to as the target instruction. If an unmasked floating-point exception is pending and the target instruction is considered error-sensitive, then the relationship between NE and IGNNE# is as follows:
s
If NE = 0, then: * If IGNNE# is sampled asserted, the processor ignores the floating-point exception and continues with the execution of the target instruction. * If IGNNE# is sampled negated, the processor waits until it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted. If IGNNE# is sampled asserted while waiting, the processor ignores the floating-point exception and continues with the execution of the target instruction. If INTR, SMI#, NMI, or INIT is sampled asserted while waiting, the processor handles its assertion appropriately. If NE = 1, the processor invokes the INT 10h exception handler.
s
If an unmasked floating-point exception is pending and the target instruction is considered error-insensitive, then the processor ignores the floating-point exception and continues with the execution of the target instruction. FERR # is not affected by the state of the NE bit or IGNNE #. FERR # is always asserted at the instruction boundary of the target instruction that follows the floating-point instruction that caused the unmasked floating-point exception. This signal is provided to allow the system logic to handle exceptions in a manner consistent with IBM-compatible PC/AT systems.
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Sampled
The processor samples IGNNE # as a level-sensitive input on every clock edge. The system logic can drive the signal either s y n ch ro n o u s ly o r a s y n ch ro n o u s ly. I f i t i s a s s e r t e d asynchronously, it must be asserted for a minimum pulse width of two clocks.
5.28
Summary
INIT (Initialization)
Input
The assertion of INIT causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address FFFF_FFF0h--the same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMX state, Model-Specific Registers, the CD and NW bits of the CR0 register, and other specific internal resources. INIT can be used as an accelerator for 80286 code that requires a reset to exit from Protected mode back to Real mode.
Sampled
INIT is sampled and latched as a rising edge-sensitive signal. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY # is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
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5.29
Summary
INTR (Maskable Interrupt)
Input
INTR is the system's maskable interrupt input to the processor. When the processor samples and recognizes INTR asserted, the processor executes a pair of interrupt acknowledge bus cycles and then jumps to the interrupt service routine specified by the interrupt number that was returned during the interrupt acknowledge sequence. The processor only recognizes INTR if the interrupt flag (IF) in the EFLAGS register equals 1. The processor samples INTR as a level-sensitive input on every clock edge, but the interrupt request is not recognized until the next instruction boundary. The system logic can drive INTR either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. In order to be recognized, INTR must remain asserted until an interrupt acknowledge sequence is complete.
Sampled
5.30
Summary
INV (Invalidation Request)
Input
During an inquire cycle, the state of INV determines whether an addressed cache line that is found in the processor's instruction or data cache transitions to the invalid state or the shared state. If INV is sampled asserted during an inquire cycle, the processor transitions the cache line (if found) to the invalid state, regardless of its previous state. If INV is sampled negated during an inquire cycle, the processor transitions the cache line (if found) to the shared state. In either case, if the cache line is found in the modified state, the processor writes it back to memory before changing its state.
Sampled
INV is sampled on the clock edge on which EADS# is sampled asserted.
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5.31
Summary
KEN# (Cache Enable)
Input
If KEN # is sampled asserted, it indicates that the address presented by the processor is cacheable. If KEN # is sampled asserted and the processor intends to perform a cache-line fill (signified by the assertion of CACHE#), the processor executes a 32-byte burst read cycle and expects to sample BRDY # asserted a total of four times. If KEN # is sampled negated during a read cycle, a single-transfer cycle is executed and the processor does not cache the data. For write cycles, CACHE# is asserted to indicate the current bus cycle is a modified cache-line writeback. KEN# is ignored during writebacks. If PCD is asserted during a bus cycle, the processor does not cache any data read during that cycle, regardless of the state of KEN#. (See "PCD (Page Cache Disable)" on page 107 for more details.) If the processor has sampled the state of KEN# during a cycle, and that cycle is aborted due to the sampling of BOFF # asserted, the system logic must ensure that KEN# is sampled in the same state when the processor restarts the aborted cycle.
Sampled
KEN# is sampled on the clock edge on which the first BRDY# or NA # of a read cycle is sampled asserted. If the read cycle is a burst, KEN # is ignored during the last three assertions of BRDY #. KEN # is sampled during read cycles only when CACHE# is asserted.
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5.32
Summary
LOCK# (Bus Lock)
Output
The processor asserts LOCK# during a sequence of bus cycles to ensure that the cycles are completed without allowing other bus masters to intervene. Locked operations consist of two to five bus cycles. LOCK# is asserted during the following operations:
s s s s s
An interrupt acknowledge sequence Descriptor Table accesses Page Directory and Page Table accesses XCHG instruction An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processor's cache are flushed and invalidated from the cache prior to the locked operation. If the cache line is in the modified state, it is written back and invalidated prior to the locked operation. Likewise, any data read during a locked operation is not cached. The processor ensures that LOCK# does not glitch. Driven and Floated During a locked cycle, LOCK# is asserted off the same clock edge on which ADS# is asserted and remains asserted until the last BRDY# of the last bus cycle is sampled asserted. The processor negates LOCK# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. LOCK# is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD. When LOCK# is floated due to BOFF# sampled asserted, the system logic is responsible for preserving the lock condition while LOCK# is in the high-impedance state.
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5.33
Summary
M/IO# (Memory or I/O)
Output
The processor drives M/IO# during a bus cycle to indicate whether it is addressing the memory or I/O space. If M/IO# = 1, the processor is addressing memory or a memory-mapped I/O port as the result of an instruction fetch or an instruction that loads or stores data. If M/IO# = 0, the processor is addressing an I/O port during the execution of an I/O instruction. In addition, M/IO# is used to define other bus cycles, including interrupt acknowledge and special cycles. (See Table 19 on page 119 for more details.) M/IO# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. M/IO# is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. M/IO# is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.
Driven and Floated
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5.34
Summary
NA# (Next Address)
Input
System logic asserts NA# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ADS#, along with address and status signals, can be asserted as early as one clock edge after NA# is sampled asserted if the processor is prepared to start a new cycle. Because the processor allows a maximum of two cycles to be in progress at a time, the assertion of NA# is sampled while two cycles are in progress but ADS# is not asserted until the completion of the first cycle. NA# is sampled every clock edge during bus cycles, starting one clock edge after the clock edge that negates ADS#, until the last expected BRDY# of the last executed cycle is sampled asserted (with the exception of the clock edge after the clock edge that negates the ADS# for a second pending cycle). Because the processor latches NA# when sampled, the system logic only needs to assert NA# for one clock.
Sampled
5.35
Summary
NMI (Non-Maskable Interrupt)
Input
When NMI is sampled asserted, the processor jumps to the interrupt service routine defined by interrupt number 02h. Unlike the INTR signal, software cannot mask the effect of NMI if it is sampled asserted by the processor. However, NMI is temporarily masked upon entering System Management Mode (SMM). In addition, an interrupt acknowledge cycle is not executed because the interrupt number is predefined. If NMI is sampled asserted while the processor is executing the interrupt service routine for a previous NMI, the subsequent NMI remains pending until the completion of the execution of the IRET instruction at the end of the interrupt service routine.
Sampled
NMI is sampled and latched as a rising edge-sensitive signal. During normal operation, NMI is sampled on every clock edge but is not recognized until the next instruction boundary. If it is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. Signal Descriptions Chapter 5
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5.36
Summary
PCD (Page Cache Disable)
Output
The processor drives PCD to indicate the operating system's specification of cacheability for the page being addressed. System logic can use PCD to control external caching. If PCD is asserted, the addressed page is not cached. If PCD is negated, the cacheability of the addressed page depends upon the state of CACHE# and KEN#. The state of PCD depends upon the processor's operating mode and the state of certain bits in its control registers and TLB as follows:
s
s
In Real mode, or in Protected and Virtual-8086 modes while paging is disabled (PG bit in CR0 set to 0): PCD output = CD bit in CR0 In Protected and Virtual-8086 modes while caching is enabled (CD bit in CR0 set to 0) and paging is enabled (PG bit in CR0 set to 1): * For accesses to I/O space, page directory entries, and other non-paged accesses: PCD output = PCD bit in CR3 * For accesses to 4-Kbyte page table entries or 4-Mbyte pages: PCD output = PCD bit in page directory entry * For accesses to 4-Kbyte pages: PCD output = PCD bit in page table entry
Driven and Floated
PCD is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. PCD is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.
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5.37
Summary
PCHK# (Parity Check)
Output
The processor asserts PCHK# during read cycles if it detects an even parity error on one or more valid bytes of D[63:0] during a read cycle. (Even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) The processor checks data parity for the data bytes that are valid, as defined by BE[7:0]#, the byte enables. PCHK# is always driven but is only asserted for memory and I/O re a d b u s cy c l es a n d t he se c o n d cy c l e of a n i n t e r ru p t acknowledge sequence. PCHK# is not driven during any type of write cycles or special bus cycles. The processor does not take an internal exception as the result of detecting a data parity error, and system logic must respond appropriately to the assertion of this signal. The processor ensures that PCHK# does not glitch, enabling the signal to be used as a clocking source for system logic.
Driven
PCHK# is always driven except in Tri-State Test mode. For each BRDY# returned to the processor during a read cycle with a parity error detected on the data bus, PCHK# is asserted for one clock, one clock edge after BRDY# is sampled asserted.
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5.38
Summary
PWT (Page Writethrough)
Output
The processor drives PWT to indicate the operating system's specification of the writeback state or writethrough state for the page being addressed. PWT, together with WB/WT#, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. (See "WB/WT# (Writeback or Writethrough)" on page 116 for more details.) The state of PWT depends upon the processor's operating mode and the state of certain bits in its control registers and TLB as follows:
s
s
In Real mode, or in Protected and Virtual-8086 modes while paging is disabled (PG bit in CR0 set to 0): PWT output = 0 (writeback state) In Protected and Virtual-8086 modes while paging is enabled (PG bit in CR0 set to 1): * For accesses to I/O space, page directory entries, and other non-paged accesses: PWT output = PWT bit in CR3 * For accesses to 4-Kbyte page table entries or 4-Mbyte pages: PWT output = PWT bit in page directory entry * For accesses to 4-Kbyte pages: PWT output = PWT bit in page table entry
Driven and Floated
PWT is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. PWT is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.
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5.39
Summary
RESET (Reset)
Input
When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the MMX state, and all registers, and then the processor jumps to address FFFF_FFF0h to start instruction execution. The signals BRDYC# and FLUSH# are sampled during the falling transition of RESET to select the drive strength of selected output signals and to invoke the Tri-State Test mode, respectively. (See these signal descriptions for more details.)
Sampled
RESET is sampled as a level-sensitive input on every clock edge. System logic can drive the signal either synchronously or asynchronously. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. During a warm reset, while CLK and V CC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation.
5.40
Summary
RSVD (Reserved)
Reserved signals are a special class of pins that can be treated in one of the following ways:
s
s
s
As no-connect (NC) pins, in which case these pins are left unconnected As pins connected to the system logic as defined by the industry-standard Pentium interface (Socket 7) Any combination of NC and Socket 7 pins
In any case, if the RSVD pins are treated accordingly, the normal operation of the AMD-K6 processor is not adversely affected in any manner. See "Pin Designations" on page 269 for a list of the locations of the RSVD pins.
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5.41
Summary
SCYC (Split Cycle)
Output
The processor asserts SCYC during misaligned, locked transfers on the D[63:0] data bus. The processor generates additional bus cycles to complete the transfer of misaligned data. For purposes of bus cycles, the term aligned means:
s s
Any 1-byte transfers 2-byte and 4-byte transfers that lie within 4-byte address boundaries 8-byte transfers that lie within 8-byte address boundaries
s
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated off the clock edge on which NA# or the last expected BRDY# of the entire locked sequence is sampled asserted. SCYC is only valid during locked memory cycles. SCYC is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.
5.42
Summary
SMI# (System Management Interrupt)
Input, Internal Pullup
The assertion of SMI# causes the processor to enter System Management Mode (SMM). Upon recognizing SMI#, the processor performs the following actions, in the order shown: 1. Flushes its instruction pipelines 2. Completes all pending and in-progress bus cycles 3. Acknowledges the interrupt by asserting SMIACT# after sampling EWBE# asserted 4. Saves the internal processor state in SMM memory 5. Disables interrupts by clearing the interrupt flag (IF) in EFLAGS and disables NMI interrupts 6. Jumps to the entry point of the SMM service routine at the SMM base physical address which defaults to 0003_8000h in SMM memory
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See "System Management Mode (SMM)" on page 193 for more details regarding SMM. Sampled SMI# is sampled and latched as a falling edge-sensitive signal. SMI# is sampled on every clock edge but is not recognized until the next instruction boundary. If SMI# is to be recognized on the instruction boundary associated with a BRDY#, it must be sampled asserted a minimum of three clock edges before the BRDY# is sampled asserted. If it is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks followed by an assertion of a minimum of two clocks. A second assertion of SMI# while in SMM is latched but is not recognized until the SMM service routine is exited.
5.43
Summary
SMIACT# (System Management Interrupt Active)
Output
The processor acknowledges the assertion of SMI# with the assertion of SMIACT# to indicate that the processor has entered System Management Mode (SMM). The system logic can use SMIACT# to enable SMM memory. See "SMI# (System Management Interrupt)" on page 111 for more details. See "System Management Mode (SMM)" on page 193 for more details regarding SMM.
Driven
The processor asserts SMIACT# after the last BRDY# of the last pending bus cycle is sampled asserted (including all pending write cycles) and after EWBE# is sampled asserted. SMIACT# remains asserted until after the last BRDY# of the last pending bus cycle associated with exiting SMM is sampled asserted. SMIACT# remains asserted during any flush, internal snoop, or writeback cycle due to an inquire cycle.
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5.44
Summary
STPCLK# (Stop Clock)
Input, Internal Pullup
The assertion of STPCLK# causes the processor to enter the Stop Grant state, during which the processor's internal clock is stopped. From the Stop Grant state, the processor can subsequently transition to the Stop Clock state, in which the bus clock CLK is stopped. Upon recognizing STPCLK#, the processor performs the following actions, in the order shown: 1. Flushes its instruction pipelines 2. Completes all pending and in-progress bus cycles 3. Acknowledges the STPCLK# assertion by executing a Stop Grant special bus cycle (see Table 19 on page 119) 4. Stops its internal clock after BRDY# of the Stop Grant special bus cycle is sampled asserted and after EWBE# is sampled asserted 5. Enters the Stop Clock state if the system logic stops the bus clock CLK (optional) See "Clock Control" on page 223 for more details regarding clock control.
Sampled
STPCLK# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. System logic can drive the signal either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. STPCLK# must remain asserted until recognized, which is indicated by the completion of the Stop Grant special cycle.
5.45
Summary
TCK (Test Clock)
Input, Internal Pullup
TCK is the clock for boundary-scan testing using the Test Access Port (TAP). See "Boundary-Scan Test Access Port (TAP)" on page 205 for details regarding the operation of the TAP controller. The processor always samples TCK, except while TRST# is asserted. Signal Descriptions 113
Sampled
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5.46
Summary
TDI (Test Data Input)
Input, Internal Pullup
T D I i s t h e s e r i a l t e s t d a t a a n d i n s t r u c t i o n i n p u t fo r boundary-scan testing using the Test Access Port (TAP). See "Boundary-Scan Test Access Port (TAP)" on page 205 for details regarding the operation of the TAP controller. The processor samples TDI on every rising TCK edge but only while in the Shift-IR and Shift-DR states.
Sampled
5.47
Summary
TDO (Test Data Output)
Output
TDO is the serial test data and instruction out put for boundary-scan testing using the Test Access Port (TAP). See "Boundary-Scan Test Access Port (TAP)" on page 205 for details regarding the operation of the TAP controller. The processor drives TDO on every falling TCK edge but only while in the Shift-IR and Shift-DR states. TDO is floated at all other times.
Driven and Floated
5.48
Summary
TMS (Test Mode Select)
Input, Internal Pullup
TMS specifies the test function and sequence of state changes for boundary-scan testing using the Test Access Port (TAP). See "Boundary-Scan Test Access Port (TAP)" on page 205 for details regarding the operation of the TAP controller. The processor samples TMS on every rising TCK edge. If TMS is sampled High for five or more consecutive clocks, the TAP controller enters its Test-Logic-Reset state, regardless of the controller state. This action is the same as that achieved by asserting TRST#.
Sampled
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5.49
Summary
TRST# (Test Reset)
Input, Internal Pullup
The assertion of TRST# initializes the Test Access Port (TAP) by resetting its state machine to the Test-Logic-Reset state. See "Boundary-Scan Test Access Port (TAP)" on page 205 for details regarding the operation of the TAP controller. TRST# is a completely asynchronous input that does not require a minimum setup and hold time relative to TCK. See Table 54 on page 253 for the minimum pulse width requirement.
Sampled
5.50
Summary
VCC2DET (VCC2 Detect)
Output
VCC2DET is tied to VSS (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the VCC2 pins. The VCC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the VCC3 pins. VCC2DET always equals 0 and is never floated--even during Tri-State Test mode.
Driven
5.51
Summary
W/R# (Write/Read)
Output
The processor drives W/R# to indicate whether it is performing a write or a read cycle on the bus. In addition, W/R# is used to define other bus cycles, including interrupt acknowledge and special cycles (see Table 19 on page 119 for more details). W/R# is driven off the same clock edge as ADS# and remains in the same state until the clock edge on which NA# or the last expected BRDY# of the cycle is sampled asserted. W/R# is driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. W/R# is floated off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in response to HOLD.
Driven and Floated
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5.52
Summary
WB/WT# (Writeback or Writethrough)
Input
WB/WT#, together with PWT, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. If WB/WT# = 0 or PWT = 1 during a cacheable read miss or write hit to a shared cache line, the accessed line is cached in the shared state. This is referred to as the writethrough state because all write cycles to this cache line are driven externally on the bus. If WB/WT# = 1 and PWT = 0 during a cacheable read miss or a write hit to a shared cache line, the accessed line is cached in the exclusive state. Subsequent write hits to the same line cause its state to transition from exclusive to modified. This is referred to as the writeback state because the data cache can contain modified cache lines that are subject to be written back--referred as a writeback cycle--as the result of an inquire cycle, an internal snoop, a flush operation, or the WBINVD instruction.
Sampled
WB/WT# is sampled on the clock edge that the first BRDY# or NA# of a bus cycle is sampled asserted. If the cycle is a burst read, WB/WT# is ignored during the last three assertions of BRDY #. WB /WT# is sampled during mem ory re ad and non-writeback write cycles and is ignored during all other types of cycles.
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Table 14. Input Pin Types
Name A20M# AHOLD BF[2:0] BOFF# BRDY# BRDYC# CLK EADS# EWBE# FLUSH# HOLD
Notes:
Type Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Clock Synchronous Synchronous Asynchronous Synchronous
Note Note 1 Note 4 INIT INTR INV
Name IGNNE#
Type Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous
Note Note 1 Note 2 Note 1
KEN# Note 7 NA# NMI RESET SMI# Note 2, 3 STPCLK# WB/WT#
Note 2 Note 5, 6 Note 2 Note 1
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. 6. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 7. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET. If asserted asynchronously, BRDYC# must meet a minimum setup and hold time of two clocks relative to the negation of RESET.
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Table 15. Output Pin Float Conditions
Name A[4:3] ADS# ADSC# APCHK# BE[7:0]# BREQ CACHE# D/C# FERR# HIT#
Notes:
Floated At: (Note 1) HLDA, AHOLD, BOFF# HLDA, BOFF# HLDA, BOFF# Always Driven HLDA, BOFF# Always Driven HLDA, BOFF# HLDA, BOFF# Always Driven Always Driven
Note Note 2, 3 Note 2 Note 2 Note 2 Note 2 Note 2
Name HITM# HLDA LOCK# M/IO# PCD PCHK# PWT SCYC SMIACT# W/R#
Floated At: (Note 1) Always Driven Always Driven HLDA, BOFF# HLDA, BOFF# HLDA, BOFF# Always Driven HLDA, BOFF# HLDA, BOFF# Always Driven HLDA, BOFF#
Note
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
1. All outputs except VCC2DET and TDO float during Tri-State Test mode. 2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted. 3. Floated off the clock edge that AHOLD is sampled asserted.
Table 16. Input/Output Pin Float Conditions
Name A[31:5] AP D[63:0] DP[7:0]
Notes:
Floated At: (Note 1) HLDA, AHOLD, BOFF# HLDA, AHOLD, BOFF# HLDA, BOFF# HLDA, BOFF#
Note Note 2,3 Note 2,3 Note 2 Note 2
1. All outputs except VCC2DET and TDO float during Tri-State Test mode. 2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted. 3. Floated off the clock edge that AHOLD is sampled asserted.
Table 17. Test Pins
Name TCK TDI TDO TMS TRST# Type Clock Input Output Input Input Sampled on the rising edge of TCK Driven on the falling edge of TCK Sampled on the rising edge of TCK Asynchronous (Independent of TCK) Note
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Table 18. Bus Cycle Definition
Bus Cycle Initiated M/IO# Code Read, Instruction Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special Cycle Interrupt Acknowledge I/O Read I/O Write Memory Read, Data Cache Line Fill Memory Read, Noncacheable Memory Read, Noncacheable Memory Write, Data Cache Writeback Memory Write, Noncacheable
Note:
Generated by Processor D/C# 0 0 0 0 0 1 1 1 1 1 1 1 W/R# 0 0 0 1 0 0 1 0 0 0 1 1 CACHE# 0 1 x 1 1 1 1 0 1 x 0 1
Generated by System KEN# 0 x 1 x x x x 0 x 1 x x
1 1 1 0 0 0 0 1 1 1 1 1
x means "don't care"
Table 19. Special Cycles
CACHE# 1 1 1 1 1 1 M/IO# W/R# BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# D/C# Special Cycle Stop Grant Flush Acknowledge (FLUSH# sampled asserted) Writeback (WBINVD instruction) Halt Flush (INVD, WBINVD instruction) Shutdown
Note:
1 0 0 0 0 0
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
0 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 1 0
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
x means "don't care"
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KEN# x x x x x x
A4
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6
Bus Cycles
The following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. A representative set of bus cycles is illustrated.
6.1
Timing Diagrams
The timing diagrams illustrate the signals on the external local bus as a function of time, as measured by the bus clock (CLK). Throughout this chapter, the term clock refers to a signal bus-clock cycle. A clock extends from one rising CLK edge to the next rising CLK edge. The processor samples and drives most signals relative to the rising edge of CLK. The exceptions to this rule include the following:
s s
s
BF[2:0]--Sampled on the falling edge of RESET FLUSH#, BRDYC#--Sampled on the falling edge of RESET, also sampled on the rising edge of CLK All inputs and outputs are sampled relative to TCK in Boundary-Scan Test Mode. Inputs are sampled on the rising edge of TCK, outputs are driven off of the falling edge of TCK.
For each signal in the timing diagrams, the High level represents 1, the Low level represents 0, and the Middle level represents the floating (high-impedance) state. When both the High and Low levels are shown, the meaning depends on the signal. A single signal indicates `don't care'. In the case of bus activity, if both High and Low levels are shown, it indicates the processor, alternate master, or system logic is driving a value, but this value may or may not be valid. (For example, the value on the address bus is valid only during the assertion of ADS#, but addresses are also driven on the bus at other times.) Figure 43 on page 122 defines the different waveform representations.
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Waveform
Description
Don't care or bus is driven
Signal or bus is changing from Low to High
Signal or bus is changing from High to Low
Bus is changing
Bus is changing from valid to invalid
Signal or bus is floating
Denotes multiple clock periods
Figure 43. Waveform Definitions For all active-High signals, the term asserted means the signal is in the High-voltage state and the term negated means the signal is in the Low-voltage state. For all active-Low signals, the term asserted means the signal is in the Low-voltage state and the term negated means the signal is in the High-voltage state.
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6.2
Bus State Machine Diagram
Bus State Addr No Pending Request? Yes Address Branch Condition
Idle Idle
Data Data
Yes
Last BRDY# Asserted?
No
NA# Sampled Asserted? Data-NA# Yes
No
Yes
Last BRDY# Asserted? No
Data-NA# Requested
Yes Pending Request? Pipe-A Yes Pipeline Address No NA# Sampled Asserted? No
Pipe-D Pipeline Data No Last BRDY# Asserted? Yes Trans Yes NA# Sampled Asserted? No Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted. Transition Yes Bus Transition? No
Figure 44. Bus State Machine Diagram Chapter 6 Bus Cycles 123
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Idle
The processor does not drive the system bus in the Idle state and remains in this state until a new bus cycle is requested. The processor enters this state off the clock edge on which the last BRDY# of a cycle is sampled asserted during the following conditions:
s s
The processor is in the Data state The processor is in the Data-NA# Requested state and no internal pending cycle is requested
In addition, the processor is forced into this state when the system logic asserts RESET or BOFF#. The transition to this state occurs on the clock edge on which RESET or BOFF# is sampled asserted. Address In this state, the processor drives ADS# to indicate the beginning of a new bus cycle by validating the address and control signals. The processor remains in this state for one clock and unconditionally enters the Data state on the next clock edge. In the Data state, the processor drives the data bus during a write cycle or expects data to be returned during a read cycle. The processor remains in this state until either NA# or the last BRDY# is sampled asserted. If the last BRDY# is sampled asserted or both the last BRDY# and NA# are sampled asserted on the same clock edge, the processor enters the Idle state. If NA# is sampled asserted first, the processor enters the Data-NA# Requested state. If the processor samples NA# asserted while in the Data state and the current bus cycle is not completed (the last BRDY# is not sampled asserted), it enters the Data-NA# Requested state. The processor remains in this state until either the last BRDY# is sampled asserted or an internal pending cycle is requested. If the last BRDY# is sampled asserted before the processor drives a new bus cycle, the processor enters the Idle state (no internal pending cycle is requested) or the Address state (processor has a internal pending cycle). In this state, the processor drives ADS# to indicate the beginning of a new bus cycle by validating the address and control signals. In this state, the processor is still waiting for the current bus cycle to be completed (until the last BRDY# is
Data
Data-NA# Requested
Pipeline Address
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sampled asserted). If the last BRDY# is not sampled asserted, the processor enters the Pipeline Data state. If the processor samples the last BRDY# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. A bus transition is required when the data bus direction changes between bus cycles, such as a memory write cycle followed by a memory read cycle. If a bus transition is required, the processor enters the Transition state for one clock to prevent data bus contention. If a bus transition is not required, the processor enters the Data state. The processor does not transition to the Data-NA# Requested state from the Pipeline Address state because the processor does not begin sampling NA# until it has exited the Pipeline Address state. Pipeline Data Two bus cycles are concurrently executing in this state. The processor cannot issue any additional bus cycles until the current bus cycle is completed. The processor drives the data bus during write cycles or expects data to be returned during read cycles for the current bus cycle until the last BRDY# of the current bus cycle is sampled asserted. If the processor samples the last BRDY# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. If the bus transition is required, the processor enters the Transition state for one clock to prevent data bus contention. If a bus transition is not required, the processor enters the Data state (NA# was not sampled asserted) or the Data-NA# Requested state (NA# was sampled asserted). Transition The processor enters this state for one clock during data bus transitions and enters the Data state on the next clock edge if NA# is not sampled asserted. The sole purpose of this state is to avoid bus contention caused by bus transitions during pipeline operation.
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6.3
Memory Reads and Writes
The AMD-K6 processor performs single or burst memory bus cycles. The single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. Misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. A burst cycle consists of four back-to-back 8-byte (64-bit) transfers on the data bus.
Single-Transfer Memory Read and Write
Figure 45 on page 127 shows a single-transfer read from memory, followed by two single-transfer writes to memory. For the memory read cycle, the processor asserts ADS# for one clock to validate the bus cycle and also drives A[31:3], BE[7:0]#, D/C#, W/R#, and M/IO# to the bus. The processor then waits for the system logic to return the data on D[63:0] (with DP[7:0] for parity checking) and assert BRDY#. The processor samples BRDY# on every clock edge starting with the clock edge after the clock edge that negates ADS#. See "BRDY# (Burst Ready)" on page 88. During the read cycle, the processor drives PCD, PWT, and CACHE# to indicate its caching and cache-coherency intent for the access. The system logic returns KEN# and WB/WT# to either confirm or change this intent. If the processor asserts PCD and negates CACHE#, the accesses are non-cacheable, even though the system logic asserts KEN# during the BRDY# to indicate its support for cacheability. The processor (which drives CACHE#) and the system logic (which drives KEN#) must agree in order for an access to be cacheable. The processor can drive another cycle (in this example, a write cycle) by asserting ADS# off the next clock edge after BRDY# is sampled asserted. Therefore, an idle clock is guaranteed between any two bus cycles. The processor drives D[63:0] with valid data one clock edge after the clock edge on which ADS# is asserted. To minimize CPU idle times, the system logic stores the address and data in write buffers, returns BRDY#, and performs the store to memory later. If the processor samples EWBE# negated during a write cycle, it suspends certain activities until EWBE# is sampled asserted. See "EWBE# (External Write Buffer Empty)" on page 95. In Figure 45, the second write cycle occurs during the execution of a serializing instruction. The processor delays the following cycle until EWBE# is sampled asserted.
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Read Cycle
ADDR DATA IDLE
Write Cycle
ADDR DATA DATA IDLE
Write Cycle (Next Cycle Delayed by EWBE#)
ADDR DATA DATA IDLE IDLE IDLE IDLE IDLE ADDR
CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BREQ D[63:0] DP[7:0] CACHE# EWBE# KEN# BRDY# WB/WT#
Figure 45. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
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Misaligned Single-Transfer Memory Read and Write
Figure 46 on page 129 shows a misaligned (split) memory read followed by a misaligned memory write. Any cycle that is not aligned as defined in "SCYC (Split Cycle)" on page 111 is considered misaligned. When the processor encounters a misaligned access, it determines the appropriate pair of bus cycles -- each with its own ADS# and BRDY# -- required to complete the access. The AMD-K6 processor performs misaligned memory reads and memory writes using least-significant bytes (LSBs) first followed by most-significant bytes (MSBs). Table 20 shows the order. In the first memory read cycle in Figure 46, the processor reads the least-significant bytes. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to read the most-significant bytes to complete the misaligned transfer. Table 20. Bus-Cycle Order During Misaligned Transfers
Type of Access Memory Read Memory Write First Cycle LSBs LSBs Second Cycle MSBs MSBs
Similarly, the misaligned memory write cycle in Figure 46 transfers the LSBs to the memory bus first. In the next cycle, after the processor samples BRDY# asserted, the MSBs are written to the memory bus.
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Memory Read (Misaligned) CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY# LSB MSB
Memory Write (Misaligned)
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE
LSB
MSB
Figure 46. Misaligned Single-Transfer Memory Read and Write
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Burst Reads and Pipelined Burst Reads
Figure 47 on page 131 shows normal burst read cycles and a pipelined burst read cycle. The AMD-K6 processor drives CACHE# and ADS# together to specify that the current bus cycle is a burst cycle. If the processor samples KEN# asserted with the first BRDY#, it performs burst transfers. During the burst transfers, the system logic must ignore BE[7:0]# and must return all eight bytes beginning at the starting address the processor asserts on A[31:3]. Depending on the starting address, the system logic must determine the successive quadword addresses (A[4:3]) for each transfer in a burst, as shown in Table 21. The processor expects the second, third, and fourth quadwords to occur in the sequences shown in Table 21. Table 21. A[4:3] Address-Generation Sequence During Bursts
Address Driven By Processor on A[4:3] Quadword 1 00b 01b 10b 11b
Note:
A[4:3] Addresses of Subsequent Quadwords* Generated By System Logic Quadword 2 01b 00b 11b 10b Quadword 3 10b 11b 00b 01b Quadword 4 11b 10b 01b 00b
*
quadword = 8 bytes
In Figure 47, the processor drives CACHE# throughout all burst read cycles. In the first burst read cycle, the processor drives ADS# and CACHE#, then samples BRDY# on every clock edge starting with the clock edge after the clock edge that negates ADS#. The processor samples KEN# asserted on the clock edge on which the first BRDY# is sampled asserted, executes a 32-byte burst read cycle, and expects to sample BRDY# a total of four times. An ideal no-wait state access is shown in Figure 47, whereas most system logic solutions add wait states between the transfers. The second burst read cycle illustrates a similar sequence, but the processor samples NA# asserted on the same clock edge that the first BRDY# is sampled asserted. NA# assertion indicates the system logic is requesting the processor to output the next address early (also known as a pipeline transfer request). Without waiting for the current cycle to complete, the processor drives ADS# and related signals for the next burst cycle. Pipelining can reduce CPU cycle-to-cycle idle times. 130 Bus Cycles Chapter 6
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Burst Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# NA# D[63:0] CACHE# KEN# BRDY# DATA1 ADDR1
Burst Read
Pipelined Burst Read
ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA DATA PIPE-A DATA DATA DATA DATA IDLE -NA
ADDR2
ADDR3
DATA2
DATA3
Figure 47. Burst Reads and Pipelined Burst Reads
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Burst Writeback
Figure 48 on page 133 shows a burst read followed by a writeback transaction. The AMD-K6 processor initiates writebacks under the following conditions:
s
s
Replacement--If a cache-line fill is initiated for a cache line currently filled with valid entries, the processor uses a least-recently-allocated (LRA) algorithm to select a line for replacement. Before a replacement is made to a data cache line that is in the modified state, the modified line is scheduled to be written back to memory. Internal Snoop--The processor snoops the data cache whenever an instruction-cache line is read, and it snoops the instruction cache whenever a data cache line is written. This snooping is performed to determine whether the same address is stored in both caches, a situation that is taken to imply the occurrence of self-modifying code. If a snoop hits a data cache line in the modified state, the line is written back to memory before being invalidated. WBINVD Instruction--When the processor executes a WBINVD instruction, it writes back all modified lines in the data cache and then invalidates all lines in both caches. Cache Flush--When the processor samples FLUSH# asserted, it executes a flush acknowledge special cycle and writes back all modified lines in the data cache and then invalidates all lines in both caches.
s
s
The processor drives writeback cycles during inquire or cache flush cycles. The writeback shown in Figure 48 is caused by a cache-line replacement. The processor completes the burst read cycle that fills the cache line. Immediately following the burst read cycle is the burst writeback cycle that represents the modified line to be written back to memory. D[63:0] are driven one clock edge after the clock edge on which ADS# is asserted and are subsequently changed off the clock edge on which each BRDY# assertion of the burst cycle is sampled.
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Burst Read
ADDR DATA DATA DATA DATA IDLE ADDR
Burst Writeback from L1 Cache
DATA DATA DATA DATA IDLE
CLK A[31:3] BE[7:0]# ADS# CACHE# M/IO# D/C# W/R# D[63:0] KEN# BRDY# WB/WT#
Figure 48. Burst Writeback due to Cache-Line Replacement
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6.4
I/O Read and Write
The processor accesses I/O when it executes an I/O instruction (for example, IN or OUT). Figure 49 shows an I/O read followed by an I/O write. The processor drives M/IO# Low and D/C# High during I/O cycles. In this example, the first cycle shows a single wait state I/O read cycle. It follows the same sequence as a single-transfer memory read cycle. The processor drives ADS# to initiate the bus cycle, then it samples BRDY# on every clock edge starting with the clock edge after the clock edge that negates ADS#. The system logic must return BRDY# to complete the cycle. When the processor samples BRDY# asserted, it can assert ADS# for the next cycle off the next clock edge. (In this example, an I/O write cycle.) The I/O write cycle is similar to a memory write cycle, but the processor drives M/IO# low during an I/O write cycle. The processor asserts ADS# to initiate the bus cycle. The processor drives D[63:0] with valid data one clock edge after the clock edge on which ADS# is asserted. The system logic must assert BRDY# when the data is properly stored to the I/O destination. The processor samples BRDY# on every clock edge starting with the clock edge after the clock edge that negates ADS#. In this example, two wait states are inserted while the processor waits for BRDY# to be asserted.
I/O Read Cycle
ADDR DATA DATA IDLE ADDR DATA
Basic I/O Read and Write
I/O Write Cycle
DATA DATA IDLE
CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY#
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Misaligned I/O Read and Write
Table 22 shows the misaligned I/O read and write cycle order executed by the AMD-K6. In Figure 50, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle. Table 22. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access I/O Read I/O Write First Cycle LSBs LSBs Second Cycle MSBs MSBs
Misaligned I/O Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# LOCK# SCYC D[63:0] BRDY# LSB MSB
Misaligned I/O Write
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE
LSB
MSB
Figure 50. Misaligned I/O Transfer
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6.5
Inquire and Bus Arbitration Cycles
The AMD-K6 processor provides built-in level-one data and instruction caches. Each cache is 32 Kbytes and two-way set-associative. The system logic or other bus master devices can initiate an inquire cycle to maintain cache/memory coherency. In response to the inquire cycle, the processor compares the inquire address with its cache tag addresses in both caches, and, if necessary, updates the MESI state of the cache line and performs writebacks to memory. An inquire cycle can be initiated by asserting AHOLD, BOFF#, or HOLD. AHOLD is exclusively used to support inquire cycles. During AHOLD-initiated inquire cycles, the processor only floats the address bus. BOFF# provides the fastest access to the bus because it aborts any processor cycle that is in-progress, whereas AHOLD and HOLD both permit an in-progress bus cycle to complete. During HOLD-initiated and BOFF#-initiated inquire cycles, the processor floats all of its bus-driving signals.
Hold and Hold Acknowledge Cycle
The system logic or another bus device can assert HOLD to initiate an inquire cycle or to gain full control of the bus. When the AMD-K6 processor samples HOLD asserted, it completes any in-progress bus cycle and asserts HLDA to acknowledge release of the bus. The processor floats the following signals off the same clock edge that HLDA is asserted:
s s s s s s s
A[31:3] ADS# AP# BE[7:0]# CACHE# D[63:0] D/C#
s s s s s s s
DP[7:0] LOCK# M/IO# PCD PWT SCYC W/R#
Figure 51 on page 137 shows a basic HOLD/HLDA operation. In this example, the processor samples HOLD asserted during the memory read cycle. It continues the current memory read cycle until BRDY# is sampled asserted. The processor drives HLDA and floats its outputs one clock edge after the last BRDY# of the cycle is sampled asserted. The system logic can assert HOLD for as long as it needs to utilize the bus. The processor samples HOLD on every clock edge but does not assert HLDA until any in-progress cycle or sequence of locked cycles is completed. 136 Bus Cycles Chapter 6
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When the processor samples HOLD negated during a hold acknowledge cycle, it negates HLDA off the next clock edge. The processor regains control of the bus and can assert ADS# off the same clock edge on which HLDA is negated.
CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] HOLD HLDA BRDY#
Figure 51. Basic HOLD/HLDA Operation
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HOLD-Initiated Inquire Hit to Shared or Exclusive Line
Figure 52 on page 139 shows a HOLD-initiated inquire cycle. In this example, the processor samples HOLD asserted during the burst memory read cycle. The processor completes the current cycle (until the last expected BRDY# is sampled asserted), asserts HLDA and floats its outputs as described on page 136. The system logic drives an inquire cycle within the hold acknowledge cycle. It asserts EADS#, which validates the inquire address on A[31:5]. If EADS# is sampled asserted before HOLD is sampled negated, the processor recognizes it as a valid inquire cycle. In Figure 52, the processor asserts HIT# and negates HITM# on the clock edge after the clock edge on which EADS# is sampled asserted, indicating the current inquire cycle hit a shared or exclusive cache line. (Shared and exclusive cache lines in the processor data or instruction cache have the same contents as the data in the external memory.) During an inquire cycle, the processor samples INV to determine whether the addressed cache line found in the processor's instruction or data cache transitions to the invalid state or the shared state. In this example, the processor samples INV asserted with EADS#, which invalidates the cache line. The system logic can negate HOLD off the same clock edge on which EADS# is sampled asserted. The processor continues driving HIT# in the same state until the next inquire cycle. HITM# is not asserted unless HIT# is asserted.
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Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV
Inquire
Figure 52. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
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HOLD-Initiated Inquire Hit to Modified Line
Figure 53 on page 141 shows the same sequence as Figure 52 on page 139, but in Figure 53 the inquire cycle hits a modified line and the processor asserts both HIT# and HITM#. In this example, the processor performs a writeback cycle immediately after the inquire cycle. It updates the modified cache line to the external memory (normally, level-two cache or DRAM). The processor uses the address (A[31:5]) that was latched during the inquire cycle to perform the writeback cycle. The processor asserts HITM# throughout the writeback cycle and negates HITM# one clock edge after the last expected BRDY# of the writeback is sampled asserted. When the processor samples EADS# during the inquire cycle, it also samples INV to determine the cache line MESI state after the inquire cycle. If INV is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid stat e, regardless of its previous sta te. The cache line invalidation operation is not visible on the bus. If INV is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. In Figure 53 the processor samples INV asserted during the inquire cycle. In a HOLD-initiated inquire cycle, the system logic can negate HOLD off the same clock edge on which EADS# is sampled asserted. The processor drives HIT# and HITM# on the clock edge after the clock edge on which EADS# is sampled asserted.
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Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV
Inquire
Writeback Cycle
Figure 53. HOLD-Initiated Inquire Hit to Modified Line
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AHOLD-Initiated Inquire Miss
AHOLD can be asserted by the system to initiate one or more inquire cycles. To allow the system to drive the address bus during an inquire cycle, the processor floats A[31:3] and AP off the clock edge on which AHOLD is sampled asserted. The data bus and all other control and status signals remain under the control of the processor and are not floated. This functionality allows a bus cycle in progress when AHOLD is sampled asserted to continue to completion. The processor resumes driving the address bus off the clock edge on which AHOLD is sampled negated. In Figure 54 on page 143, the processor samples AHOLD asserted during the memory burst read cycle, and it floats the address bus off the same clock edge on which it samples AHOLD asserted. While the processor still controls the bus, it completes the current cycle until the last expected BRDY# is sampled asserted. The system logic drives EADS# with an inquire address on A[31:5] during an inquire cycle. The processor samples EADS# asserted and compares the inquire address to its tag address in both the instruction and data caches. In Figure 54, the inquire address misses the tag address in the processor (both HIT# and HITM# are negated). Therefore, the processor proceeds to the next cycle when it samples AHOLD negated. (The processor can drive a new cycle by asserting ADS# off the same clock edge that it samples AHOLD negated.) For an AHOLD-initiated inquire cycle to be recognized, the processor must sample AHOLD asserted for at least two consecutive clocks before it samples EADS# asserted. If the processor detects an address parity error during an inquire cycle, APCHK# is asserted for one clock. The system logic must respond appropriately to the assertion of this signal.
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Read CLK A[31:3] BE[7:0]# AP APCHK# ADS# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV
Inquire
Figure 54. AHOLD-Initiated Inquire Miss
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AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
In Figure 55 on page 145, the processor asserts HIT# and negates HITM# off the clock edge after the clock edge on which EADS# is sampled asserted, indicating the current inquire cycle hits either a shared or exclusive line. (HIT# is driven in the same state until the next inquire cycle.) The processor samples INV asserted during the inquire cycle and transitions the line to the invalid state regardless of its previous state. During an AHOLD-initiated inquire cycle, the processor samples AHOLD on every clock edge until it is negated. In Figure 55, the processor asserts ADS# off the same clock on which AHOLD is sampled negated. If the inquire cycle hits a modified line, the processor performs a writeback cycle before it drives a new bus cycle. The next section describes the AHOLD-initiated inquire cycle that hits a modified line.
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Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV
Inquire
Figure 55. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
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AHOLD-Initiated Inquire Hit to Modified Line
Figure 56 on page 147 shows an AHOLD-initiated inquire cycle that hits a modified line. During the inquire cycle in this example, the processor asserts both HIT# and HITM# on the clock edge after the clock edge that it samples EADS# asserted. This condition indicates that the cache line exists in the processor's data cache in the modified state. If the inquire cycle hits a modified line, the processor performs a writeback cycle immediately after the inquire cycle to update the modified cache line to shared memory (normally level-two cache or DRAM). In Figure 56, the system logic holds AHOLD asserted throughout the inquire cycle and the processor writeback cycle. In this case, the processor is not driving the address bus during the writeback cycle because AHOLD is sampled asserted. The system logic writes the data to memory by using its latched copy of the inquire cycle address. If the processor samples AHOLD negated before it performs the writeback cycle, it drives the writeback cycle by using the address (A[31:5]) that it latched during the inquire cycle. If INV is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state (the cache invalidation operation is not visible on the bus). If INV is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. In either case, if the line is found in the modified state, the processor writes it back to memory before changing its state. Figure 56 shows that the processor samples INV asserted during the inquire cycle and invalidates the cache line after the inquire cycle.
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Burst Memory Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV
Inquire
Writeback
Figure 56. AHOLD-Initiated Inquire Hit to Modified Line
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AHOLD Restriction
When the system logic drives an AHOLD-initiated inquire cycle, it must assert AHOLD for at least two clocks before it asserts EADS#. This requirement guarantees the processor recognizes and responds to the inquire cycle properly. The processor's 32 address bus drivers turn on almost immediately after AHOLD is sampled negated. If the processor switches the data bus (D[63:0] and DP[7:0]) during a write cycle off the same clock edge that switches the address bus (A[31:3] and AP), the processor switches 102 drivers simultaneously, which can lead to ground-bounce spikes. Therefore, before negating AHOLD the following restrictions must be observed by the system logic:
s
When the system logic negates AHOLD during a write cycle, it must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled asserted (See Figure 57 on page 149). When the system logic negates AHOLD during a writeback cycle, it must ensure that AHOLD is not sampled negated on the clock edge on which ADS# is negated (See Figure 57). When a write cycle is pipelined into a read cycle, AHOLD must not be sampled negated on the clock edge after the clock edge on which the last BRDY# of the read cycle is sampled asserted to avoid the processor simultaneously driving the data bus (for the pending write cycle) and the address bus off this same clock edge.
s
s
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CLK ADS# W/R# HITM# EADS# D[63:0] BRDY#
Legal AHOLD negation during write cycle
AHOLD
Illegal AHOLD negation during write cycle The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.
The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled asserted.
Figure 57. AHOLD Restriction
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Bus Backoff (BOFF#)
BOFF# provides the fastest response among bus-hold inputs. Either the system logic or another bus master can assert BOFF# to gain control of the bus immediately. BOFF# is also used to resolve potential deadlock problems that arise as a result of inquire cycles. The processor samples BOFF# on every clock e d g e . I f B O F F # i s s a m p l e d a s s e r t e d , t h e p ro c e s s o r unconditionally aborts any cycles in progress and transitions to a bus hold state. (See "BOFF# (Backoff)" on page 87.) Figure 58 on page 151 shows a read cycle that is aborted when the processor samples BOFF# asserted even though BRDY# is sampled asserted on the same clock edge. The read cycle is restarted after BOFF# is sampled negated (KEN# must be in the same state during the restarted cycle as its state during the aborted cycle). During a BOFF#-initiated inquire cycle that hits a shared or exclusive line, the processor samples BOFF# negated and restarts any bus cycle that was aborted when BOFF# was asserted. If a BOFF#-initiated inquire cycle hits a modified line, the processor performs a writeback cycle before it restarts the aborted cycle. If the processor samples BOFF# asserted on the same clock edge that it asserts ADS#, ADS# is floated but the system logic may erroneously interpret ADS# as asserted. In this case, the system logic must properly interpret the state of ADS# when BOFF# is negated.
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Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BOFF# D[63:0] BRDY#
Back Off Cycle
Restart Read Cycle
Figure 58. BOFF# Timing
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Locked Cycles
The processor asserts LOCK# during a sequence of bus cycles to ensure the cycles are completed without allowing other bus masters to intervene. Locked operations can consist of two to five cycles. LOCK# is asserted during the following operations:
s s s s s
An interrupt acknowledge sequence Descriptor Table accesses Page Directory and Page Table accesses XCHG instruction An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processor's cache are flushed and invalidated from the cache prior to the locked operation. If the cache line is in the modified state, it is written back and invalidated prior to the locked operation. Likewise, any data read during a locked operation is not cached. The processor negates LOCK# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. The processor asserts SCYC during misaligned locked transfers on the D[63:0] data bus. The processor generates additional bus cycles to complete the transfer of misaligned data. Basic Locked Operation Figure 59 on page 153 shows a pair of read-write bus cycles. It represents a typical read-modify-write locked operation. The processor asserts LOCK# off the same clock edge that it asserts ADS# of the first bus cycle in the locked operation and holds it asserted until the last expected BRDY# of the last bus cycle in the locked operation is sampled asserted. (The processor negates LOCK# off the same clock edge.)
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Locked Write Cycle Locked Read Cycle ADDR DATA DATA DATA IDLE IDLE ADDR DATA DATA DATA IDLE IDLE ADDR CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# SCYC D[63:0] BRDY#
Figure 59. Basic Locked Operation
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Locked Operation with BOFF# Intervention
Figure 60 on page 155 shows BOFF# asserted within a locked read-write pair of bus cycles. In this example, the processor asserts LOCK# with ADS# to drive a locked memory read cycle followed by a locked memory write cycle. During the locked memory write cycle in this example, the processor samples BOFF# asserted. The processor immediately aborts the locked memory write cycle and floats all its bus-driving signals, including LOCK#. The system logic or another bus master can initiate an inquire cycle or drive a new bus cycle one clock edge after the clock edge on which BOFF# is sampled asserted. If the system logic drives a BOFF#-initiated inquire cycle and hits a modified line, the processor performs a writeback cycle before it restarts the locked cycle (the processor asserts LOCK# during the writeback cycle). In Figure 60, the processor immediately restarts the aborted locked write cycle by driving the bus off the clock edge on which BOFF# is sampled negated. The system logic must ensure the processor results for interrupted and uninterrupted locked cycles are consistent. That is, the system logic must guarantee the memory accessed by the processor is not modified during the time another bus master controls the bus.
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Locked Read Cycle CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# BOFF# D[63:0] BRDY#
Aborted Write Cycle
Restart Write Cycle
Figure 60. Locked Operation with BOFF# Intervention
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Interrupt Acknowledge
In response to recognizing the system's maskable interrupt (INTR), the processor drives an interrupt acknowledge cycle at t h e n e x t i n s t r u c t i o n b o u n d a ry. D u r i n g a n i n t e r r u p t acknowledge cycle, the processor drives a locked pair of read cycles as shown in Figure 61 on page 157. The first read cycle is not functional, and the second read cycle returns the interrupt number on D[7:0] (00h-FFh). Table 23 shows the state of the signals during an interrupt acknowledge cycle. Table 23. Interrupt Acknowledge Operation Definition
Processor Outputs D/C# M/IO# W/R# BE[7:0]# A[31:3] D[63:0] First Bus Cycle Low Low Low EFh 0000_0000h (ignored) Second Bus Cycle Low Low Low FEh (low byte enabled) 0000_0000h Interrupt number expected from interrupt controller on D[7:0]
The system logic can drive INTR either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. To ensure it is recognized, INTR must remain asserted until an interrupt acknowledge sequence is complete.
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Interrupt Acknowledge Cycles CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# LOCK# INTR D[63:0] KEN# BRDY# Interrupt Number
Figure 61. Interrupt Acknowledge Operation
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6.6
Special Bus Cycles
The AMD-K6 processor drives special bus cycles that include stop grant, flush acknowledge, cache writeback invalidation, halt, cache invalidation, and shutdown cycles. During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and A[31:3] are driven to differentiate among the special cycles, as shown in Table 24. The system logic must return BRDY# in response to all processor special cycles. Table 24. Encodings For Special Bus Cycles
BE[7:0]# FBh EFh F7h FBh FDh FEh
Note:
A[4:3]* 10b 00b 00b 00b 00b 00b
Special Bus Cycle Stop Grant Writeback Halt Flush Shutdown
Cause STPCLK# sampled asserted WBINVD instruction HLT instruction INVD,WBINVD instruction Triple fault
Flush Acknowledge FLUSH# sampled asserted
*
A[31:5] = 0
Basic Special Bus Cycle
Figure 62 on page 159 shows a basic special bus cycle. The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (See Table 24). A halt special cycle is generated after the processor executes the HLT instruction. If the processor samples FLUSH# asserted, it writes back any data cache lines that are in the modified state and invalidates all lines in the instruction and data cache. The processor then drives a flush acknowledge special cycle. If the processor executes a WBINVD instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines.
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Halt Cycle CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BRDY#
A[4:3] = 00b FBh
Figure 62. Basic Special Bus Cycle (Halt Cycle)
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Shutdown Cycle
In Figure 63, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle follows in the second half. The processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (INT 8), which amounts to a triple fault. When the processor encounters a triple fault, it stops its activity on the bus and generates the shutdown special bus cycle (BE[7:0]# = FEh). The system logic must assert NMI, INIT, RESET, or SMI# to get the processor out of the shutdown state.
Shutdown Occurs (Triple Fault) Shutdown Special Cycle
CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# D[63:0] KEN# BRDY#
A[4:3] = 00b FEh
Figure 63. Shutdown Cycle
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Stop Grant and Stop Clock States
Figure 64 on page 162 and Figure 65 on page 163 show the processor transition from normal execution to the Stop Grant state, then to the Stop Clock state, back to the Stop Grant state, and finally back to normal execution. The series of transitions begins when the processor samples STPCLK# asserted. On recognizing a STPCLK# interrupt at the next instruction retirement boundary, the processor performs the following actions, in the order shown: 1. Its instruction pipelines are flushed 2. All pending and in-progress bus cycles are completed 3. The STPCLK# assertion is acknowledged by executing a Stop Grant special bus cycle 4. Its internal clock is stopped after BRDY# of the Stop Grant special bus cycle is sampled asserted and after EWBE# is sampled asserted 5. The Stop Clock state is entered if the system logic stops the bus clock CLK (optional) STPCLK# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. The system logic drives the signal either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. STPCLK# must remain asserted until recognized, which is indicated by the completion of the Stop Grant special cycle.
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STPCLK# Sampled Asserted CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY#
Stop Grant Special Cycle
Stop Clock
A[4:3] = 10b FBh
Figure 64. Stop Grant and Stop Clock Modes, Part 1
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Stop Clock CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY#
Stop Grant State (Re-entered after PLL stabilization)
STPCLK# Sampled Negated
Normal
Figure 65. Stop Grant and Stop Clock Modes, Part 2
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INIT-Initiated Transition from Protected Mode to Real Mode
INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode. The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFF0h--the same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMX state, Model-Specific Registers (MSRs), the CD and NW bits of the CR0 register, the time stamp counter, and other specific internal resources. Figure 66 on page 165 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INIT. The sampling of INIT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
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INIT Sampled Asserted CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] KEN# BRDY# INIT
Code Fetch
FFFF_FFF0
Figure 66. INIT-Initiated Transition from Protected Mode to Real Mode
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7
Power-on Configuration and Initialization
On power-on the system logic must reset the AMD-K6 processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX state, and all registers. Then the processor jumps to address FFFF_FFF0h to start instruction execution.
7.1
Signals Sampled During the Falling Transition of RESET
FLUSH# FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Tri-State Test mode. If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFF0h to start instruction execution. (See "Built-In Self-Test (BIST)" on page 203 for more details.) If FLUSH# is Low during the falling transition of RESET, the processor enters Tri-State Test mode. (See "Tri-State Test Mode" on page 204 and "FLUSH# (Cache Flush)" on page 97 for more details.) The in t er n a l op erat i n g f re q u e n cy o f t h e p roce s so r is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See "BF[2:0] (Bus Frequency)" on page 86 for the processor-clock to bus-clock ratios.) BRDYC# is sampled on the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM#, and W/R#. If BRDYC# is Low during the fall of RESET, these outputs are configured using higher drive strengths than the standard strength. If BRDYC# is High during the fall of RESET, the standard strength is selected. (See "BRDYC# (Burst Ready Copy)" on page 89 for more details.)
BF[2:0]
BRDYC#
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7.2
RESET Requirements
During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification. (See "CLK Switching Characteristics" on page 241 for clock specifications. See "Electrical Data" on page 233 for VCC specifications.) D u r i n g a wa r m re s e t w h i l e C L K a n d V C C a re w i t h i n specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation.
7.3
State of Processor After RESET
Table 25 show s the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 25. Output Signal State After RESET
Signal A[31:3], AP ADS#, ADSC# APCHK# BE[7:0]# BREQ CACHE# D/C# D[63:0], DP[7:0] FERR# HIT# HITM# State Floating High High Floating Low High Low Floating High High High HLDA LOCK# M/IO# PCD PCHK# PWT SCYC SMIACT# TDO VCC2DET W/R# Signal State Low High Low Low High Low Low High Floating Low Low
Output Signals
Registers
Table 26 on page 169 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET.
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Table 26. Register State After RESET
Register GDTR IDTR TR LDTR EIP EFLAGS EAX EBX ECX EDX ESI EDI EBP ESP CS SS DS ES FS GS FPU Stack R7-R0 FPU Control Word FPU Status Word FPU Tag Word FPU Instruction Pointer FPU Data Pointer FPU Opcode Register CR0 CR2
Notes:
State (hex) base:0000_0000h limit:0FFFFh base:0000_0000h limit:0FFFFh 0000h 0000h FFFF_FFF0h 0000_0002h 0000_0000h 0000_0000h 0000_0000h 0000_056Xh 0000_0000h 0000_0000h 0000_0000h 0000_0000h F000h 0000h 0000h 0000h 0000h 0000h 0000_0000_0000_0000_0000h 0040h 0000h 5555h 0000_0000_0000h 0000_0000_0000h 000_0000_0000b 6000_0010h 0000_0000h
Notes
1
2
3 3 3 3 3 3 3 4
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6 processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
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Table 26. Register State After RESET (continued)
Register CR3 CR4 DR7 DR6 DR3 DR2 DR1 DR0 MCAR MCTR TR12 TSC WHCR
Notes:
State (hex) 0000_0000h 0000_0000h 0000_0400h FFFF_0FF0h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h
Notes
3 3 3 3 3
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6 processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
7.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address FFFF_FFF0h--the same instruction execution starting point used after RESET. Unlike RESET, the p r o c e s s o r p re s e rve s t h e c o n t e n t s o f i t s c a ch e s , t h e floating-point state, the MMX state, MSRs, and the CD and NW bits of the CR0 register. The edge-sensitive interrupts FLUSH# and SMI# are sampled and preserved during the INIT process and are handled accordingly after the initialization is complete. However, the processor resets any pending NMI interrupt upon sampling INIT asserted. INIT can be used as an accelerator for 80286 code that requires a reset to exit from Protected mode back to Real mode.
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8
Cache Organization
The following sections describe the basic architecture and resources of the AMD-K6 processor internal caches. The performance of the AMD-K6 processor is enhanced by a writeback level-one (L1) cache. The cache is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache, each with two-way set associativity (See Figure 67). The cache line size is 32 bytes, and lines are prefetched from main memory using an efficient, pipelined burst transaction. As the instruction cache is filled, each instruction byte is analyzed for instruction boundaries using predecode logic. Predecoding annotates each instruction byte with information that later enables the decoders to efficiently decode multiple instructions simultaneously. Translation lookaside buffers (TLB) are also used to translate linear addresses to physical addresses. The instruction cache is associated with a 64-entry TLB while the data cache is associated with a 128-entry TLB.
32-Kbyte Instruction Cache Tag RAM Way 0 State Tag Bit RA Way 1 State Bit
64-Entry TLB
System Bus Interface Unit
Pre-Decode Instruction Cache
Processor Core
128-Entry TLB Tag RAM MESI Tag Bits RA 32-Kbyte Data Cache MESI Bits
Way 0
Way 1
Figure 67. Cache Organization
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The processor cache design takes advantage of a sectored organization (See Figure 68). Each sector consists of 64 bytes configured as two 32-byte cache lines. The two cache lines of a sector share a common tag but have separate MESI (modified, exclusive, shared, invalid) bits that track the state of each cache line. Instruction Cache Line
Tag Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ Address Cache Line 2 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit ........ Byte 0 Predecode Bits 1 MESI Bit
Data Cache Line
Tag Address Cache Line 1 Cache Line 2 Byte 31 Byte 31 Byte 30 Byte 30 ........ ........ ........ ........ Byte 0 Byte 0 2 MESI Bits 2 MESI Bits
Note: Instruction-cache lines have only two coherency states (valid or invalid) rather than the four MESI coherency states of data-cache lines. Only two states are needed for the instruction cache because these lines are read-only.
Figure 68. Cache Sector Organization
8.1
MESI States in the Data Cache
The state of each line in the caches is tracked by the MESI bits. The coherency of these states or MESI bits is maintained by internal processor snoops and external inquiries by the system logic. The following four states are defined for the data cache:
s
s
s
s
Modified--This line has been modified and is different from main memory. Exclusive--This line is not modified and is the same as main memory. If this line is written to, it becomes Modified. Shared--If a cache line is in the shared state it means that the same line can exist in more than one cache system. Invalid--The information in this line is not valid.
8.2
Predecode Bits
Decoding x86 instructions is particularly difficult because the instructions vary in length, ranging from 1 to 15 bytes long. Predecode logic supplies the predecode bits associated with each instruction byte. The predecode bits indicate the number
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of bytes to the start of the next x86 instruction. The predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. The predecode bits use memory separate from the 32-Kbyte instruction cache. The predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in Figure 68 on page 172.
8.3
Cache Operation
The operating modes for the caches are configured by software using the not writethrough (NW) and cache disable (CD) bits of control register 0 (CR0 bits 29 and 30 respectively). These bits are used in all operating modes. When the CD and NW bits are both set to 0, the cache is fully enabled. This is the standard operating mode for the cache. If a read miss occurs when the processor reads from the cache, a line fill takes place. Write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. Note: A write allocate operation can modify the behavior of write misses to the cache. See "Write Allocate" on page 177. When CD is set to 0 and NW is set to 1, an invalid mode of operation exists that causes a general protection fault to occur. When CD is set to 1 (disabled) and NW is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. The processor reads from the cache and, if a read miss occurs, no line fills take place. Write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. When the CD and NW bits are both set to 1, the cache is fully disabled. Even though the cache is disabled, the contents are not necessarily invalid. The processor reads from the cache and, if a read miss occurs, no line fills take place. If a write hit occurs, the cache is updated but an external memory update does not occur. If a data line is in the exclusive state during a write hit, the MESI bits are changed to the modified state. Write misses access memory directly.
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The operating system can control the cacheability of a page. The paging mechanism is controlled by CR3, the Page Directory Entry (PDE), and the Page Table Entry (PTE). Within CR3, PDE, and PTE are Page Cache Disable (PCD) and Page Writethrough (PWT) bits. The values of the PCD and PWT bits used in Table 27 through Table 29 are taken from either the PTE or PDE. For more information see the descriptions of PCD and PWT on pages 107 and 109, respectively. Table 27 through Table 29 describe the logic that determines the cacheability of a cycle and how that cacheability is affected by the PCD bits, the PWT bits, the PG bit of CR0, the CD bit of CR0, writeback cycles, the Cache Inhibit (CI) bit of Test Register 12 (TR12), and unlocked memory reads. Table 27 describes how the PWT signal is driven based on the values of the PWT bits and the PG bit of CR0. Table 27. PWT Signal Generation
PWT Bit* 1 0 1 0
Note:
PG Bit of CR0 1 1 0 0
PWT Signal High Low Low Low
* PWT is taken from PTE or PDE
Table 28 describes how the PCD signal is driven based on the values of the CD bit of CR0, the PCD bits, and the PG bit of CR0. Table 28. PCD Signal Generation
CD Bit of CR0 1 0 0 0 0
Note:
PCD Bit* X 1 0 1 0
PG Bit of CR0 X 1 1 0 0
PCD Signal High High Low Low Low
* PCD is taken from PTE or PDE
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Table 29 describes how the CACHE# signal is driven based on writeback cycles, the CI bit of TR12, unlocked memory reads, and the PCD signal. Table 29. CACHE# Signal Generation
Writeback Cycle 1 0 0 0 0 0 0 0 0 CI Bit of TR12 X 1 0 1 0 1 0 1 0 Unlocked PCD Signal Memory Reads X 1 1 0 0 1 1 0 0 X High High High High Low Low Low Low CACHE# Low High High High High High Low High High
Cache-Related Signals
Complete descriptions of the signals that control cacheability and cache coherency are given on the following pages:
s s s s s s s s s s
CACHE#--page 90 EADS#--page 94 FLUSH#--page 97 HIT#--page 98 HITM#--page 98 INV--page 102 KEN#--page 103 PCD--page 107 PWT--page 109 WB/WT#--page 116
8.4
Cache Disabling
To completely disable all cache accesses, the CD and NW bits must be set to 1 and the cache must be completely flushed. There are two different methods for flushing the cache. The first method relies on the system logic and the second relies on software.
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For the system logic to flush the cache, the processor must sample FLUSH# asserted. In this method, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle (See Table 19 on page 119). Software can use two different instructions to flush the cache. Both the WBINVD and INVD instructions cause all cache lines to be marked invalid. The WBINVD instruction causes all modified lines to first be written back to memory. The INVD instruction invalidates all cache lines without writing modified lines back to memory. Any area of system memory can be cached. However, the processor prevents caching of locked operations and TLB reads, the operating system can prevent caching of certain pages by setting the PCD and PWT bits in the PDE or PTE, and system logic can prevent caching of certain bus cycles by negating the KEN# input signal with the first BRDY# or NA# of a cycle.
8.5
Cache-Line Fills
When the CPU needs to read memory, the processor drives a read cycle onto the bus. If the cycle is cacheable the CPU asserts CACHE#. The system logic also has control of the cacheability of bus cycles. If it determines the address is cacheable, system logic asserts the KEN# signal and the appropriate value of WB/WT#. One of two events takes place next. If the cycle is not cacheable, a non-pipelined, single-transfer read takes place. The processor waits for the system logic to return the data and assert a single BRDY# (See Figure 45 on page 127). If the cycle is cacheable, the processor executes a 32-byte burst read cycle. The processor expects to sample BRDY# asserted a total of four times for a burst read cycle to take place (See Figure 47 on page 131). Instruction-cache line fills initiate 32-byte transfers from memory (one burst cycle) on the bus. Data-cache line fills also initiate 32-byte transfers on the bus. If the data-cache line being filled replaces a modified line, the prior contents of the line are copied to a 32-byte writeback (copyback) buffer in the bus interface unit while the new line is being read.
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8.6
Cache-Line Replacements
As programs execute and task switches occur, some cache lines eventually require replacement. Instruction cache lines are replaced using a Least Recently Used (LRU) algorithm. If line replacement is required, lines are replaced when read cache misses occur. The data cache uses a slightly different approach to line replacement. If a miss occurs, and a replacement is required, lines are replaced by using a Least Recently Allocated (LRA) algorithm. Two forms of cache misses and associated cache fills can take place--a sector replacement and a cache line replacement. In the case of a sector replacement, the miss is due to a tag mismatch, in which case the required cache line is filled from external memory, and the cache line within the sector that was not required is marked as invalid. In the case of a cache line replacement, the address matches the tag, but the requested cache line is marked as invalid. The required cache line is filled from external memory, and the cache line within the sector that is not required remains in the same cache state.
8.7
Write Allocate
Write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the L1 data cache. In this case, the processor performs a burst read cycle to fetch the data-cache line addressed by the pending write cycle. The data associated w i t h t h e p e n d i n g w r i t e cy c l e i s m e r g e d w i t h t h e recently-allocated data-cache line and stored in the processor's L1 data cache. The final MESI state of the cache line depends on the state of the WB/WT# and PWT signals during the burst read cycle and the subsequent cache write hit (See Table 30 on page 182 to determine the cache-line states and the access types following a cache read miss and cache write hit). During write allocates, a 32-byte burst read cycle is executed in place of a non-burst write cycle. While the burst read cycle generally takes longer to execute than the write cycle, performance gains are realized on subsequent write cycle hits
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to the write-allocated cache line. Due to the nature of software, memory accesses tend to occur in proximity of each other (principle of locality). The likelihood of additional write hits to the write-allocated cache line is high. The following is a description of three mechanisms by which the AMD-K6 processor performs write allocations. A write allocate is performed when any one or more of these mechanisms indicates that a pending write is to a cacheable area of memory. Write to a Cacheable Page Every time the processor performs a cache line fill, the address of the page in which the cache line resides is saved in the Cacheability Control Register (CCR). The page address of subsequent write cycles is compared with the page address stored in the CCR. If the two addresses are equal, then the processor performs a write allocate because the page has already been determined to be cacheable. When the processor performs a cache line fill from a different page than the address saved in the CCR, the CCR is updated with the new page address. Write to a Sector If the address of a pending write cycle matches the tag address of a valid cache sector, but the addressed cache line within the sector is marked invalid (a sector hit but a cache line miss), then the processor performs a write allocate. The pending write cycle is determined to be cacheable because the sector hit indicates the presence of at least one valid cache line in the sector. The two cache lines within a sector are guaranteed by design to be within the same page. The Write Handling Control Register (WHCR) is a MSR that contains three fields -- the WCDE bit, the Write Allocate Enable Limit (WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit (See Figure 69 on page 179). For proper functionality, always program the WCDE bit to 0.
Write Allocate Limit
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63
9
8 0
7 WAELIM
1
0
W A E 1 5 M
Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program to 0 8 Write Allocate Enable Limit 7-1 Write Allocate Enable 15-to-16-Mbyte 0
Note: Hardware RESET initializes this MSR to all zeros.
Figure 69. Write Handling Control Register (WHCR) The WAELIM field is 7 bits wide. This field, multiplied by 4 Mbytes, defines an upper memory limit. Any pending write cycle that addresses memory below this limit causes the processor to perform a write allocate. Write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanisms--Write to a Cacheable Page and Write to a Sector. The maximum value of this memory limit is ((27 - 1) * 4 Mbytes) = 508 Mbytes. When all the bits in this field are set to 0, all memory is above this limit and this mechanism for allowing write allocate is effectively disabled. The Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit is used to enable write allocations for the memory write cycles that address the 1 Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit must be set to 1 to allow write allocate in this memory area. This bit is provided to account for a small number of uncommon memory-mapped I/O adapters that use this particular memory address space. If the system contains one of these peripherals, the bit should be set to 0. The WAE15M bit is ignored if the value in the WAELIM field is set to less than 16 Mbytes. By definition a write allocate is never performed in the memory area between 640 Kbytes and 1 Mbyte unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanisms--Write to a Cacheable Page and Write to a Sector. It is not considered safe to perform Chapter 8 Cache Organization 179
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write allocations between 640 Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered a non-cacheable region of memory. Figure 70 shows the logic flow for all the mechanisms involved with write allocate for memory bus cycles. The left side of the diagram (the text) describes the conditions that need to be true in order for the value of that line to be a 1. Items 1 to 3 of the diagram are related to general cache operation and items 4 to 11 are related to the write allocate mechanisms. Fo r m o re i n f o r m a t i o n a b o u t w r i t e a l l o c a t e , s e e t h e Implementation of Write Allocate in the K86TM Processors Application Note, order# 21326.
1) CD Bit of CR0. 2) PCD Signal 3) CI Bit of TR12 4) Write to Cacheable Page (CCR) 5) Write to a Sector 6) WCDE Bit 7) Less Than Limit (WAELIM) 8) Between 640 Kbytes and 1 Mbyte 9) Between 15-16 Mbytes 10) Write Allocate Enable 15-16 Mbyte (WAE15M) Perform Write Allocate
Figure 70. Write Allocate Logic Mechanisms and Conditions Descriptions of the Logic Mechanisms and Conditions 1. CD Bit of CR0--When the cache disable (CD) bit within control register 0 (CR0) is set to 1, the cache fill mechanism for both reads and writes is disabled, therefore write allocate does not occur. 2. PCD Signal--When the PCD (page cache disable) signal is driven High, caching for that page is disabled even if KEN# is sampled asserted, therefore write allocate does not occur. 3. CI Bit of TR12--When the cache inhibit bit of Test Register 12 is set to 1, the L1 caches are disabled, therefore write allocate does not occur. 4. Write to a Cacheable Page (CCR)--A write allocate is performed if the processor knows that a page is cacheable. The CCR is used to store the page address of the last cache fill for a read miss. See "Write to a Cacheable Page" on page 178 for a detailed description of this condition. 180 Cache Organization Chapter 8
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5. Write to a Sector--A write allocate is performed if the address of a pending write cycle matches the tag address of a valid cache sector but the addressed cache line within the sector is invalid. See "Write to a Sector" on page 178 for a detailed description of this condition. 6. WCDE Bit--For proper functionality, always program bit 8 of WHCR to 0. 7. Less Than Limit (WAELIM)--The write allocate limit mechanism determines if the memory area being addressed is less than the limit set in the WAELIM field of WHCR. If the address is less than the limit, write allocate for that memory address is performed as long as conditions 9 and 10 do not prevent write allocate. 8. Between 640 Kbytes and 1 Mbyte --Write allocate is not performed in the memory area between 640 Kbytes and 1 Mbyte. It is not considered safe to perform write allocations between 640 Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because this area of memory is considered a non-cacheable region of memory. 9. Between 15-16 Mbytes--If the address of a pending write cycle is in the 1 Mbyte of memory between 15 Mbytes and 16 Mbytes, and the WAE15M bit is set to 1, write allocate for this cycle is enabled. 10. Write Allocate Enable 15-16 Mbytes (WAE15M)--This condition is associated with the Write Allocate Limit mechanism and affects write allocate only if the limit specified by the WAELIM field is greater than or equal to 16 Mbytes. If the memory address is between 15 Mbytes and 16 Mbytes, and the WAE15M bit in the WHCR is set to 0, write allocate for this cycle is disabled.
8.8
Prefetching
The AMD-K6 processor performs instruction cache prefetching for sector replacements only -- as opposed to cache-line replacements. The cache prefetching results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. Furthermore, the prefetch of the second cache line is initiated only in the forward direction--that is, only if the requested cache line is the first position within the sector. From the perspective of the external
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bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as p i p e l in e d cy c le s . The b u rst re a d cy c l e s d o n o t o c c u r back-to-back (wait states occur) if the processor is not ready to start a new cycle, if higher priority data read or write requests exist, or if NA# (next address) was sampled negated. Wait states can also exist between burst cycles if the processor samples AHOLD or BOFF# asserted.
8.9
Cache States
Table 30 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. The table includes the correspondence between MESI states and writethrough or writeback states for lines in the data cache.
Table 30. Data Cache States for Read and Write Accesses
Type Cache State Before Access invalid Read Miss Cache Read Read Hit Write Miss Cache Write
Notes:
Access Type1 single read burst read2 (cacheable) - - - single write4 cache update and single write cache update
Cache State After Access MESI State invalid shared or exclusive3 shared exclusive modified invalid shared or exclusive3 modified Writeback Writethrough State - writethrough or writeback3 writethrough writeback writeback - writethrough or writeback3 writeback
invalid shared exclusive modified invalid shared exclusive or modified
Write Hit
Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read. If CACHE# is driven Low and KEN# is sampled asserted. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. A write cycle occurs only if the write allocate conditions as specified in "Write Allocate" on page 177 are not met. - Not applicable or none.
1. 2. 3. 4.
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8.10
Cache Coherency
Different ways exist to maintain coherency between the system memory and cache memories. Inquire cycles, internal snoops, FLUSH#, WBINVD, INVD, and line replacements all prevent inconsistencies between memories.
Inquire Cycles
Inquire cycles are bus cycles initiated by system logic. These inquiries ensure coherency between the caches and main memory. In systems with multiple caching masters, system logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus and then driving EADS#, INV (optional), and an inquire address (A[31:5]). This type of bus cycle causes the processor to compare the tags for both its instruction and data caches with the inquire address. If there is a hit to a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. If the compare hits a modified line in the data cache, the processor asserts HIT# and HITM#. If HITM# is asserted, the processor writes the modified line back to memory. If INV was sampled asserted with EADS#, a hit invalidates the line. If INV was sampled negated with EADS#, a hit leaves the line in the shared state or transitions it from the exclusive or modified to shared state. Internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. It is used to maintain coherency between the L1 instruction and data caches. The processor automatically snoops its instruction cache during read or write misses to its data cache, and it snoops its data cache during read misses to its instruction cache. Table 31 on page 185 summarizes the actions taken during this internal snooping. If an internal snoop hits its target, the processor does the following:
s
Internal Snooping
Data cache snoop during an instruction-cache read miss--If modified, the line in the data cache is written back to memory. Regardless of its state, the data-cache line is invalidated and the instruction cache performs a burst cycle read from memory. Cache Organization 183
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s
Instruction cache snoop during a data cache miss--The line in the instruction cache is marked invalid, and the data-cache read or write is performed from memory.
FLUSH#
In response to sampling FLUSH# asserted, the processor writes back any data cache lines that are in the modified state and then marks all lines in the instruction and data caches as invalid. These x86 instructions cause all cache lines to be marked as invalid. WBINVD writes back modified lines before marking all cache lines invalid. INVD does not write back modified lines. Replacing lines in the instruction or data cache, according to the line replacement algorithms described in "Cache-Line Fills" on page 176, ensures coherency between main memory and the caches. Table 31 on page 185 shows all possible cache-line states before and after cache snoop or invalidation operations performed with inquire cycles. This table shows all of the conditions for writethroughs and writebacks to memory.
WBINVD and INVD
Cache-Line Replacement
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Table 31. Cache States for Inquiries, Snoops, Invalidation, and Replacement
Type of Operation Cache State Before Operation shared or exclusive modified shared or exclusive modified shared or exclusive modified shared or exclusive modified - shared or exclusive modified Cache State After Operation Memory Access MESI State INV=0 INV=1 INV=0 INV=1 shared invalid shared invalid Writeback Writethrough State writethrough invalid writethrough invalid
Inquire Cycle
- burst write (writeback) - burst write (writeback) - burst write (writeback) - burst write (writeback) - - burst write (writeback)
Internal Snoop
invalid
invalid
FLUSH# Signal
invalid
invalid
WBINVD Instruction INVD Instruction Cache-Line Replacement
Notes:
invalid
invalid
invalid
invalid
See Table 30
All writebacks are 32-byte burst write cycles. - Not applicable or none.
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Cache Snooping
Table 32 shows the conditions under which snooping occurs in the AMD-K6 processor and the resources that are snooped. Table 32. Snoop Action
Snooping Action Type of Event Inquire Cycle Type of Access System Logic Instruction Cache Read Miss Read Hit Read Miss Data Cache Read Hit Write Miss Write Hit
Notes:
Instruction Cache yes1 - - yes3 no yes3 no
Data Cache yes1 yes2 no - - - -
Internal Snoop
1. The processor's response to an inquire cycle depends on the state of the INV input signal and the state of the cache line as follows: For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but if INV is sampled asserted, the line is invalidated. For the data cache, if INV is sampled negated, valid lines remain in or transition to the shared state, a modified data cache line is written back before the line is marked shared (with HITM# asserted), and invalid lines remain invalid. For the data cache, if INV is sampled asserted, the line is marked invalid. Modified lines are written back before invalidation. 2. If an internal snoop hits a modified line in the data cache, the line is written back and invalidated. Then the instruction cache performs a burst read from memory. 3. If an internal snoop hits a line in the instruction cache, the instruction cache line is invalidated and the data-cache read or write is performed from memory. - Not applicable.
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8.11
Writethrough vs. Writeback Coherency States
The terms writethrough and writeback apply to two related concepts in a read-write cache like the AMD-K6 processor L1 data cache. The following conditions apply to both the writethrough and writeback modes:
s
s
Memory Writes--A relationship exists between external memory writes and their concurrence with cache updates: * An external memory write that occurs concurrently with a cache update to the same location is a writethrough. Writethroughs are driven as single cycles on the bus. * An external memory write that occurs after the processor has modified a cache line is a writeback. Writebacks are driven as burst cycles on the bus. Coherency State--A relationship exists between MESI coherency states and writethrough-writeback coherency states of lines in the cache as follows: * Shared MESI lines are in the writethrough state. * Modified and exclusive MESI lines are in the writeback state.
8.12
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive input on every clock edge, it should only be asserted in Real mode. The CPU applies the A20M# masking to its tags, through which all programs access the caches. Therefore, assertion of A20M# affects all addresses (cache and external memory), including the following:
s s
Cache-line fills (caused by read misses) Cache writethroughs (caused by write misses or write hits to lines in the shared state)
However, A20M# does not mask writebacks or invalidations caused by the following actions:
s s s s
Internal snoops Inquire cycles The FLUSH# signal The WBINVD instruction Cache Organization 187
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9
9.1
Floating-Point and Multimedia Execution Units
Floating-Point Execution Unit
The AMD-K6 processor contains an IEEE 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. Floating-point software is typically written to manipulate numbers that are very large or very small, that require a high degree of precision, or that result f r o m c o m p l e x m a t h e m a t i c a l o p e ra t i o n s s u c h a s transce ndentals. Applications t hat t ake advantage of floating-point operations include geometric calculations for graphics acceleration, scientific, statistical, and engineering applications, and business applications that use large amounts of high-precision data. The high-performance floating-point execution unit contains an adder unit, a multiplier unit, and a divide/square root unit. These low-latency units can execute floating-point instructions in as few as two processor clocks. To increase performance, the proce sso r is de sig ned to simul ta neo usly de code mo st floating-point instructions with most short-decodeable instructions. See "Software Environment" on page 21 for a description of the floating-point data types, registers, and instructions.
Handling Floating-Point Exceptions
The AMD-K6 processor provides the following two types of exception handling for floating-point exceptions:
s
s
If the numeric error (NE) bit in CR0 is set to 1, the processor invokes the interrupt 10h handler. In this manner, the floating-point exception is completely handled by software. If the NE bit in CR0 is set to 0, the processor requires external logic to generate an interrupt on the INTR signal in order to handle the exception.
External Logic Support of Floating-Point Exceptions
The processor provides the FERR# (Floating-Point Error) and IGNNE# (Ignore Numeric Error) signals to allow the external logic to generate the interrupt in a manner consistent with IBM-compatible PC/AT systems. The assertion of FERR# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point Floating-Point and Multimedia Execution Units 189
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instruction. IGNNE# is used by the external hardware to control the effect of an unmasked floating-point exception. Under certain circumstances, if IGNNE# is sampled asserted, the processor ignores the floating-point exception. Figure 71 illustrates an implementation of external logic for supporting floating-point exceptions. The following example explains the operation of the external logic in Figure 71: As the result of a floating-point exception, the processor asserts FERR#. The assertion of FERR# and the sampling of IGNNE# negated indicates the processor has stopped instruction execution and is waiting for an interrupt. The assertion of FERR# leads to the assertion of INTR by the interrupt controller. The processor a ck n o w l e d g e s t h e i n t e r r u p t a n d j u m p s t o t h e corresponding interrupt service routine in which an I/O write cycle to address port F0h leads to the assertion of IGNNE#. When IGNNE# is sampled asserted, the processor ignores the floating-point exception and continues instruction execution. When the processor negates FERR#, the external logic negates IGNNE#. See "FERR# (Floating-Point Error)" on page 96 and "IGNNE# (Ignore Numeric Exception)" on page 100 for more details.
AMD-K6(R)
Processor I/O Address Port F0h IGNNE# Flip-Flop CLOCK Q "1" FERR# DATA CLEAR FERR# Flip-Flop CLOCK Q DATA CLEAR INTR IGNNE# Q Interrupt Controller IRQ13 Q
RESET
Figure 71. External Logic for Supporting Floating-Point Exceptions
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9.2
Multimedia Execution Unit
The multimedia execution unit of the AMD-K6 processor is designed to accelerate the performance of software written using the industry-standard MMX instructions. Applications that can take advantage of the MMX instructions include graphics, video and audio compression and decompression, speech recognition, and telephony applications. The multimedia execution unit can execute MMX instructions in a single processor clock. To increase performance, the processor is designed to simultaneously decode all MMX instructions with most other instructions. For more information on MMX instructions, refer to AMD-K6(R) Processor Multimedia Technology, order# 20726.
9.3
Registers
Floating-Point and MMXTM Instruction Compatibility
T h e e i g h t 6 4 -b i t M M X re g i s t e rs a re m a p p e d o n t h e floating-point stack. This enables backward compatibility with all existing software. For example, the register saving event that is performed by operating systems during task switching requires no changes to the operating system. The same support provided in an operating system's interrupt 7 handler (Device Not Available) for saving and restoring the floating-point registers also supports saving and restoring the MMX registers. There are no new exceptions defined for supporting the MMX instructions. All exceptions that occur while decoding or executing an MMX instruction are handled in existing exception handlers without modification. MMX instructions do not generate floating-point exceptions. However, if an unmasked floating-point exception is pending, the processor asserts FERR# at the instruction boundary of the next floating-point instruction, MMX instruction, or WAIT instruction. The sampling of IGNNE# asserted only affects processor o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive floating-point instruct ion, MMX inst ruct ion, or WAIT instruction when the NE bit in CR0 is set to 0.
Exceptions
FERR# and IGNNE#
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10
10.1
System Management Mode (SMM)
Overview
SMM is an alternate operating mode entered by way of a system management interrupt (SMI#) and handled by an interrupt service routine. SMM is designed for system control activities s u ch a s p owe r m a n a g e m e n t . Th e s e a c t iv i t i e s a p p e a r transparent to conventional operating systems like DOS and Windows. SMM is primarily targeted for use by the Basic Input Output System (BIOS) and specialized low-level device drivers. The code and data for SMM are stored in the SMM memory area, which is isolated from main memory. The processor enters SMM by the system logic's assertion of the SMI# interrupt and the processor's acknowledgment by the assertion of SMIACT#. At this point the processor saves its state into the SMM memory state-save area and jumps to the SMM service routine. The processor returns from SMM when it executes the RSM (resume) instruction from within the SMM service routine. Subsequently, the processor restores its state from the SMM save area, negates SMIACT#, and resumes execution with the instruction following the point where it entered SMM. The following sections summarize the SMM state-save area, entry into and exit from SMM, exceptions and interrupts in SMM, memory allocation and addressing in SMM, and the SMI# and SMIACT# signals.
10.2
SMM Operating Mode and Default Register Values
The software environment within SMM has the following characteristics:
s s s
s
Addressing and operation in Real mode 4-Gbyte segment limits Default 16-bit operand, address, and stack sizes, although instruction prefixes can override these defaults Control transfers that do not override the default operand size truncate the EIP to 16 bits System Management Mode (SMM) 193
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s
s s s s s s
Far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits, as in Real mode segment-base addressing A20M# is masked Interrupt vectors use the Real-mode interrupt vector table The IF flag in EFLAGS is cleared (INTR not recognized) The TF flag in EFLAGS is cleared The NMI and INIT interrupts are disabled Debug register DR7 is cleared (debug traps disabled)
Figure 72 on page 195 shows the default map of the SMM me mo ry a rea . I t consis ts o f a 64 -Kbyt e area, bet wee n 0003_0000h and 0003_FFFFh, of which the top 32 Kbytes (0003_8000h to 0003_FFFFh) must be populated with RAM. The default code-segment (CS) base address for the area -- called the SMM base address --is at 0003_0000h. The top 512 bytes (0003_FE00h to 0003_FFFFh) contain a fill-down SMM state-save area. The default entry point for the SMM service routine is 0003_8000h.
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Fill Down
SMM State-Save Area
0003_FFFFh
0003_FE00h
32-Kbyte Minimum RAM
SMM Service Routine Service Routine Entry Point 0003_8000h
SMM Base Address (CS)
0003_0000h
Figure 72. SMM Memory Table 33 shows the initial state of registers when entering SMM. Table 33. Initial State of Registers in SMM
Registers General Purpose Registers EFLAGs CR0 DR7 GDTR, LDTR, IDTR, TSSR, DR6 EIP CS DS, ES, FS, GS, SS unmodified 0000_0002h PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31). The other bits are unmodified. 0000_0400h unmodified 0000_8000h 0003_0000h 0000_0000h SMM Initial State
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10.3
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by asserting SMIACT#, it saves its state in a 512-byte SMM state-save area shown in Table 34. The save begins at the top of the SMM memory area (SMM base address + FFFFh) and fills down to SMM base address + FE00h. Table 34 shows the offsets in the SMM state-save area relative to the SMM base address. The SMM service routine can alter any of the read/write values in the state-save area. Table 34. SMM State-Save Area Map
Address Offset FFFCh FFF8h FFF4h FFF0h FFECh FFE8h FFE4h FFE0h FFDCh FFD8h FFD4h FFD0h FFCCh FFC8h FFC4h FFC0h FFBCh FFB8h FFB4h FFB0h FFACh FFA8h
Notes:
Contents Saved CR0 CR3 EFLAGS EIP EDI ESI EBP ESP EBX EDX ECX EAX DR6 DR7 TR LDTR Base GS FS DS SS CS ES
-- No data dump at that address * Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 34. SMM State-Save Area Map (continued)
Address Offset FFA4h FFA0h FF9Ch FF98h FF94h FF90h FF8Ch FF88h FF84h FF80h FF7Ch FF78h FF74h FF70h FF6Ch FF68h FF64h FF60h FF5Ch FF58h FF54h FF50h FF4Ch FF48h FF44h FF40h FF3Ch FF38h FF34h FF30h FF2Ch
Notes:
Contents Saved I/O Trap Dword -- I/O Trap EIP* -- -- IDT Base IDT Limit GDT Base GDT Limit TSS Attr TSS Base TSS Limit -- LDT High LDT Low GS Attr GS Base GS Limit FS Attr FS Base FS Limit DS Attr DS Base DS Limit SS Attr SS Base SS Limit CS Attr CS Base CS Limit ES Attr
-- No data dump at that address * Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 34. SMM State-Save Area Map (continued)
Address Offset FF28h FF24h FF20h FF1Ch FF18h FF14h FF10h FF0Ch FF08h FF04h FF02h FF00h FEFCh FEF8h FEF7h-FE00h
Notes:
Contents Saved ES Base ES Limit -- -- -- CR2 CR4 I/O restart ESI* I/O restart ECX* I/O restart EDI* HALT Restart Slot I/O Trap Restart Slot SMM RevID SMM BASE --
-- No data dump at that address * Only contains information if SMI# is asserted during a valid I/O bus cycle.
10.4
SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM state-save area specifies the version of SMM and the extensions that are available on the processor. The SMM revision identifier fields are as follows:
s s s s
Bits 31-18--Reserved Bit 17--SMM base address relocation (1 = enabled) Bit 16--I/O trap restart (1 = enabled) Bits 15-0--SMM revision level for the AMD-K6 processor = 0002h
Table 35 on page 199 shows the format of the SMM Revision Identifier.
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Table 35. SMM Revision Identifier
31-18 Reserved 0 17 SMM Base Relocation 1 16 I/O Trap Extension 1 15-0 SMM Revision Level 0002h
10.5
SMM Base Address
During RESET, the processor sets the base address of the code-segment (CS) for the SMM memory area--the SMM base address--to its default, 0003_0000h. The SMM base address at offset FEF8h in the SMM state-save area can be changed by the SMM service routine to any address that is aligned to a 32-Kbyte boundary. (Locations not aligned to a 32-Kbyte boundary cause the processor to enter the Shutdown state when executing the RSM instruction.) In some operating environments it may be desirable to relocate the 64-Kbyte SMM memory area to a high memory area in order to provide more low memory for legacy software. During system initialization, the base of the 64-Kbyte SMM memory area is relocated by the BIOS. To relocate the SMM base address, the system enters the SMM handler at the default address. This handler changes the SMM base address location in the SMM state-save area, copies the SMM handler to the new location, and exits SMM. The next time SMM is entered, the processor saves its state at the new base address. This new address is used for every SMM entry until the SMM base address in the SMM state-save area is changed or a hardware reset occurs.
10.6
Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in the SMM state-save area indicates if SMM was entered from the Halt state. Before returning from SMM, the halt restart slot (offset FF02h) can be written to by the SMM service routine to specify whether the return from SMM takes the processor back to the Halt state or to the next instruction after the HLT instruction.
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Upon entry into SMM, the halt restart slot is defined as follows:
s s
Bits 15-1--Reserved Bit 0--Point of entry to SMM: 1 = entered from Halt state 0 = not entered from Halt state
After entry into the SMI handler and before returning from SMM, the halt restart slot can be written using the following definition:
s s
Bits 15-1--Reserved Bit 0--Point of return when exiting from SMM: 1 = return to Halt state 0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt state, the HLT instruction is not re-executed, but the Halt special bus cycle is driven on the bus after the return.
10.7
I/O Trap Dword
If the assertion of SMI# is recognized during the execution of an I/O instruction, the I/O trap dword at offset FFA4h in the SMM state-save area contains information about the instruction. The fields of the I/O trap dword are configured as follows:
s s s
s
s s
Bits 31-16--I/O port address Bits 15-4--Reserved Bit 3--REP (repeat) string operation (1 = REP string, 0 = not a REP string) Bit 2--I/O string operation (1 = I/O string, 0 = not an I/O string) Bit 1--Valid I/O instruction (1 = valid, 0 = invalid) Bit 0--Input or output instruction (1 = INx, 0 = OUTx)
Table 36 shows the format of the I/O trap dword. Table 36. I/O Trap Dword Configuration
31--16 I/O Port Address 15--4 Reserved 3 REP String Operation 2 I/O String Operation 1 Valid I/O Instruction 0 Input or Output
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The I/O trap dword is related to the I/O trap restart slot (see "I/O Trap Restart Slot"). If bit 1 of the I/O trap dword is set by the processor, it means that SMI# was asserted during the execution of an I/O instruction. The SMI handler tests bit 1 to see if there is a valid I/O instruction trapped. If the I/O instruction is valid, the SMI handler is required to ensure the I/O trap restart slot is set properly. The I/O trap restart slot informs the CPU whether it should re-execute the I/O instruction after the RSM or execute the instruction following the trapped I/O instruction. Note: If SMI# is sampled asserted during an I/O bus cycle a minimum of three clock edges before BRDY# is sampled asserted, the associated I/O instruction is guaranteed to be trapped by the SMI handler.
10.8
I/O Trap Restart Slot
The I/O trap restart slot at offset FF00h in the SMM state-save area specifies whether the trapped I/O instruction should be re-executed on return from SMM. This slot in the state-save area is called the I/O instruction restart function. Re-executing a trapped I/O instruction is useful, for example, if an I/O write occurs to a disk that is powered down. The system logic monitoring such an access can assert SMI#. Then the SMM service routine would query the system logic, detect a failed I/O write, take action to power-up the I/O device, enable the I/O trap restart slot feature, and return from SMM. The fields of the I/O trap restart slot are defined as follows:
s s
Bits 31-16--Reserved Bits 15-0--I/O instruction restart on return from SMM: 0000h = execute the next instruction after the trapped I/O instruction 00FFh = re-execute the trapped I/O instruction
Table 37 shows the format of the I/O trap restart slot. Table 37. I/O Trap Restart Slot
31-16 Reserved
s s
15-0 I/O Instruction restart on return from SMM: 0000h = execute the next instruction after the trapped I/O 00FFh = re-execute the trapped I/O instruction
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The processor initializes the I/O trap restart slot to 0000h upon entry into SMM. If SMM was entered due to a trapped I/O instruction, the processor indicates the validity of the I/O instruction by setting or clearing bit 1 of the I/O trap dword at offset FFA4h in the SMM state-save area. The SMM service routine should test bit 1 of the I/O trap dword to determine if a valid I/O instruction was being executed when entering SMM and before writing the I/O trap restart slot. If the I/O instruction is valid, the SMM service routine can safely rewrite the I/O trap restart slot with the value 00FFh, which causes the processor to re-execute t he trapped I/O instruction w hen the RSM instruction is executed. If the I/O instruction is invalid, writing the I/O trap restart slot has undefined results. If a second SMI# is asserted and a valid I/O instruction was trapped by the first SMM handler, the CPU services the second SMI# prior to re-executing the trapped I/O instruction. The second entry into SMM never has bit 1 of the I/O trap dword set, and the second SMM service routine must not rewrite the I/O trap restart slot. During a simultaneous SMI# I/O instruction trap and debug breakpoint trap, the AMD-K6 processor first responds to the SMI# and postpones recognizing the debug exception until after returning from SMM via the RSM instruction. If the debug registers DR3-DR0 are used while in SMM, they must be saved and restored by the SMM handler. The processor automatically saves and restores DR7-DR6. If the I/O trap restart slot in the SMM state-save area contains the value 00FFh when the RSM instruction is executed, the debug trap does not occur until after the I/O instruction is re-executed.
10.9
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the AMD-K6 processor changes from its normal priority. The normal priority places the debug traps at a priority higher than the sampling of the FLUSH# or SMI# signals. However, during an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals takes precedence over debug traps. The processor recognizes the assertion of NMI within SMM immediately after the completion of an IRET instruction. Once NMI is recognized within SMM, NMI recognition remains enabled until SMM is exited, at which point NMI masking is restored to the state it was in before entering SMM.
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11
Test and Debug
The AMD-K6 processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. In addition, the debug features of the processor allow designers to debug the instruction execution of software components. This chapter describes the following test and debug features:
s
Built-In Self-Test (BIST)--The BIST, which is invoked after the falling transition of RESET, runs internal tests that exercise most on-chip RAM structures. Tri-State Test Mode--A test mode that causes the processor to float its output and bidirectional pins. Boundary-Scan Test Access Port (TAP)--The Joint Test Action Group (JTAG) test access function defined by the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) specification. Level-One (L1) Cache Inhibit--A feature that disables the processor's internal L1 instruction and data caches. Debug Support--Consists of all x86-compatible software debug features, including the debug extensions.
s
s
s
s
11.1
Built-In Self-Test (BIST)
Following the falling transition of RESET, the processor unconditionally runs its BIST. The internal resources tested during BIST include the following:
s s
L1 instruction and data caches Instruction and Data Translation Lookaside Buffers (TLBs)
The contents of the EAX general-purpose register after the completion of reset indicate if the BIST was successful. If EAX contains 0000_0000h, then BIST was successful. If EAX is non-zero, the BIST failed. Following the completion of the BIST, the pro ce ssor jum ps to address FF FF_FF F0 h to start instruction execution, regardless of the outcome of the BIST. The BIST takes approximately 295,000 processor clocks to complete.
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11.2
Tri-State Test Mode
The Tri-State Test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. In this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ATE) to test components that drive the same signals as those the processor floats. If the FLUSH# signal is sampled Low during the falling transition of RESET, the processor enters the Tri-State Test mode. (See "FLUSH# (Cache Flush)" on page 97 for the specific sampling requirements.) The signals floated in the Tri-State Test mode are as follows:
s s s s s s s s
A[31:3] ADS# ADSC# AP APCHK# BE[7:0]# BREQ CACHE#
s s s s s s s s
D/C# D[63:0] DP[7:0] FERR# HIT# HITM# HLDA LOCK#
s s s s s s s
M/IO# PCD PCHK# PWT SCYC SMIACT# W/R#
The VCC2DET and TDO signals are the only outputs not floated in the Tri-State Test mode. VCC2DET must remain Low to ensure the system continues to supply the specified processor core voltage to the VCC2 pins. TDO is never floated because the Boundary-Scan Test Access Port must remain enabled at all times, including during the Tri-State Test mode. The Tri-State Test mode is exited when the processor samples RESET asserted.
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11.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. The AMD-K6 processor supports the TAP standard defined in the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) specification. Boundary scan testing uses a shift register consisting of the serial interconnection of boundary-scan cells that correspond to each I/O buffer of the processor. This non-inverting register chain, called a Boundary Scan Register (BSR), can be used to capture the state of every processor pin and to drive every processor output and bidirectional pin to a known state. Each BSR of every component on a board that implements the boundary-scan architecture can be serially interconnected to enable component interconnect testing.
Test Access Port
The TAP consists of the following:
s
s
s
Test Access Port (TAP) Controller--The TAP controller is a synchronous, finite state machine that uses the TMS and TDI input signals to control a sequence of test operations. See "TAP Controller State Machine" on page 212 for a list of TAP states and their definition. Instruction Register (IR)--The IR contains the instructions that select the test operation to be performed and the Test Data Register (TDR) to be selected. See "TAP Registers" on page 206 for more details on the IR. Test Data Registers (TDR)--The three TDRs are used to process the test data. Each TDR is selected by an instruction in the Instruction Register (IR). See "TAP Registers" on page 206 for a list of these registers and their functions.
TAP Signals
The test signals associated with the TAP controller are as follows:
s
TCK--The Test Clock for all TAP operations. The rising edge of TCK is used for sampling TAP signals, and the falling edge of TCK is used for asserting TAP signals. The state of the TMS signal sampled on the rising edge of TCK causes
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s
s
the state transitions of the TAP controller to occur. TCK can be stopped in the logic 0 or 1 state. TDI--The Test Data Input represents the input to the most significant bit of all TAP registers, including the IR and all test data registers. Test data and instructions are serially shifted by one bit into their respective registers on the rising edge of TCK. TDO--The Test Data Output represents the output of the least significant bit of all TAP registers, including the IR and all test data registers. Test data and instructions are serially shifted by one bit out of their respective registers on the falling edge of TCK. TMS--The Test Mode Select input specifies the test function and sequence of state changes for boundary-scan testing. If TMS is sampled High for five or more consecutive clocks, the TAP controller enters its reset state. TRST#--The Test Reset signal is an asynchronous reset that unconditionally causes the TAP controller to enter its reset state.
s
s
Refer to "Electrical Data" on page 233 and "Signal Switching Charac teristics" on page 241 to obtain t he electrical specifications of the test signals. TAP Registers The AMD-K6 processor provides an Instruction Register (IR) a n d t h re e Te s t D a t a R e g i s t e rs ( T D R ) t o s u p p o r t t h e boundary-scan architecture. The IR and one of the TDRs--the Boundary-Scan Register (BSR)--consist of a shift register and an output register. The shift register is loaded in parallel in the Capture states. (See "TAP Controller State Machine" on page 212 for a description of the TAP controller states.) In addition, the shift register is loaded and shifted serially in the Shift states. The output register is loaded in parallel from its corresponding shift register in the Update states. Instruction Register (IR). The IR is a 5-bit register, without parity, that determines which instruction to run and which test data register to select. When the TAP controller enters the Capture-IR state, the processor loads the following bits into the IR shift register:
s
s
01b--Loaded into the two least significant bits, as specified by the IEEE 1149.1 standard 000b--Loaded into the three most significant bits Test and Debug Chapter 11
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Lo a d ing 0 00 01 b int o t h e I R sh if t re g ist e r d u rin g t h e Capture-IR state results in loading the SAMPLE/PRELOAD instruction. For each entry into the Shift-IR state, the IR shift register is serially shifted by one bit toward the TDO pin. During the shift, the most significant bit of the IR shift register is loaded from the TDI pin. The IR output register is loaded from the IR shift register in the Update-IR state, and the current instruction is defined by the IR output register. See "TAP Instructions" on page 211 for a list and definition of the instructions supported by the AMD-K6. Boundary Scan Register (BSR). The BSR is a Test Data Register consisting of the interconnection of 152 boundary-scan cells. Each output and bidirectional pin of the processor requires a two-bit cell, where one bit corresponds to the pin and the other bit is the output enable for the pin. When a 0 is shifted into the enable bit of a cell, the corresponding pin is floated, and when a 1 is shifted into the enable bit, the pin is driven valid. Each input pin requires a one-bit cell that corresponds to the pin. The last cell of the BSR is reserved and does not correspond to any processor pin. The total number of bits that comprise the BSR is 281. Table 38 on page 209 lists the order of these bits, where TDI is the input to bit 280, and TDO is driven from the output of bit 0. The entries listed as pin_E (where pin is an output or bidirectional signal) are the enable bits. If the BSR is the register selected by the current instruction and the TAP controller is in the Capture-DR state, the processor loads the BSR shift register as follows:
s
s
If the current instruction is SAMPLE/PRELOAD, then the current state of each input, output, and bidirectional pin is loaded. A bidirectional pin is treated as an output if its enable bit equals 1, and it is treated as an input if its enable bit equals 0. If the current instruction is EXTEST, then the current state of each input pin is loaded. A bidirectional pin is treated as an input, regardless of the state of its enable.
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While in the Shift-DR state, the BSR shift register is serially shifted toward the TDO pin. During the shift, bit 280 of the BSR is loaded from the TDI pin. The BSR output register is loaded with the contents of the BSR shift register in the Update-DR state. If the current instruction is EXTEST, the processor's output pins, as well as those bidirectional pins that are enabled as outputs, are driven with their corresponding values from the BSR output register.
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Table 38. Boundary Scan Bit Definitions
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit 280 D35_E 279 D35 278 D29_E 277 D29 276 D33_E 275 D33 274 D27_E 273 D27 272 DP3_E 271 DP3 270 D25_E 269 D25 268 D0_E 267 D0 266 D30_E 265 D30 264 DP2_E 263 DP2 262 D2_E 261 D2 260 D28_E 259 D28 258 D24_E 257 D24 256 D26_E 255 D26 254 D22_E 253 D22 252 D23_E 251 D23 250 D20_E 249 D20 248 D21_E 247 D21 246 D18_E 245 D18 244 D19_E 243 D19 242 D16_E 241 D16 240 D17_E 239 D17 238 D15_E 237 D15 236 DP1_E 235 DP1 234 D13_E 233 D13 232 D6_E 231 D6 230 D14_E 229 D14 228 D11_E 227 D11 226 D1_E 225 D1 224 D12_E 223 D12 222 D10_E 221 D10 220 D7_E 219 D7 218 D8_E 217 D8 216 D9_E 215 D9 214 D4_E 213 D4 212 DP0_E 211 DP0 210 HOLD 209 BOFF# 208 AHOLD 207 STPCLK# 206 INIT 205 IGNNE# 204 BF1 203 BF2 202 RESET 201 BF0 200 FLUSH# 199 INTR 198 NMI 197 SMI# 196 A25_E 195 A25 194 A23_E 193 A23 192 A26_E 191 A26 190 A29_E 189 A29 188 A28_E 187 A28 186 A27_E 185 A27 184 A11_E 183 A11 182 A3_E 181 A3 180 A31_E 179 A31 178 A21_E 177 A21 176 A30_E 175 A30 174 A7_E 173 A7 172 A24_E 171 A24 170 A18_E 169 A18 168 A5_E 167 A5 166 A22_E 165 A22 164 EADS# 163 A4_E 162 A4 161 HITM_E 160 HITM# 159 A9_E 158 A9 157 SCYC_E 156 SCYC 155 A8_E 154 A8 153 A19_E 152 A19 151 A6_E 150 A6 149 A20_E 148 A20 147 A13_E 146 A13 145 DP7_E 144 DP7 143 BE6_E 142 BE6# 141 A12_E 140 A12 139 CLK 138 BE4_E 137 BE4# 136 A10_E 135 A10 134 D63_E 133 D63 132 BE2_E 131 BE2# 130 A15_E 129 A15 128 BRDY# 127 BE1_E 126 BE1# 125 A14_E 124 A14 123 BRDYC# 122 BE0_E 121 BE0# 120 A17_E 119 A17 118 KEN# 117 A20M# 116 A16_E Pin/Enable 115 A16 114 FERR_E 113 FERR# 112 HIT_E 111 HIT# 110 BE7_E 109 BE7# 108 NA# 107 ADSC_E 106 ADSC# 105 BE5_E 104 BE5# 103 WB/WT# 102 PWT_E 101 PWT 100 BE3_E 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 BE3# BREQ_E BREQ PCD_E PCD WR_E W/R# SMIACT_E SMIACT# EWBE# DC_E D/C# APCHK_E APCHK# CACHE_E CACHE# ADS_E
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Table 38. Boundary Scan Bit Definitions (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit 82 81 80 79 78 77 76 75 74 73 72 71 70 69 ADS# AP_E AP INV HLDA_E HLDA PCHK_E PCHK# LOCK_E LOCK# MIO_E M/IO# D52_E D52 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DP6_E DP6 D54_E D54 D50_E D50 D56_E D56 D55_E D55 D48_E D48 D57_E D57 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D53_E D53 D47_E D47 D59_E D59 D51_E D51 D45_E D45 D61_E D61 DP5_E DP5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 D43_E D43 D62_E D62 D49_E D49 DP4_E DP4 D46_E D46 D41_E D41 D44_E D44 26 25 24 23 22 21 20 19 18 17 16 15 14 13 D38_E D38 D58_E D58 D42_E D42 D36_E D36 D60_E D60 D40_E D40 D34_E D34 12 11 10 9 8 7 6 5 4 3 2 1 0 Pin/Enable D3_E D3 D39_E D39 D32_E D32 D5_E D5 D37_E D37 D31_E D31 Reserved
Device Identification Register (DIR). The DIR is a 32-bit Test Data Register selected during the execution of the IDCODE instruction. The fields of the DIR and their values are shown in Table 39 and are defined as follows:
s
s
s
s
Version Code--This 4-bit field is incremented by AMD manufacturing for each major revision of silicon. Part Number--This 16-bit field identifies the specific processor model. Manufacturer--This 11-bit field identifies the manufacturer of the component (AMD). LSB--The least significant bit (LSB) of the DIR is always set to 1, as specified by the IEEE 1149.1 standard.
Table 39. Device Identification Register
Version Code (Bits 31-28) Xh Part Number (Bits 27-12) 0560h Manufacturer (Bits 11-1) 00000000001b LSB (Bit 0) 1b
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Bypass Register (BR). The BR is a Test Data Register consisting of a 1-bit shift register that provides the shortest path between TDI and TDO. When the processor is not involved in a test operation, the BR can be selected by an instruction to allow the transfer of test data through the processor without having to serially scan the test data through the BSR. This functionality preserves the state of the BSR and significantly reduces test time. The BR register is selected by the BYPASS and HIGHZ instructions as well as by any instructions not supported by the AMD-K6. TAP Instructions The processor supports the three instructions required by the IEEE 1149.1 standard -- EXTEST, SAMPLE/PRELOAD, and BYPASS -- as well as two additional optional instructions -- IDCODE and HIGHZ. Table 40 shows the complete set of TAP instructions supported by the processor along with the 5-bit Instruction Register encoding and the register selected by each instruction. Table 40. Supported Tap Instructions
Instruction EXTEST1 SAMPLE / PRELOAD IDCODE HIGHZ BYPASS2 BYPASS3
Notes:
Encoding 00000b 00001b 00010b 00011b 00100b-11110b 11111b
Register BSR BSR DIR BR BR BR
Description Sample inputs and drive outputs Sample inputs and outputs, then load the BSR Read DIR Float outputs and bidirectional pins Undefined instruction, execute the BYPASS instruction Connect TDI to TDO to bypass the BSR
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation. 2. These instruction encodings are undefined on the AMD-K6 processor and default to the BYPASS instruction. 3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST. When the EXTEST instruction is execut ed, the processor loads the BSR shift register with the current state of the input and bidirectional pins in the Capture-DR state and drives the output and bidirectional pins with the corresponding values from the BSR output register in the Update-DR state.
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SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction performs two functions. These functions are as follows:
s
s
During the Capture-DR state, the processor loads the BSR shift register with the current state of every input, output, and bidirectional pin. During the Update-DR state, the BSR output register is loaded from the BSR shift register in preparation for the next EXTEST instruction.
The SAMPLE/PRELOAD instruction does not affect the normal operational state of the processor. BYPASS. The BYPASS instruction selects the BR register, which reduces the boundary-scan length through the processor from 281 to one (TDI to BR to TDO). The BYPASS instruction does not affect the normal operational state of the processor. IDCODE. The IDCODE instruction selects the DIR register, allowing the device identification code to be shifted out of the processor. This instruction is loaded into the IR when the TAP controller is reset. The IDCODE instruction does not affect the normal operational state of the processor. HIGHZ. T h e H I G H Z i n s t r u c t i o n f o rc e s a l l o u t p u t a n d bidirectional pins to be floated. During this instruction, the BR is selected and the normal operational state of the processor is not affected. TAP Controller State Machine The TAP controller state diagram is shown in Figure 73 on page 213. State transitions occur on the rising edge of TCK. The logic 0 or 1 next to the states represents the value of the TMS signal sampled by the processor on the rising edge of TCK.
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Test-Logic-Reset 1 0 1 1 1
Run-Test/Idle 0
Select-DR-Scan
Select-IR-Scan
0 1 1
0
Capture-DR
Capture-IR
0 Shift-DR 0 1 1 Exit1-DR
0
Shift-IR 0 1 Exit1-IR 1
0 Pause-DR 0 1
0 Pause-IR 0 1 Exit2-IR 0 0 1 Update-IR 0 1 0
Exit2-DR
1 Update-DR 1
IEEE Std 1149.1-1990, Copyright (c) 1990. IEEE. All rights reserved
Figure 73. TAP State Diagram
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The states of the TAP controller are described as follows: Test-Logic-Reset. This state represents the initial reset state of the TAP controller and is entered when the processor samples RESET asserted, when TRST# is asynchronously asserted, and when TMS is sampled High for five or more consecutive clocks. In addition, this state can be entered from the Select-IR-Scan state. The IR is initialized with the IDCODE instruction, and the processor's normal operation is not affected in this state. Capture-DR. During the SAMPLE/PRELOAD instruction, the processor loads the BSR shift register with the current state of every input, output, and bidirectional pin. During the EXTEST instruction, the processor loads the BSR shift register with the current state of every input and bidirectional pin. Capture-IR. When the TAP controller enters the Capture-IR state, the processor loads 01b into the two least significant bits of the IR shift register and loads 000b into the three most significant bits of the IR shift register. Shift-DR. While in the Shift-DR state, the selected TDR shift register is serially shifted toward the TDO pin. During the shift, the most significant bit of the TDR is loaded from the TDI pin. Shift-IR. While in the Shift-IR state, the IR shift register is serially shifted toward the TDO pin. During the shift, the most significant bit of the IR is loaded from the TDI pin. Update-DR. During the SAMPLE/PRELOAD instruction, the BSR output register is loaded with the contents of the BSR shift register. During the EXTEST instruction, the output pins, as well as those bidirectional pins defined as outputs, are driven with their corresponding values from the BSR output register. Update-IR. In this state, the IR output register is loaded from the IR shift register, and the current instruction is defined by the IR output register.
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The following states have no effect on the normal or test operation of the processor other than as shown in Figure 73 on page 213:
s
s
s
Run-Test/Idle--This state is an idle state between scan operations. Select-DR-Scan--This is the initial state of the test data register state transitions. Select-IR-Scan--This is the initial state of the Instruction Register state transitions. Exit1-DR--This state is entered to terminate the shifting process and enter the Update-DR state. Exit1-IR--This state is entered to terminate the shifting process and enter the Update-IR state. Pause-DR--This state is entered to temporarily stop the shifting process of a Test Data Register. Pause-IR--This state is entered to temporarily stop the shifting process of the Instruction Register. Exit2-DR--This state is entered in order to either terminate the shifting process and enter the Update-DR state or to resume shifting following the exit from the Pause-DR state. Exit2-IR--This state is entered in order to either terminate the shifting process and enter the Update-IR state or to resume shifting following the exit from the Pause-IR state.
s
s
s
s
s
s
11.4
Purpose
L1 Cache Inhibit
The AMD-K6 processor provides a means for inhibiting the normal operation of its L1 instruction and data caches while still supporting an external Level-2 (L2) cache. This capability allows system designers to disable the L1 cache during the testing and debug of an L2 cache. If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set to 0, the processor's L1 cache is enabled and operates as described in "Cache Organization" on page 171. If the Cache Inhibit bit is set to 1, the L1 cache is disabled and no new cache lines are allocated. Even though new allocations do not occur, valid L1 cache lines remain valid and are read by the processor when a requested address hits a cache line. In addition, the processor continues to support inquire cycles initiated by the
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system logic, including the execution of writeback cycles when a modified cache line is hit. While the L1 is inhibited, the processor continues to drive the PCD output signal appropriately, which system logic can use to control external L2 caching. In order to completely disable the L1 cache so no valid lines exist in the cache, the Cache Inhibit bit must be set to 1 and the cache must be flushed in one of the following ways:
s s s
By asserting the FLUSH# input signal By executing the WBINVD instruction By executing the INVD instruction (modified cache lines are not written back to memory)
11.5
Debug
The AMD-K6 processor implements the standard x86 debug functions, registers, and exceptions. In addition, the processor supports the I/O breakpoint debug extension. The debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. The exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. The following sections describe the debug registers and the various types of breakpoints and exceptions that the processor supports.
Debug Registers
Figures 74 through 77 show the 32-bit debug registers supported by the processor.
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AMD-K6(R) Processor Data Sheet
Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0
Description Length of Breakpoint #3 Type of Transaction(s) to Trap Length of Breakpoint #2 Type of Transaction(s) to Trap Length of Breakpoint #1 Type of Transaction(s) to Trap Length of Breakpoint #0 Type of Transaction(s) to Trap
Bits 31-30 29-28 27-26 25-24 23-22 21-20 19-18 17-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 G D G E
8
7
6
5 L 2
4
3
2
1
0 L 0
LGL E33
LG 21
LG 10
Reserved Symbol GD GE LE G3 L3 G2 L2 G1 L1 G0 L0 Description General Detect Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint # 3 Enabled Local Exact Breakpoint # 3 Enabled Global Exact Breakpoint # 2 Enabled Local Exact Breakpoint # 2 Enabled Global Exact Breakpoint # 1 Enabled Local Exact Breakpoint # 1 Enabled Global Exact Breakpoint # 0 Enabled Local Exact Breakpoint # 0 Enabled Bit 13 9 8 7 6 5 4 3 2 1 0
Figure 74. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BBB TSD
8
7
6
5
4
3 B 3
2 B 2
1 B 1
0 B 0
Reserved Symbol BT BS BD B3 B2 B1 B0 Description Breakpoint Task Switch Breakpoint Single Step Breakpoint Debug Access Detected Breakpoint #3 Condition Detected Breakpoint #2 Condition Detected Breakpoint #1 Condition Detected Breakpoint #0 Condition Detected Bit 15 14 13 3 2 1 0
Figure 75. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0
Figure 76. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 3 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 2 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 1 32-bit Linear Address 8 7 6 5 4 3 2 1 0
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Breakpoint 0 32-bit Linear Address 8 7 6 5 4 3 2 1 0
Figure 77. Debug Registers DR3, DR2, DR1, and DR0 DR3-DR0. The processor allows the setting of up to four breakpoints. DR3-DR0 contain the linear addresses for breakpoint 3 through breakpoint 0, respectively, and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. Debug register DR7 defines the specific type of cycle that must occur in order for the breakpoint to occur. DR5-DR4. When debugging extensions are disabled (bit 3 of CR4 is set to 0), the DR5 and DR4 registers are mapped to DR7 and DR6, respectively, in order to be software compatible with previous generations of x86 processors. When debugging Chapter 11 Test and Debug 219
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extensions are enabled (bit 3 of CR4 is set to 1), any attempt to load DR5 or DR4 results in an undefined opcode exception. Likewise, any attempt to store DR5 or DR4 also results in an undefined opcode exception. DR6. If a breakpoint is enabled in DR7, and the breakpoint conditions as defined in DR7 occur, then the corresponding B-bit (B3-B0) in DR6 is set to 1. In addition, any other breakpoints defined using these particular breakpoint conditions are reported by the processor by setting the appropriate B-bits in DR6, regardless of whether these breakpoints are enabled or disabled. However, if a breakpoint is not enabled, a debug exception does not occur for that breakpoint. If the processor decodes an instruction that writes or reads DR7 through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in DR7) and the processor generates a debug exception. This operation allows control to pass to the debugger prior to debug register access by software. If the Trap Flag (bit 8) of the EFLAGS register is set to 1, the processor generates a debug exception after the successful execution of every instruction (single-step operation) and sets the BS bit (bit 14) in DR6 to indicate the source of the exception. When the processor switches to a new task and the debug trap bit (T-bit) in the corresponding Task State Segment (TSS) is set to 1, the processor sets the BT bit (bit 15) in DR6 and generates a debug exception. DR7. When set to 1, L3-L0 locally enable breakpoints 3 through 0, respectively. L3-L0 are set to 0 whenever the processor executes a task switch. Setting L3-L0 to 0 disables the breakpoints and ens ures that these particular debug exceptions are only generated for a specific task. When set to 1, G3-G0 globally enable breakpoints 3 through 0, respectively. Unlike L3-L0, G3-G0 are not set to 0 whenever the processor executes a task switch. Not setting G3-G0 to 0 allows breakpoints to remain enabled across all tasks. If a breakpoint is enabled globally but disabled locally, the global enable overrides the local enable.
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The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the operation of the processor and are provided in order to be software compatible with previous generations of x86 processors. When set to 1, the GD bit in DR7 (bit 13) enables the debug exception associated with the BD bit (bit 13) in DR6. This bit is set to 0 when a debug exception is generated. LEN3-LEN0 and RW3-RW0 are two-bit fields in DR7 that specify the length and type of each breakpoint as defined in Table 41. Table 41. DR7 LEN and RW Definitions
LEN Bits1 00b 00b 01b 11b 00b 01b 11b 00b 01b 11b
Notes:
RW Bits 00b2 01b
Breakpoint Instruction Execution One-byte Data Write Two-byte Data Write Four-byte Data Write One-byte I/O Read or Write
10b3
Two-byte I/O Read or Write Four-byte I/O Read or Write One-byte Data Read or Write
11b
Two-byte Data Read or Write Four-byte Data Read or Write
1. LEN bits equal to 10b is undefined. 2. When RW equals 00b, LEN must be equal to 00b. 3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1). If DE is set to 0, then RW equal to 10b is undefined.
Debug Exceptions
A debug exception is categorized as either a debug trap or a debug fault. A debug trap calls the debugger following the execution of the instruction that caused the trap. A debug fault calls the debugger prior to the execution of the instruction that caused the fault. All debug traps and faults generate either an Interrupt 01h or an Interrupt 03h exception.
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Interrupt 01h. The following events are considered debug traps that cause the processor to generate an Interrupt 01h exception:
s s s
Enabled breakpoints for data and I/O cycles Single Step Trap Task Switch Trap
The following events are considered debug faults that cause the processor to generate an Interrupt 01h exception:
s s
Enabled breakpoints for instruction execution BD bit in DR6 set to 1
Interrupt 03h. The INT 3 instruction is defined in the x86 architecture as a breakpoint instruction. This instruction causes the processor to generate an Interrupt 03h exception. This exception is a debug trap because the debugger is called following the execution of the INT 3 instruction. The INT 3 instruction is a one-byte instruction (opcode CCh) typically used to insert a breakpoint in software by writing CCh to the address of the first byte of the instruction to be trapped (the target instruction). Following the trap, if the target instruction is to be executed, the debugger must replace the INT 3 instruction with the first byte of the target instruction.
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12
Clock Control
The AMD-K6 processor supports five modes of clock control. The processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (See "Power Dissipation" on page 235 for the maximum power dissipation of the AMD-K6 processor within the normal and reduced-power states.) The five clock-control states supported are as follows:
s
s
s
Normal State: The processor is running in Real Mode, Virtual-8086 Mode, Protected Mode, or System Management Mode (SMM). In this state, all clocks are running--including the external bus clock CLK and the internal processor clock--and the full features and functions of the processor are available. Halt State: This low-power state is entered following the successful execution of the HLT instruction. During this state, the internal processor clock is stopped. Stop Grant State: This low-power state is entered following the recognition of the assertion of the STPCLK# signal. During this state, the internal processor clock is stopped. Stop Grant Inquire State: This state is entered from the Halt state and the Stop Grant state as the result of a system-initiated inquire cycle. Stop Clock State: This low-power state is entered from the Stop Grant state when the CLK signal is stopped.
s
s
The following sections describe each of the four low-power states. Figure 78 on page 228 illustrates the clock control state transitions.
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12.1
Halt State
During the execution of the HLT instruction, the AMD-K6 processor executes a Halt special cycle. After BRDY# is sampled asserted during this cycle, and then EWBE# is also sampled asserted, the processor enters the Halt state in which the processor disables most of its internal clock distribution. In order to support the following operations, the internal phase-lock loop (PLL) still runs, and some internal resources are still clocked in the Halt state:
s
Enter Halt State
s
s
s
Inquire Cycles: The processor continues to sample AHOLD, BOFF#, and HOLD in order to support inquire cycles that are initiated by the system logic. The processor transitions to the Stop Grant Inquire state during the inquire cycle. After returning to the Halt state following the inquire cycle, the processor does not execute another Halt special cycle. Flush Cycles: The processor continues to sample FLUSH#. If FLUSH# is sampled asserted, the processor performs the flush operation in the same manner as it is performed in the Normal state. Upon completing the flush operation, the processor executes the Halt special cycle which indicates the processor is in the Halt state. Time Stamp Counter (TSC): The TSC continues to count in the Halt state. Signal Sampling: The processor continues to sample INIT, INTR, NMI, RESET, and SMI#.
After entering the Halt state, all signals driven by the processor retain their state as they existed following the completion of the Halt special cycle. Exit Halt State The AMD-K6 processor remains in the Halt state until it samples INIT, INTR (if interrupts are enabled), NMI, RESET, or SMI# asserted. If any of these signals is sampled asserted, the processor returns to the Normal state and performs the corresponding operation. All of the normal requirements for recognition of these input signals apply within the Halt state.
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12.2
Stop Grant State
After recognizing the assertion of STPCLK#, the AMD-K6 processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and acknowledges the STPCLK# assertion by executing a Stop Grant special bus cycle. After BRDY# is sampled asserted during this cycle, and then EWBE# is also sampled asserted, the processor enters the Stop Grant state. The Stop Grant state is like the Halt state in that the processor disables most of its internal clock distribution in the Stop Grant state. In order to support the following operations, the internal PLL still runs, and some internal resources are still clocked in the Stop Grant state:
s
Enter Stop Grant State
s
s
Inquire cycles: The processor transitions to the Stop Grant Inquire state during an inquire cycle. After returning to the Stop Grant state following the inquire cycle, the processor does not execute another Stop Grant special cycle. Time Stamp Counter (TSC): The TSC continues to count in the Stop Grant state. Signal Sampling: The processor continues to sample INIT, INTR, NMI, RESET, and SMI#.
FLUSH# is not recognized in the Stop Grant state (unlike while in the Halt state). Upon entering the Stop Grant state, all signals driven by the processor retain their state as they existed following the completion of the Stop Grant special cycle. Exit Stop Grant State The AMD-K6 processor remains in the Stop Grant state until it samples STPCLK# negated or RESET asserted. If STPCLK# is sampled negated, the processor returns to the Normal state in less than 10 bus clock (CLK) periods. After the transition to the Norm al state, the processor resumes execution at the instruction boundary on which STPCLK# was initially recognized. If STPCLK# is recognized as negated in the Stop Grant state and subsequently sampled asserted prior to returning to the Normal state, the AMD-K6 processor guarantees that a minimum of one instruction is executed prior to re-entering the Stop Grant state.
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If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or SMI# are sampled asserted in the Stop Grant state, the processor latches the edge-sensitive signals (INIT, FLUSH#, NMI, and SMI#), but otherwise does not exit the Stop Grant state to service the interrupt. When the processor returns to the Normal state due to sampling STPCLK# negated, any pending interrupts are recognized after returning to the Normal state. To ensure their recognition, all of the normal requirements for these input signals apply within the Stop Grant state. If RESET is sampled asserted in the Stop Grant state, the processor immediately returns to the Normal state and the reset process begins.
12.3
Stop Grant Inquire State
The Stop Grant Inquire state is entered from the Stop Grant state or the Halt state when EADS# is sampled asserted during an inquire cycle initiated by the system logic. The AMD-K6 processor responds to an inquire cycle in the same manner as in the Normal state by driving HIT# and HITM#. If the inquire cycle hits a modified data cache line, the processor performs a writeback cycle. Following the completion of any writeback, the processor returns to the state from which it entered the Stop Grant Inquire state.
Enter Stop Grant Inquire State
Exit Stop Grant Inquire State
12.4
Stop Clock State
If the CLK signal is stopped while the AMD-K6 processor is in the Stop Grant state, the processor enters the Stop Clock state. Because all internal clocks and the PLL are not running in the Stop Clock s tat e, the St op Clock st at e represe nt s t he minimum-power state of all clock control states. The CLK signal must be held Low while it is stopped. The Stop Clock state cannot be entered from the Halt state. INTR is the only input signal that is allowed to change states while the processor is in the Stop Clock state. However, INTR is not sampled until the processor returns to the Stop Grant state.
Enter Stop Clock State
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All other input signals must remain unchanged in the Stop Clock state. Exit Stop Clock State The AMD-K6 processor returns to the Stop Grant state from the Stop Clock state after the CLK signal is started and the internal PLL has stabilized. PLL stabilization is achieved after the CLK signal has been running within its specification for a minimum of 1.0 ms. The frequency of CLK when exiting the Stop Clock state can be different than the frequency of CLK when entering the Stop Clock state. The state of the BF[2:0] signals when exiting the Stop Clock state is ignored because the BF[2:0] signals are only sampled during the falling transition of RESET.
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HLT Instruction RESET, SMI#, INIT, or INTR Asserted
Normal Mode
- Real - Virtual-8086 - Protected - SMM
STPCLK# Asserted STPCLK# Negated, or RESET Asserted
Halt State
EADS# Asserted
Writeback Completed
Stop Grant Inquire State
EADS# Asserted
Stop Grant State
Writeback Completed
CLK Started
CLK Stopped
Stop Clock State
Figure 78. Clock Control State Transitions
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13
13.1
Power and Grounding
Power Connections
The AMD-K6 processor is a dual voltage device. Two separate supply voltages are required: VCC2 and VCC3. VCC2 provides the core voltage for the processor and VCC3 provides the I/O voltage. See "Electrical Data" on page 233 for the value and range of VCC2 and VCC3. There are 28 V CC2 , 32 V CC3 , and 68 V SS pins on the AMD-K6 processor. (See "Pin Designations" on page 269 for all power and ground pin designations.) The large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. For proper operation and functionality, all VCC2, VCC3, and VSS pins must be connected to the appropriate planes in the circuit board. The power planes have been arranged in a pattern to simplify routing and minimize crosstalk on the circuit board. The isolation region between two voltage planes must be at least 0.254mm if they are in the same layer of the circuit board. ( S e e Fi g u re 7 9 o n p a g e 2 3 0 . ) I n o rd e r t o m a i n t a i n a low-impedance current sink and reference, the ground plane must never be split. Although the AMD-K6 has two separate supply voltages, there are no special power sequencing requirements. The best procedure is to minimize the time between which VCC2 and VCC3 are either both on or both off.
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0.254mm (min.) for isolation region
C5 C6 C7 C9 C1 C2 C11 C12 C10 C13
C18
C17 C19 CC3
C20 C21 C22 C23 C24 C25 C29 C16 C30 C31 CC7 C15 CC9 CC2
+ +
C26
CC4 CC5 CC6
+ + +
C27 C28
C14
VCC3 (I/O) Plane
VCC2 (Core) Plane
CC1
Figure 79. Suggested Component Placement
13.2
Decoupling Recommendations
In addition to the isolation region mentioned in "Power Connections" on page 229, adequate decoupling capacitance is required between the two system power planes and the ground plane to minimize ringing and to provide a low-impedance path for return currents. Suggested decoupling capacitor placement is shown in Figure 79. Surface mounted capacitors should be used under the processor's ZIF socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. For information and recommendations about the specific value, quantity, and location of the capacitors, see the AMD-K6 (R) Processor Power Supply Design Application Note, order# 21103.
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13.3
Pin Connection Requirements
For proper operation, the following requirements for signal pin connections must be met:
s
s s
s
Do not drive address and data signals into large capacitive loads at high frequencies. If necessary, use buffer chips to drive large capacitive loads. Leave all NC (no-connect) pins unconnected. Unused inputs should always be connected to an appropriate signal level. * Active Low inputs that are not being used should be connected to VCC3 through a 20k- pullup resistor. * Active High inputs that are not being used should be connected to GND through a pulldown resistor. Reserved signals can be treated in one of the following ways: * As no-connect (NC) pins, in which case these pins are left unconnected * As pins connected to the system logic as defined by the industry-standard Pentium interface (Socket 7) * Any combination of NC and Socket 7 pins Keep trace lengths to a minimum.
s
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14
14.1
Electrical Data
Operating Ranges
The func tional operation of the AMD-K6 proce ssor is guaranteed if the voltage and temperature parameters are within the limits defined in Table 42. Table 42. Operating Ranges
Parameter VCC2 VCC3 TCASE
Notes:
Minimum 2.755 V 3.1 V 3.135 V 0C
Typical 2.9 V 3.2 V 3.3 V
Maximum 3.045 V 3.3 V 3.6 V 70C
Comments Note 1, 2 Note 1, 3 Note 1
1. VCC2 and VCC3 are referenced from VSS. 2. VCC2 specification for 2.9 V components. 3. VCC2 specification for 3.2 V components.
14.2
Absolute Ratings
While functional operation is not guaranteed beyond the operating ranges listed in Table 42, no long-term reliability or functional damage is caused as long as the AMD-K6 processor is not subjected to conditions exceeding the absolute ratings listed in Table 43. Table 43. Absolute Ratings
Parameter VCC2 VCC3 VPIN TCASE (under bias) TSTORAGE
Note:
Minimum -0.5 V -0.5 V -0.5 V -65C -65C
Maximum 3.5 V 4.0 V VCC3+0.5 V and 4.0 V +110C +150C
Comments
Note
VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
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14.3
DC Characteristics
The DC characteristics of the AMD-K6 processor are shown in Table 44.
Table 44. DC Characteristics
Symbol VIL VIH VOL VOH ICC2 ICC2 ICC3 ILI ILO IIL IIH CIN COUT COUT CCLK CTIN CTOUT CTCK
Notes:
Parameter Description Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.9 V Power Supply Current 3.2 V Power Supply Current 3.3 V Power Supply Current Input Leakage Current Output Leakage Current Input Leakage Current Bias with Pullup Input Leakage Current Bias with Pulldown Input Capacitance Output Capacitance I/O Capacitance CLK Capacitance Test Input Capacitance (TDI, TMS, TRST#) Test Output Capacitance (TDO) TCK Capacitance
Preliminary Data Min - 0.3 V 2.0 V Max +0.8 V VCC3 +0.3 V 0.4 V 2.4 V 6.25 A 7.50 A 9.50 A 0.48 A 0.50 A 0.52 A 15 A 15 A -400 A 200 A 15 pF 20 pF 25 pF 15 pF 15 pF 20 pF 15 pF
Comments
Note 1 IOL = 4.0-mA load IOH = 3.0-mA load 166 MHz, Note 2 200 MHz, Note 2 233 MHz, Note 3 166 MHz, Note 4 200 MHz, Note 4 233 MHz, Note 4 Note 5 Note 5 Note 6 Note 7
1. 2. 3. 4. 5. 6. 7.
VCC3 refers to the voltage being applied to VCC3 during functional operation. VCC2 = 3.045 V -- The maximum power supply current must be taken into account when designing a power supply. VCC2 = 3.3 V -- The maximum power supply current must be taken into account when designing a power supply. VCC3 = 3.6 V -- The maximum power supply current must be taken into account when designing a power supply. Refers to inputs and I/O without an internal pullup resistor and 0 VIN VCC3. Refers to inputs with an internal pullup and VIL = 0.4V. Refers to inputs with an internal pulldown and VIH = 2.4V.
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14.4
Power Dissipation
Table 45 contains the typical and maximum power dissipation of the AMD-K6 processor during normal and reduced power states.
Table 45. Typical and Maximum Power Dissipation
Clock Control State Normal (Maximum Thermal Power) Normal (Typical Thermal Power) Stop Grant / Halt (Maximum) Stop Clock (Maximum)
Notes:
2.9 V Component 166 MHz 17.2 W 10.3 W 1.45 W 1.0 W 200 MHz 20.0 W 12.0 W 1.53 W 1.0 W
3.2 V Component 233 MHz 28.3 W 17.0 W 1.75 W 1.0 W
Comments Note 1, 2 Note 3 Note 4 Note 5
1. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the AMD-K6 processor. 2. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with VCC2 = 2.9 V (for the 2.9 V component) or VCC2 = 3.2 V (for the 3.2 V component), and VCC3 = 3.3 V. 3. Typical power is determined for the typical instruction sequences or functions associated with normal system operation with VCC2 = 2.9 V (for the 2.9 V component) or VCC2 = 3.2 V (for the 3.2 V component), and VCC3 = 3.3 V. 4. The CLK signal and the internal PLL are still running but most internal clocking has stopped. 5. The CLK signal, the internal PLL, and all internal clocking has stopped.
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15
I/O Buffer Characteristics
All of the AMD-K6 processor inputs, outputs, and bidirectional buffers are implemented using a 3.3 V buffer design. In addition, a subset of the processor I/O buffers include a second, higher drive strength option. These buffers can be configured to provide the higher drive strength for applications that place a heavier load on these I/O signals. AMD has developed two I/O buffer models that represent the characteristics of each of the two possible drive strength configurations supported by the AMD-K6. These two models are called the Standard I/O Model and the Strong I/O Model. AMD developed the two models to allow system designers to perform analog simulations of AMD-K6 signals that interface with the system logic. Analog simulations are used to determine a signal's time of flight from source to destination and to ensure that the system's signal quality requirements are met. Signal quality measurements include overshoot, undershoot, slope reversal, and ringing.
15.1
Selectable Drive Strength
The AMD-K6 processor samples the BRDYC# input during the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM# and W/R#. If BRDYC# is 0 during the fall of RESET, these particular outputs are configured using the higher drive strength. If BRDYC# is 1 during the fall of RESET, the standard drive strength is selected for all I/O buffers. Table 46 shows the relationship between BRDYC# and the two available drive strengths -- K6STD and K6STG. Table 46. A[20:3], ADS#, HITM#, and W/R# Strength Selection
Drive Strength Strength 1 (standard) Strength 2 (strong) BRDYC# 1 0 I/O Buffer Name K6STD K6STG
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15.2
I/O Buffer Model
AMD provides models of the AMD-K6 processor I/O buffers for system designers to use in board-level simulations. These I/O b u f f e r m o d e l s co n fo r m t o t h e I / O B u f f e r I n f o r m a t i o n Specification (IBIS), Version 2.1. The Standard I/O Model uses K6STD, the standard I/O buffer representation, for all I/O buffers. The Strong I/O Model uses K6STG, the stronger I/O buffer representation for A[20:3], ADS#, HITM#, and W/R#, and uses K6STD for the remainder of the I/O buffers. Both I/O models contain voltage versus current (V/I) and voltage versus time (V/T) data tables for accurate modeling of I/O buffer behavior. The following list characterizes the properties of each I/O buffer model:
s
s
s s
s s s s
All data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. The pullup, pulldown, power clamp, and ground clamp device V/I tables contain enough data points to accurately represent the nonlinear nature of the V/I curves. In addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-K6 processor for those simulators that yield more accurate results based on this wider range. Figure 80 and Figure 81 on page 239 illustrate the min/typ/max pulldown and pullup V/I curves for K6STD between 0V and 3.3V. The rising and falling ramp rates are specified. The min/typ/max VCC3 operating range is specified as 3.135V, 3.3V, and 3.6V, respectively. Vil = 0.8V, Vih = 2.0V, and Vmeas = 1.5V The R/L/C of the package is modeled. The capacitance of the silicon die is modeled. The model assumes the test load is 0 capacitance, resistance, inductance, and voltage.
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70 60 50 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.0
Iol (mA)
Voutput (V)
Figure 80. K6STD Pulldown V/I Curves
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 -10 -20 -30 -40 -50 -60 -70
Ioh (mA)
Voutput (V)
Figure 81. K6STD Pullup V/I Curves
15.3
I/O Model Application Note
For the AMD-K6 processor I/O Buffer IBIS Models and their application, refer to the AMD-K6(R) Processor I/O Model (IBIS) Application Note, order# 21084.
15.4
I/O Buffer AC and DC Characteristics
See "Signal Switching Characteristics" on page 241 for the AMD-K6 processor AC timing specifications. See "Electrical Data" on page 233 for the AMD-K6 processor DC specifications.
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3.3
0
3.3
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16
Signal Switching Characteristics
The AMD-K6 processor signal switching characteristics are presented in Table 47 through Table 55. Valid delay, float, setup, and hold timing specifications are listed. These specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. Table 47 and Table 48 contain the switching characteristics of the CLK input. Table 49 through Table 52 contain the timings for the normal operation signals. Table 53 contains the timings for RESET and the configuration signals. Table 54 and Table 55 contain the timings for the test operation signals. All signal timings provided are:
s
s
s
s
Measured between CLK, TCK, or RESET at 1.5 V and the corresponding signal at 1.5 V--this applies to input and output signals that are switching from Low to High, or from High to Low Based on input signals applied at a slew rate of 1 V/ns between 0 V and 3 V (rising) and 3 V to 0 V (falling) Valid within the operating ranges given in "Operating Ranges" on page 233 Based on a load capacitance (CL) of 0 pF
16.1
CLK Switching Characteristics
Table 47 and Table 48 contain the switching characteristics of the CLK input to the AMD-K6 processor for 66-MHz and 60-MHz bus operation, respectively, as measured at the voltage levels indicated by Figure 82. The CLK Period Stability specifies the variance (jitter) allowed between successive periods of the CLK input measured at 1.5 V. This parameter must be considered as one of the elements of clock skew between the AMD-K6 and the system logic.
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16.2
Clock Switching Characteristics for 66-MHz Bus Operation
Preliminary Data Min 33.3 MHz 15.0 ns 4.0 ns 4.0 ns 0.15 ns 0.15 ns 1.5 ns 1.5 ns 250 ps Max 66.6 MHz 30.0 ns 82 82 82 82 82 Note
Table 47. CLK Switching Characteristics for 66-MHz Bus Operation
Symbol Parameter Description Frequency t1 t2 t3 t4 t5
Note:
Figure
Comments In Normal Mode In Normal Mode
CLK Period CLK High Time CLK Low Time CLK Fall Time CLK Rise Time CLK Period Stability
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 KHz.
16.3
Clock Switching Characteristics for 60-MHz Bus Operation
Preliminary Data Min 30 MHz 16.67 ns 4.0 ns 4.0 ns 0.15 ns 0.15 ns 1.5 ns 1.5 ns 250 ps Max 60 MHz 33.33 ns 82 82 82 82 82 Note
Table 48. CLK Switching Characteristics for 60-MHz Bus Operation
Symbol Parameter Description Frequency t1 t2 t3 t4 t5
Note:
Figure
Comments In Normal Mode In Normal Mode
CLK Period CLK High Time CLK Low Time CLK Fall Time CLK Rise Time CLK Period Stability
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 KHz.
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t2
2.0 V 1.5 V 0.8 V t5 t1 t4 t3
Figure 82. CLK Waveform
16.4
Valid Delay, Float, Setup, and Hold Timings
Valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of CLK. During boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of TCK. The maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. Likewise, the minimum valid delay timings are used to analyze hold times to the system logic. The setup and hold time requirements for the AMD-K6 processor input signals must be met by the system logic to assure the proper operation of the AMD-K6. The setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of CLK and TCK, respectively.
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16.5
Output Delay Timings for 66-MHz Bus Operation
Preliminary Data Min 1.1 ns Max 6.3 ns 10.0 ns 1.0 ns 6.0 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns 1.0 ns 8.5 ns 10.0 ns 1.0 ns 1.0 ns 8.3 ns 7.0 ns 10.0 ns 1.0 ns 1.0 ns 8.0 ns 7.0 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns 1.3 ns 7.5 ns 10.0 ns 1.3 ns 7.5 ns 10.0 ns 1.0 ns 1.0 ns 1.1 ns 1.0 ns 1.1 ns 8.3 ns 6.8 ns 6.0 ns 6.8 ns 7.0 ns 10.0 ns 1.0 ns 5.9 ns 10.0 ns
Table 49. Output Delay Timings for 66-MHz Bus Operation
Symbol t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 Parameter Description A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay AP Valid Delay AP Float Delay APCHK# Valid Delay BE[7:0]# Valid Delay BE[7:0]# Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Write Data Valid Delay D[63:0] Write Data Float Delay DP[7:0] Write Data Valid Delay DP[7:0] Write Data Float Delay FERR# Valid Delay HIT# Valid Delay HITM# Valid Delay HLDA Valid Delay LOCK# Valid Delay LOCK# Float Delay M/IO# Valid Delay M/IO# Float Delay Figure 84 85 84 85 84 85 84 85 84 84 85 84 84 85 84 85 84 85 84 85 84 84 84 84 84 85 84 85 Comments
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Table 49. Output Delay Timings for 66-MHz Bus Operation (continued)
Symbol t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 Parameter Description PCD Valid Delay PCD Float Delay PCHK# Valid Delay PWT Valid Delay PWT Float Delay SCYC Valid Delay SCYC Float Delay SMIACT# Valid Delay W/R# Valid Delay W/R# Float Delay 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns Preliminary Data Min 1.0 ns Max 7.0 ns 10.0 ns 7.0 ns 7.0 ns 10.0 ns 7.0 ns 10.0 ns 7.3 ns 7.0 ns 10.0 ns Figure 84 85 84 84 85 84 85 84 84 85 Comments
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16.6
Input Setup and Hold Timings for 66-MHz Bus Operation
Preliminary Data Min 6.0 ns 1.0 ns 5.0 ns 1.0 ns 5.5 ns 1.0 ns 5.0 ns 1.0 ns 5.5 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 2.8 ns 1.5 ns 2.8 ns 1.5 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns Max
Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation
Symbol t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 t65 t66 t67
Notes:
Parameter Description A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time AP Setup Time AP Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Comments
Note 1 Note 1
Note 2 Note 2
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
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Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Symbol t68 t69 t70 t71 t72 t73 t74 t75 t76 t77 t78 t79 t80 t81 t82 t83 t84 t85 t86 t87 t88 t89
Notes:
Parameter Description HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time INV Setup Time INV Hold Time KEN# Setup Time KEN# Hold Time NA# Setup Time NA# Hold Time NMI Setup Time NMI Hold Time SMI# Setup Time SMI# Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
Preliminary Data Min 5.0 ns 1.5 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 4.5 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 4.5 ns 1.0 ns Max
Figure 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Comments
Note 1 Note 1 Note 2 Note 2 Note 1 Note 1
Note 2 Note 2 Note 2 Note 2 Note 1 Note 1
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
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16.7
Output Delay Timings for 60-MHz Bus Operation
Preliminary Data Min 1.1 ns Max 6.3 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns 1.0 ns 8.5 ns 10.0 ns 1.0 ns 1.0 ns 8.3 ns 7.0 ns 10.0 ns 1.0 ns 1.0 ns 8.0 ns 7.0 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns 1.3 ns 7.5 ns 10.0 ns 1.3 ns 7.5 ns 10.0 ns 1.0 ns 1.0 ns 1.1 ns 1.0 ns 1.1 ns 8.3 ns 8.0 ns 6.0 ns 8.0 ns 7.0 ns 10.0 ns 1.0 ns 7.0 ns 10.0 ns
Table 51. Output Delay Timings for 60-MHz Bus Operation
Symbol t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 Parameter Description A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay AP Valid Delay AP Float Delay APCHK# Valid Delay BE[7:0]# Valid Delay BE[7:0]# Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Write Data Valid Delay D[63:0] Write Data Float Delay DP[7:0] Write Data Valid Delay DP[7:0] Write Data Float Delay FERR# Valid Delay HIT# Valid Delay HITM# Valid Delay HLDA Valid Delay LOCK# Valid Delay LOCK# Float Delay M/IO# Valid Delay M/IO# Float Delay Figure 84 85 84 85 84 85 84 85 84 84 85 84 84 85 84 85 84 85 84 85 84 84 84 84 84 85 84 85 Comments
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Table 51. Output Delay Timings for 60-MHz Bus Operation (continued)
Symbol t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 Parameter Description PCD Valid Delay PCD Float Delay PCHK# Valid Delay PWT Valid Delay PWT Float Delay SCYC Valid Delay SCYC Float Delay SMIACT# Valid Delay W/R# Valid Delay W/R# Float Delay 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns Preliminary Data Min 1.0 ns Max 7.0 ns 10.0 ns 7.0 ns 7.0 ns 10.0 ns 7.0 ns 10.0 ns 7.6 ns 7.0 ns 10.0 ns Figure 84 85 84 84 85 84 85 84 84 85 Comments
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16.8
Input Setup and Hold Timings for 60-MHz Bus Operation
Preliminary Data Min 6.0 ns 1.0 ns 5.0 ns 1.0 ns 5.5 ns 1.0 ns 5.0 ns 1.0 ns 5.5 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 3.0 ns 1.5 ns 3.0 ns 1.5 ns 5.5 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns Max
Table 52. Input Setup and Hold Timings for 60-MHz Bus Operation
Symbol t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 t65 t66 t67
Notes:
Parameter Description A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time AP Setup Time AP Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Comments
Note 1 Note 1
Note 2 Note 2
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
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Table 52. Input Setup and Hold Timings for 60-MHz Bus Operation (continued)
Symbol t68 t69 t70 t71 t72 t73 t74 t75 t76 t77 t78 t79 t80 t81 t82 t83 t84 t85 t86 t87 t88 t89
Notes:
Parameter Description HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time INV Setup Time INV Hold Time KEN# Setup Time KEN# Hold Time NA# Setup Time NA# Hold Time NMI Setup Time NMI Hold Time SMI# Setup Time SMI# Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
Preliminary Data Min 5.0 ns 1.5 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 4.5 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 5.0 ns 1.0 ns 4.5 ns 1.0 ns Max
Figure 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Comments
Note 1 Note 1 Note 2 Note 2 Note 1 Note 1
Note 2 Note 2 Note 2 Note 2 Note 1 Note 1
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
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16.9
RESET and Test Signal Timing
Preliminary Data Min 5.0 ns 1.0 ns 15 clocks 1.0 ms 1.0 ms 2 clocks 1.0 ns 2 clocks 2 clocks 5.0 ns 1.0 ns 2 clocks 2 clocks Max
Table 53. RESET and Configuration Signals (60-MHz and 66-MHz Operation)
Symbol t90 t91 t92 t93 t94 t95 t96 t97 t98 t99 t100 t101 t102
Notes:
Parameter Description RESET Setup Time RESET Hold Time RESET Pulse Width, VCC and CLK Stable RESET Active After VCC and CLK Stable BF[2:0] Setup Time BF[2:0] Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure 87 87 87 87 87 87 87 87 87 87 87 87 87
Comments
Note 3 Note 3 Note 4 Note 2 Note 2 Note 1 Note 1 Note 2 Note 2
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sampled negated. 2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
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Table 54. TCK Waveform and TRST# Timing at 25 MHz
Symbol Parameter Description TCK Frequency t103 t104 t105 t106 t107 t108
Notes:
Preliminary Data Min 40.0 ns 14.0 ns 14.0 ns 5.0 ns 5.0 ns 30.0 ns Max 25 MHz
Figure 88 88 88 88 88 88 89
Comments
TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width
Note 1, 2 Note 1, 2 Asynchronous
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz. 2. Rise/Fall times are measured between 0.8 V and 2.0 V.
Table 55. Test Signal Timing at 25 MHz
Symbol t109 t110 t111 t112 t113 t114 t115 t116 t117 t118
Notes:
Parameter Description TDI Setup Time TDI Hold Time TMS Setup Time TMS Hold Time TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay All Inputs (Non-Test) Setup Time All Inputs (Non-Test) Hold Time
Preliminary Data Min 5.0 ns 9.0 ns 5.0 ns 9.0 ns 3.0 ns 13.0 ns 16.0 ns 3.0 ns 13.0 ns 16.0 ns 5.0 ns 9.0 ns Max
Figure 90 90 90 90 90 90 90 90 90 90
Notes Note 2 Note 2 Note 2 Note 2 Note 1 Note 1 Note 1 Note 1 Note 2 Note 2
1. Parameter is measured from the TCK falling edge. 2. Parameter is measured from the TCK rising edge.
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WAVEFORM
INPUTS
Must be steady
OUTPUTS
Steady
Can change from High to Low
Changing from High to Low
Can change from Low to High
Changing from Low to High
Don't care, any change permitted
Changing, State Unknown
(Does not apply)
Center line is high impedance state
Figure 83. Diagrams Key
Tx CLK 1.5 V Max tv Output Signal Valid n Min
Tx
Valid n +1
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
Figure 84. Output Valid Delay Timing
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CLK
1.5 V
Tx
Tx tf
Tx
Tx
Output Signal
Valid tv Min
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42 f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
Figure 85. Maximum Float Delay Timing
Tx CLK ts Input Signal th
Tx
Tx
Tx 1.5 V
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88 h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Figure 86. Input Setup and Hold Timing
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Tx CLK
Tx
***
t90 1.5 V
1.5 V
RESET
***
t92, 93 t99
t91 1.5 V t100
FLUSH# (Synchronous)
***
FLUSH#, BRDYC# (Asynchronous)
***
t97, 101 t98, 102
BF[2:0] (Asynchronous)
***
t94 t95
Figure 87. Reset and Configuration Timing
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t104
2.0 V 1.5 V 0.8 V t107 t103 t106 t105
Figure 88. TCK Waveform
t108 1.5 V
Figure 89. TRST# Timing
t103 TCK 1.5 V t109, 111 TDI, TMS t113 TDO Output Signals Input Signals t117 t118 t115 t116 t114 t110, 112
Figure 90. Test Signal Timing Diagram Chapter 16 Signal Switching Characteristics 257
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17
17.1
Thermal Design
Package Thermal Specifications
The AMD-K6 processor operating specification calls for the case temperature (T C) to be in the range of 0C to 70C. The ambient temperature (TA) is not specified as long as the case temperature is not violated. The case temperature must be measured on the top center of the package. Table 56 shows the AMD-K6 processor thermal specifications. Table 56. Package Thermal Specification
Maximum Thermal Power TC Case Temperature JC Junction-Case 2.9V Component 166MHz 0C-70C 0.77C/W 17.2 W 1.45 W 1.0 W 200MHz 20.0 W 1.53 W 1.0 W 3.2V Component 233MHz 28.3 W 1.75 W 1.0 W
Stop Grant Mode Stop Clock Mode
Figure 91 on page 260 shows the thermal model of a processor w it h a p a s sive t h e rm a l so l u t i on . The c a s e -t o -a m b i e n t temperature (T CA ) can be calculated from the following equation:
TCA = PMAX * CA = PMAX * ( IF + SA) Where: PMAX CA IF SA = = = = Maximum Power Consumption Case-to-Ambient Thermal Resistance Interface Material Thermal Resistance Sink-to-Ambient Thermal Resistance
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Temperature (Ambient)
Thermal Resistance (C/W)
TCA
Sink Case
SA
CA
IF
Figure 91. Thermal Model Figure 92 illustrates the case-to-ambient temperature (TCA) in relation to the power consumption (X-axis) and the thermal resistance (Y-axis). If the power consumption and case te mpe rat ure are known, t he ther mal re sista nce ( C A ) requirement can be calculated for a given ambient temperature (TA) value.
6.0
T
5.0
CA
Thermal Resistance (C/W)
15 C 20 C 25 C 30 C
4.0 3.0 2.0 1.0 0.0 6W
9W
12 W
15 W
18 W
Power Consumption (Watts)
Figure 92. Power Consumption vs. Thermal Resistance
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The following example calculates the required thermal resistance of a heatsink: If:
TC = 70C TA = 45C PMAX = 20.0W at 200MHz
Then:
T C - T A 25C CA ------------------ = ----------------- = 1.25 ( C W ) P MAX 20.0W
Thermal grease is recommended as interface material because it provides the lowest thermal resistance ( 0.20C/W). The required thermal resistance ( SA ) of the heatsink in this example is calculated as follows:
SA = CA - IF = 1.25 - 0.20 = 1.05 (C/W)
Heat Dissipation Path
Figure 93 illustrates the processor's heat dissipation path. Most of the heat generated by the processor is dissipated from the top surface (ceramic and lid) of the package. The small amount of heat generated from the bottom side of the processor where the processor socket blocks the convection can be safely ignored.
Ambient Temperature
Thin Lid Case temperature
Figure 93. Processor Heat Dissipation Path
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Measuring Case Temperature
The case temperature must be measured on the top center of the package where most of the heat is dissipated. Figure 94 shows the correct location for measuring the case temperature. (If a heat exchange device is installed, the thermocouple must contact the processor top surface through a drilled hole.) The case temperature is measured to ensure that the thermal solution meets the operational specification.
Thermocouple
Figure 94. Measuring Case Temperature
17.2
Layout and Airflow Considerations
A voltage regulator is required to support the lower voltage (3.3 V and lower) to the processor. In most applications, the voltage regulator is designed with power transistors. As a result, additional heatsinks are required to dissipate the heat from the power transistors. Figure 95 shows the voltage regulator placed parallel to the processor with the airflow aligned with the devices. With this alignment, the heat generated by the voltage regulator has minimal effect on the processor.
Voltage Regulator
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Voltage Regulator
Processor
Airflow
Figure 95. Voltage Regulator Placement A heatsink and fan combination can deliver much better thermal performance than a heatsink alone. More importantly, with a fan/sink the airflow requirements in a system design are not as critical. A unidirectional heatsink with a fan moves air from the top of the heatsink to the side. In this case, the best location for the voltage regulator is on the side of the processor in the path of the airflow exiting the fan sink (see Figure 96). This location guarantees that the heatsinks on both the processor and the regulator receive adequate air circulation.
Airflow
Ideal areas for voltage regulator
Figure 96. Airflow for a Heatsink with Fan
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Airflow Management in a System Design
Complete airflow management in a system is important. In addition to the volume of air, the path of the air is also important. Figure 97 shows the airflow in a dual-fan system. The fan in the front end pulls cool air into the system through intake slots in the chassis. The power supply fan forces the hot air out of the chassis. The thermal performance of the heatsink can be maximized if it is located in the shaded area, where it receives greatest benefit from this air exchange system.
Fan Main Board P/S
V e n t s Fan Vents Front
Drive Bays
Figure 97. Airflow Path in a Dual-fan System
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Figure 98 shows the airflow management in a system using the ATX form-factor. The orientation of the power supply fan and the motherboard are modified in the ATX platform design. The power supply fan pulls cool air through the chassis and across the processor. The processor is located near the power supply fan, where it can receive adequate airflow without an auxiliary fan. The arrangement significantly improves the airflow across the processor with minimum installation cost.
Main Board F a n P/S
Drive Bays
Figure 98. Airflow Path in an ATX Form-Factor System For more information about thermal solutions, see the AMD-K6(R) Processor Thermal Solution Design Application Note, order# 21085.
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18
Pin Description Diagram
Figure 99. AMD-K6(R) Processor Top-Side View Chapter 18 Pin Description Diagram 267
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Figure 100. AMD-K6(R) Processor Pin-Side View
268
Pin Description Diagram
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19
Address Pin Name
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pin Designations
Data Pin Name
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
AMD-K6(R) Processor Model 6 Functional Grouping
Control Pin No.
K-34 G-35 J-35 G-33 F-36 F-34 E-35 E-33 D-34 C-37 C-35 B-36 D-32 B-34 C-33 A-35 B-32 C-31 A-33 D-28 B-30 C-29 A-31 D-26 C-27 C-23 D-24 C-21 D-22 C-19 D-20 C-17 C-15 D-16 C-13 D-14 C-11 D-12 C-09 D-10 D-08 A-05 E-09 B-04 D-06 C-05 E-07 C-03 D-04 E-05 D-02 F-04 E-03 G-05 E-01 G-03 H-04 J-03 J-05 K-04 L-05 L-03 M-04 N-03
Test Pin No. Pin Name
TCK TDI TDO TMS TRST#
NC Pin No. Pin No.
A-37 E-17 E-25 R-34 S-33 S-35 W-33 AJ-15 AJ-23 AL-19 AN-35
Vcc2 Pin No.
A-07 A-09 A-11 A-13 A-15 A-17 B-02 E-15 G-01 J-01 L-01 N-01 Q-01 S-01 U-01 W-01 Y-01 AA-01 AC-01 AE-01 AG-01 AJ-11 AN-09 AN-11 AN-13 AN-15 AN-17 AN-19
Vcc3 Pin No.
A-19 A-21 A-23 A-25 A-27 A-29 E-21 E-27 E-37 G-37 J-37 L-33 L-37 N-37 Q-37 S-37 T-34 U-33 U-37 W-37 Y-37 AA-37 AC-37 AE-37 AG-37 AJ-19 AJ-29 AN-21 AN-23 AN-25 AN-27 AN-29
Vss Pin No.
A-03 B-06 B-08 B-10 B-12 B-14 B-16 B-18 B-20 B-22 B-24 B-26 B-28 E-11 E-13 E-19 E-23 E-29 E-31 H-02 H-36 K-02 K-36 M-02 M-36 P-02 P-36 R-02 R-36 T-02 T-36 U-35 V-02 V-36 X-02 X-36 Z-02 Z-36 AB-02 AB-36 AD-02 AD-36 AF-02 AF-36 AH-02 AJ-07 AJ-09 AJ-13 AJ-17 AJ-21 AJ-25 AJ-27 AJ-31 AJ-37 AL-37 AM-08 AM-10 AM-12 AM-14 AM-16 AM-18 AM-20 AM-22 AM-24 AM-26 AM-28 AM-30 AN-37
Pin No.
AL-35 AM-34 AK-32 AN-33 AL-33 AM-32 AK-30 AN-31 AL-31 AL-29 AK-28 AL-27 AK-26 AL-25 AK-24 AL-23 AK-22 AL-21 AF-34 AH-36 AE-33 AG-35 AJ-35 AH-34 AG-33 AK-36 AK-34 AM-36 AJ-33
Pin Name
A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BF0 BF1 BF2 BOFF# BRDY# BRDYC# BREQ CACHE# CLK D/C# EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IGNNE# INIT INTR INV KEN# LOCK# M/IO# NA# NMI PCD PCHK# PWT RESET SCYC SMI# SMIACT# STPCLK#
VCC2DET
W/R# WB/WT#
AK-08 AJ-05 AM-02 V-04 AE-05 AL-09 AK-10 AL-11 AK-12 AL-13 AK-14 AL-15 AK-16 Y-33 X-34 W-35 Z-04 X-04 Y-03 AJ-01 U-03 AK-18 AK-04 AM-04 W-03 Q-05 AN-07 AK-06 AL-05 AJ-03 AB-04 AA-35 AA-33 AD-34 U-05 W-05 AH-04 T-04 Y-05 AC-33 AG-05 AF-04 AL-03 AK-20 AL-17 AB-34 AG-03 V-34 AL-01 AM-06 AA-05
M-34 N-35 N-33 P-34 Q-33
Parity
AP DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 AK-02 D-36 D-30 C-25 D-18 C-07 F-06 F-02 N-05
INC
C-01 H-34 Y-35 Z-34 AC-35 AL-07 AN-01 AN-03 AN-05
RSVD
J-33 L-35 P-04 Q-03 Q-35 R-04 S-03 S-05 AA-03 AC-03 AC-05 AD-04 AE-03 AE-35
KEY
AH-32
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20
20.1
Package Specifications
321-Pin Staggered CPGA Package Specification
Millimeters Min 49.28 45.59 31.32 44.90 2.91 1.30 3.05 0.43 2.29 1.14 1.52 1.52 -- Max 49.78 45.85 32.59 45.10 3.63 1.52 3.30 0.51 2.79 1.40 2.29 2.54 0.13 Flatness Notes Min 1.940 1.795 1.233 1.768 0.115 0.051 0.120 0.017 0.090 0.045 0.060 0.060 -- Inches Max 1.960 1.805 1.283 1.776 0.143 0.060 0.130 0.020 0.110 0.055 0.090 0.100 0.005 Flatness Notes
Table 57. 321-Pin Staggered CPGA Package Specification
Symbol A B C D E F G H M N d e f
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Figure 101. 321-Pin Staggered CPGA Package Specification
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21
Ordering Information
Standard Products
AMD standard products are available in several operating ranges. The ordering part number (OPN) is formed by a combination of the elements below.
AMD-K6 -233 ANR Case Temperature R = 0C-70C Operating Voltage N = 3.1 V-3.3 V (Core) / 3.135 V-3.6 V (I/O) L = 2.755 V-3.045 V (Core) / 3.135 V-3.6 V (I/O) Package Type A = 321-pin CPGA Performance Rating -233 -200 -166
Family/Core AMD-K6
Table 58. Valid Ordering Part Number Combinations
OPN AMD-K6-233ANR AMD-K6-200ALR AMD-K6-166ALR
Notes:
Package Type 321-pin CPGA 321-pin CPGA 321-pin CPGA
Operating Voltage 3.1V-3.3V (Core) 3.135V-3.6V (I/O) 2.755V-3.045V (Core) 3.135V-3.6V (I/O) 2.755V-3.045V (Core) 3.135V-3.6V (I/O)
Case Temperature 0C-70C 0C-70C 0C-70C
This table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly-released combinations.
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Ordering Information
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AMD-K6(R) Processor Data Sheet
Part Two
AMD-K6 Processor Model 7
The AMD-K6(R) Processor Data Sheet supports the Model 6 and Model 7 versions of the AMD-K6 processor family. Model 6 refers to the AMD-K6 manufactured with 0.35-micron process technology and Model 7 refers to the AMD-K6 manufactured with 0.25-micron process technology. Part Two (chapters 22-42) contains information regarding new specifications and differences that pertain only to Model 7 as compared to Model 6.
(R)
Part Two
AMD-K6(R) Processor Model 7
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AMD-K6(R) Processor Model 7
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22
s
AMD-K6(R) Processor
s
s s s s s s s
Advanced 6-Issue RISC86(R) Superscalar Microarchitecture x Seven parallel specialized execution units x Multiple sophisticated x86-to-RISC86 instruction decoders x Advanced two-level branch prediction x Speculative execution x Out-of-order execution x Register renaming and data forwarding x Issues up to six RISC86 instructions per clock Large On-Chip Split 64-Kbyte Level-One (L1) Cache x 32-Kbyte instruction cache with additional predecode cache x 32-Kbyte writeback dual-ported data cache x MESI protocol support High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit High-Performance Industry-Standard MMXTM Instructions 321-Pin Ceramic Pin Grid Array (CPGA) Package (Socket 7 Compatible) Industry-Standard System Management Mode (SMM) IEEE 1149.1 Boundary Scan Full x86 Binary Software Compatibility 0.25-Micron Process Technology
AMD continues to deliver leading-edge processor solutions by advancing the highly successful AMD-K6(R) processor with state-of-the-art 0.25-micron process technology. The AMD-developed 0.25-micron process technology enables the AMD-K6 processor to deliver higher performance with a lower core voltage and lower power dissipation. This new version of the AMD-K6 processor continues to leverage today's cost-effective infrastructure to deliver a superior price/performance PC solution. To provide industry-leading performance, the AMD-K6 processor incorporates the innovative and efficient RISC86 microarchitecture, a large 64-Kbyte level-one cache (32-Kbyte dual-ported data cache, 32-Kbyte instruction cache with predecode data), a powerful IEEE 754-compatible and 854-compatible floating-point execution unit, and a high-performance multimedia execution unit for executing industry-standard MMX instructions. These features have been combined to deliver industry leadership in 16-bit and 32-bit performance, providing exceptional performance for both Windows(R) 95 and Windows NTTM software bases.
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The AMD-K6 processor's RISC86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. Advanced design techniques implemented in the AMD-K6 include multiple x86 instruction decode, single-clock internal RISC operations, seven execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. In addition, the processor supports the industry's most advanced branch prediction logic by implementing an 8192-entry branch history table, the industry's only branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. These design techniques enable the AMD-K6 processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. The AMD-K6 processor is fully x86 binary code compatible. AMD's extensive experience through four generations of x86 processors has been carefully integrated into the AMD-K6 to provide complete compatibility with Windows 95, Windows 3.x, Windows NT, DOS, OS/2, Unix, Solaris, NetWare(R) , Vines, and other leading x86 operating systems and applications. The AMD-K6 processor is Socket 7 compatible, allowing the processor to be quickly and easily integrated into a mature and cost-effective industry-standard infrastructure of motherboards, chipsets, power supplies, and thermal designs. AMD has designed, manufactured, and delivered over 50 million Microsoft Windows-compatible processors in the last five years alone. The AMD-K6 processor is the next addition to this long line of processors. With its combination of state-of-the-art features, industry-leading performance, high-performance multimedia engine, full x86 compatibility, and low-cost infrastructure, the AMD-K6 is the superior choice for mainstream personal computers.
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23
Internal Architecture
The internal architecture of the AMD-K6 processor remains unchanged with the integration of 0.25-micron process technology. For information about the internal architecture of the AMD-K6 processor Model 7, see Chapter 2, "Internal Architecture" on page 7.
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24
Software Environment
This chapter briefly describes the AMD-K6 Model-Specific Registers (MSRs) and x86 instructions supported by the AMD-K6 processor Model 7 that are not supported by the AMD-K6 processor Model 6. For an overview of the AMD-K6 processor's x86 software environment and a description of the remaining data types, registers, operating modes, interrupts, and instructions s u p p o r t e d by t h e A M D -K 6 a rch i t e c t u re a n d d e s i g n implementation, see Chapter 3, "Software Environment" on page 21.
24.1
Registers
The AMD-K6 processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, MMX, EFLAGS, control, task, debug, test, and descriptor/memory-management registers. This section provides information on the Model-Specific Registers (MSRs) supported by the AMD-K6 processor Model 7 that are not supported by the AMD-K6 processor Model 6. For information about the remaining AMD-K6 registers, see Chapter 3, "Software Environment" on page 21. Note: Areas of the register designated as Reserved should not be modified by software.
Model-Specific Registers (MSR)
The AMD-K6 processor Model 7 supports two additional MSRs as compared to the AMD-K6 processor Model 6. The value in the ECX register selects the MSR to be addressed by the RDMSR and WRMSR instructions. The values in EAX and EDX are used as inputs and outputs by the RDMSR and WRMSR instructions. Table 59 lists the new MSRs and the corresponding value of the ECX register. Figures 102 and 103 show the MSR formats.
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Table 59. Model-Specific Registers (MSRs)
Model-Specific Register Extended Feature Enable Register (EFER) SYSCALL/SYSRET Target Address Register (STAR) Value of ECX C000_0080h C000_0081h
For mo re info rma tio n abo ut the RD MSR and WRMSR instructions, see the AMD K86TM Family BIOS and Software Tools Development Guide, order# 21062. Extended Feature Enable Register (EFER). T h e E x t e n d e d Fe a t u re Enable Register (EFER) contains the control bits that enable the extended features of the AMD-K6. Figure 102 shows the format of the EFER register, and Table 60 defines the function of each bit in the EFER register.
63 1 0 S C E Symbol Description SCE System Call/Return Extension Bit 0
Reserved
Figure 102. Extended Feature Enable Register (EFER) Table 60. Extended Feature Enable Register (EFER) Definition
Bit 63-1 0 Reserved System Call/Return Extension (SCE) Description R/W R R/W
SYSCALL/SYSRET Target Address Register (STAR). The SYSCALL/SYSRET Target Address Register (STAR) contains the target EIP address used by the SYSCALL instruction and the 16-bit code and stack segment selector bases used by the SYSCALL and SYSRET instructions. Figure 103 shows the format of the STAR register, and Table 61 defines the function of each bit of the STAR register. For more information, see the SYSCALL and SYSRET Instruction Specification Application Note, order# 21086.
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63 SYSRET CS Selector and SS Selector Base
48 47 SYSCALL CS Selector and SS Selector Base
32 31 Target EIP Address
0
Figure 103. SYSCALL/SYSRET Target Address Register (STAR) Table 61. SYSCALL/SYSRET Target Address Register (STAR) Definition
Bit 63-48 47-32 31-0 Description SYSRET CS and SS Selector Base SYSCALL CS and SS Selector Base Target EIP Address R/W R/W R/W R/W
24.2
Instructions Supported by the AMD-K6(R) Processor
This section documents the x86 instructions supported by the AMD-K6 processor Model 7 that are not supported by AMD-K6 processor Model 6. For information about the remaining x86 instructions supported by the AMD-K6 processor Model 6, see Chapter 3, "Software Environment" on page 21. Table 62 shows the instruction mnemonic, opcode, modR/M by t e , d e c o d e t y p e, a n d R I S C 8 6 o p e ra t i o n ( s ) fo r e a ch instruction. The first column of the tables indicates the instruction mnemonic and operand types. The second and third columns list all applicable opcode bytes. The fourth column lists the modR/M byte when used by the instruction. The modR/M byte defines the instruction as a register or memory form. The fifth column lists the type of instruction decode -- short, long, and vector. The sixth column lists the type of RISC86 operation(s) required for the instruction.
Table 62. Integer Instructions
Instruction Mnemonic SYSCALL SYSRET First Byte 0Fh 0Fh Second Byte 05h 07h ModR/M Byte Decode Type vector vector RISC86(R) Opcodes
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25
Logic Symbol Diagram
Clock Voltage Detection
CLK
BF[2:0]
VCC2DET VCC2H/L#
Bus Arbitration
AHOLD BOFF# BREQ HLDA HOLD
BRDY# BRDYC# D[63:0] DP[7:0] PCHK#
Data and Data Parity
Address and Address Parity
A20M# A[31:3] AP ADS# ADSC# APCHK# BE[7:0]#
EADS# HIT# HITM# INV
Inquire Cycles
Cycle Definition and Control
D/C# EWBE# LOCK# M/IO# NA# SCYC W/R#
AMD-K6(R)
Processor Model 7
FERR# IGNNE#
Floating-Point Error Handling
Cache Control
CACHE# KEN# PCD PWT WB/WT#
FLUSH# INIT INTR NMI RESET SMI# SMIACT# STPCLK#
External Interrupts, SMM, Reset and Initialization
TCK
TDI
TDO
TMS TRST#
JTAG Test
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26
Signal Descriptions
This chapter provides a description of the signals designed to i n d i c a t e t o s y s t e m l o g i c t h e s p e c i f i e d d u a l -vo l t a g e re q u ire m e n t s o f t h e A M D -K 6 p ro c e ss o r M o d e l 7 . Fo r information about the remaining AMD-K6 processor Model 7 signals, see Chapter 5, "Signal Descriptions" on page 79.
26.1
Summary
VCC2DET (VCC2 Detect)
Output
VCC2DET is internally tied to VSS (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the VCC2 and VCC3 pins. The VCC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the V CC3 pins. Upon sampling VCC2DET Low, system logic should sample VCC2H/L# to identify core voltage requirements. VCC2DET always equals 0 and is never floated--even during Tri-State Test mode.
Driven
26.2
Summary
VCC2H/L# (VCC2 High/Low)
Output
VCC2H/L# is internally tied to VSS (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the VCC2 pins. The VCC2 pins supply voltage to the processor core, independent of the voltage supplied to the I/O buffers on the V CC3 pins. Upon sampling VCC2DET Low to identify dual-voltage processor requirements, system logic should sample VCC2H/L# to identif y the core voltage requirements for 2.9 V and 3.2 V products (High) and 2.2 V products (Low). VCC2H/L# always equals 0 and is never floated for 2.2 V products--even during Tri-State Test mode. To ensure proper
Driven
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operation for 2.9V and 3.2V products, system logic that samples VCC2H/L# should design a weak pullup resistor for this signal. Table 63. Output Pin Float Conditions
Name VCC2DET VCC2H/L#
Notes:
Floated At: Always Driven Always Driven
Note * *
*
All outputs except VCC2DET, VCC2H/L#, and TDO float during Tri-State Test mode.
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Bus Cycles
The timing and relationship of bus signals for the AMD-K6 p ro c e s s o r re m a i n u n ch a n g e d w i t h t h e i n t e g ra t i o n o f 0.25-micron process technology. For information about bus cycles for the AMD-K6 processor Model 7, see Chapter 6, "Bus Cycles" on page 121.
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Power-on Configuration and Initialization
T h i s ch a p t e r p rov i d e s i n f o r m a t i o n o n t h e p o we r -o n configuration and initialization states of the AMD-K6 processor Model 7 that differ from the states of the AMD-K6 processor M o d e l 6 . Fo r m o re i n f o r m a t i o n a b o u t t h e p o we r -o n configuration and initialization states of the AMD-K6 processor Model 7, see Chapt er 7, " Power-on Conf iguration and Initialization" on page 167.
28.1
State of Processor After RESET
Table 64 shows the state of processor outputs immediately after RESET is sampled asserted. The processor outputs shown are those supported by the AMD-K6 processor Model 7 that are not supported by the outputs of the AMD-K6 processor Model 6. For information about the state of the remaining processor outputs after RESET for the AMD-K6 processor Model 7, see Chapter 7, "Power-on Configuration and Initialization" on page 167. Table 64. Output Signal State After RESET
Signal VCC2H/L# State Low
Output Signals
Table 65 on page 292 shows the state of the architecture register EDX and the Model-Specific Registers EFER and STAR after the processor has completed its initialization due to the recognition of RESET. EDX is supported in both the AMD-K6 processor Model 7 and AMD-K6 processor Model 6. EFER and STAR are supported only in the AMD-K6 processor Model 7.
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Table 65. Register State After RESET
Register EDX EFER STAR
Notes:
State (Hex) 0000_057Xh 0000_0000_0000_0000h 0000_0000_0000_0000h
Notes 1 2 2
1. EDX contains the AMD-K6 processor signature, where X indicates the processor Stepping ID. 2. The contents of these registers are preserved following the recognition of INIT.
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29
Cache Organization
The internal cache organization of the AMD-K6 processor remains unchanged with the integration of 0.25-micron process technology. For information about the cache organization of the A M D -K 6 p ro c e s s o r M o d e l 7 , s e e C h a p t e r 8 , " C a c h e Organization" on page 171.
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Floating-Point and Multimedia Execution Units
The floating-point and multimedia execution units of the AMD-K6 processor remain unchanged with the integration of 0.25-micron process technology. For information about the floating-point and multimedia execution units of the AMD-K6 processor Model 7, see Chapter 9, "Floating-Point and Multimedia Execution Units" on page 189.
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System Management Mode (SMM)
The implementation of SMM in the AMD-K6 processor remains unchanged with the integration of 0.25-micron process technology. For information about the implementation of SMM in the AMD-K6 processor Model 7, see Chapter 10, "System Management Mode (SMM)" on page 193.
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32
Test and Debug
The AMD-K6 processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. In addition, the debug features of the processor allow designers to debug the instruction execution of software components. This chapter describes the following test and debug features of the AMD-K6 processor Model 7 that differ from those supported by the AMD-K6 processor Model 6:
s
s
Tri-State Test Mode--A test mode that causes the processor to float its output and bidirectional pins. Boundary-Scan Test Access Port (TAP)--The Joint Test Action Group (JTAG) test access function defined by the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) specification.
For more information about the test and debug modes of the AMD-K6 processor Model 7, see Chapter 11, "Test and Debug" on page 203.
32.1
Tri-State Test Mode
The VCC2DET, VCC2H/L#, and TDO signals are the only outputs not floated in the Tri-State Test mode. VCC2DET and VCC2H/L# must remain Low to ensure the system continues to supply the specified processor core voltage to the V CC2 pins. TDO is never floated because the Boundary-Scan Test Access Port must remain enabled at all times, including during the Tri-State Test mode. The Tri-State Test mode is exited when the processor samples RESET asserted.
32.2
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. The AMD-K6 processor supports the TAP standard defined in the
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IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) specification. TAP Registers Device Identification Register (DIR). The DIR is a 32-bit Test Data Register selected during the execution of the IDCODE instruction. The fields of the DIR and their values are shown in Table 66 and are defined as follows:
s
s
s
Version Code--This 4-bit field is incremented by AMD manufacturing for each major revision of silicon. Part Number--This 16-bit field identifies the specific processor model. Manufacturer--This 11-bit field identifies the manufacturer of the component (AMD). LSB--The least significant bit (LSB) of the DIR is always set to 1, as specified by the IEEE 1149.1 standard.
s
Table 66. Device Identification Register
Version Code (Bits 31-28) Xh Part Number (Bits 27-12) 0570h Manufacturer (Bits 11-1) 00000000001b LSB (Bit 0) 1b
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Clock Control
The clock control modes of the AMD-K6 processor remain unchanged with the integration of 0.25-micron process technology. For information about the clock control modes of the AMD-K6 processor Model 7, see Chapter 12, "Clock Control" on page 223.
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Clock Control
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34
Power and Grounding
The fundamental power and ground requirements of the AMD-K6 processor remain unchanged with the integration of 0.25-micron process technology. For information about decoupling recommendations and pin connection requirements of the AMD-K6 processor Model 7, see the AMD-K6(R) Processor Power Supply Design Application Note, order# 21103 and Chapter 13, "Power and Grounding" on page 229.
34.1
Power Connections
The AMD-K6 processor is a dual voltage device. Two separate supply voltages are required--VCC2 and VCC3. VCC2 provides the core voltage for the processor and VCC3 provides the I/O voltage. See "Electrical Data" on page 233 for the value and range of VCC2 and VCC3. There are 28 V CC2, 32 V CC3, and 68 VSS pins on the AMD-K6 processor. (See "Pin Designations" on page 269 for all power and ground pin designations.) The large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. For more information about power connections requirements for the AMD-K6 processor Model 7, see Chapter 13, "Power and Grounding" on page 229.
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35.1
Electrical Data
Operating Ranges
The functional operation of the AMD-K6 processor Model 7 is guaranteed if the voltage and temperature parameters are within the limits defined in Table 67. Table 67. Operating Ranges
Parameter VCC2 VCC3 TCASE
Notes:
Minimum 2.1 V 3.135 V 0C
Typical 2.2 V 3.30 V
Maximum 2.3 V 3.6 V 70C
Comments Note 1, 2 Note 1
1. VCC2 and VCC3 are referenced from VSS. 2. VCC2 specification for 2.2 V components.
35.2
Absolute Ratings
Functional operation of the AMD-K6 processor Model 7 is not guaranteed beyond the operating ranges listed in Table 67. Exposure to conditions outside these operating ranges for extended periods of time can affect long-term reliability. Permanent damage can occur if the absolute ratings listed in Table 68 are exceeded. Table 68. Absolute Ratings
Parameter VCC2 VCC3 VPIN TCASE (under bias) TSTORAGE
Note:
Minimum -0.5 V -0.5 V -0.5 V -65C -65C
Maximum 2.5 V 3.6 V VCC3 + 0.5 V and 4.0 V +110C +150C
Comments
Note
VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
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35.3
DC Characteristics
The DC characteristics of the AMD-K6 processor Model 7 are shown in Table 69.
Table 69. DC Characteristics
Symbol VIL VIH VOL VOH Parameter Description Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 V 5.95 A ICC2 2.2 V Power Supply Current 6.50 A 7.05 A 7.49 A 0.50 A ICC3 3.3 V Power Supply Current 0.52 A 0.54 A 0.56 A ILI ILO IIL IIH CIN COUT COUT CCLK CTIN CTOUT CTCK
Notes:
Preliminary Data Min -0.3 V 2.0 V Max +0.8 V VCC3 +0.3V 0.4 V
Comments
Note 1 IOL = 4.0-mA load IOH = 3.0-mA load 200 MHz, Note 2 233 MHz, Note 2 266 MHz, Note 2 300 MHz, Note 2 200 MHz, Note 3 233 MHz, Note 3 266 MHz, Note 3 300 MHz, Note 3 Note 4 Note 4 Note 5 Note 6
Input Leakage Current Output Leakage Current Input Leakage Current Bias with Pullup Input Leakage Current Bias with Pulldown Input Capacitance Output Capacitance I/O Capacitance CLK Capacitance Test Input Capacitance (TDI, TMS, TRST#) Test Output Capacitance (TDO) TCK Capacitance
15 A 15 A -400 A 200 A 10 pF 15 pF 20 pF 10 pF 10 pF 15 pF 10 pF
1. 2. 3. 4. 5. 6.
VCC3 refers to the voltage being applied to VCC3 during functional operation. VCC2 = 2.3 V -- The maximum power supply current must be taken into account when designing a power supply. VCC3 = 3.6 V -- The maximum power supply current must be taken into account when designing a power supply. Refers to inputs and I/O without an internal pullup resistor and 0 VIN VCC3. Refers to inputs with an internal pullup and VIL = 0.4 V. Refers to inputs with an internal pulldown and VIH = 2.4 V.
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35.4
Power Dissipation
Table 70 contains the typical and maximum power dissipation of the AMD-K6 processor Model 7 during normal and reduced power states.
Table 70. Typical and Maximum Power Dissipation
Clock Control State Normal (Maximum Thermal Power) Normal (Typical Thermal Power) Stop Grant / Halt (Maximum) Stop Clock (Maximum)
Notes:
2.2 V Component 200 MHz 12.45 W 7.50 W 2.44 W 2.25 W 233 MHz 13.50 W 8.10 W 2.46 W 2.25 W 266 MHz 14.55 W 8.75 W 2.48 W 2.25 W 300 MHz 15.40 W 9.25 W 2.50 W 2.25 W
Comments Note 1, 2 Note 3 Note 4 Note 5
1. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the AMD-K6 processor. 2. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with VCC2 = 2.2 V and VCC3 = 3.3 V. 3. Typical power is determined for the typical instruction sequences or functions associated with normal system operation with VCC2 = 2.2 V and VCC3 = 3.3 V. 4. The CLK signal and the internal PLL are still running but most internal clocking has stopped. 5. The CLK signal, the internal PLL, and all internal clocking has stopped.
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Electrical Data
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I/O Buffer Characteristics
The I/O buffer characteristics of the AMD-K6 processor Model 7 are different from those of the AMD-K6 processor Model 6. These differences are minor and are reflected in the I/O Buffer IBIS Models that are developed for each processor. For the IBIS models and their application, refer to the AMD-K6(R) Processor I/O Model Application Note, order# 21084. Despite these minor differences, the AC timing specifications and the DC specifications of the I/O buffers remain unchanged with the integration of 0.25-micron process technology. For additional information about the I/O buffer characteristics of the AMD-K6 processor Model 7, see Chapter 15, "I/O Buffer Characteristics" on page 237.
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I/O Buffer Characteristics
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Signal Switching Characteristics
The signal switching characteristics of the AMD-K6 processor remain unchanged with the integration of 0.25-micron process technology. For information about the signal switching characteristics of the AMD-K6 processor Model 7, see Chapter 16, "Signal Switching Characteristics" on page 241.
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Signal Switching Characteristics
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38.1
Thermal Design
Package Thermal Specifications
The AMD-K6 processor Model 7 operating specification calls for the case temperature (TC) to be in the range of 0C to 70C. The ambient temperature (TA) is not specified as long as the case temperature is not violated. The case temperature must be measured on the top center of the package. Table 71 shows the AMD-K6 processor thermal specifications. Table 71. Package Thermal Specification
Maximum Thermal Power TC Case Temperature JC Junction-Case 200 MHz 0C-70C 1.7 C/W 12.45 W 2.44 W 2.25 W 2.2 V Component 233 MHz 13.50 W 2.46 W 2.25 W 266 MHz 14.55 W 2.48 W 2.25 W 300 MHz 15.40 W 2.50 W 2.25 W
Stop Grant Mode Stop Clock Mode
For information about thermal solutions, see the AMD-K6 (R) Processor Thermal Solution Design Application Note, order# 21085.
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Thermal Design
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39
Pin Description Diagram
Figure 104. AMD-K6(R) Processor Model 7 Top-Side View Chapter 39 Pin Description Diagram 315
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Figure 105. AMD-K6(R) Processor Model 7 Pin-Side View
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Pin Description Diagram
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40
Address Pin Name
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pin Designations
Data Pin Name
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
AMD-K6(R) Processor Model 7 Functional Grouping
Control Pin No.
K-34 G-35 J-35 G-33 F-36 F-34 E-35 E-33 D-34 C-37 C-35 B-36 D-32 B-34 C-33 A-35 B-32 C-31 A-33 D-28 B-30 C-29 A-31 D-26 C-27 C-23 D-24 C-21 D-22 C-19 D-20 C-17 C-15 D-16 C-13 D-14 C-11 D-12 C-09 D-10 D-08 A-05 E-09 B-04 D-06 C-05 E-07 C-03 D-04 E-05 D-02 F-04 E-03 G-05 E-01 G-03 H-04 J-03 J-05 K-04 L-05 L-03 M-04 N-03
Test Pin No. Pin Name
TCK TDI TDO TMS TRST#
NC Pin No. Pin No.
A-37 E-17 E-25 R-34 S-33 S-35 W-33 AJ-15 AJ-23 AL-19 AN-35
Vcc2 Pin No.
A-07 A-09 A-11 A-13 A-15 A-17 B-02 E-15 G-01 J-01 L-01 N-01 Q-01 S-01 U-01 W-01 Y-01 AA-01 AC-01 AE-01 AG-01 AJ-11 AN-09 AN-11 AN-13 AN-15 AN-17 AN-19
Vcc3 Pin No.
A-19 A-21 A-23 A-25 A-27 A-29 E-21 E-27 E-37 G-37 J-37 L-33 L-37 N-37 Q-37 S-37 T-34 U-33 U-37 W-37 Y-37 AA-37 AC-37 AE-37 AG-37 AJ-19 AJ-29 AN-21 AN-23 AN-25 AN-27 AN-29
Vss Pin No.
A-03 B-06 B-08 B-10 B-12 B-14 B-16 B-18 B-20 B-22 B-24 B-26 B-28 E-11 E-13 E-19 E-23 E-29 E-31 H-02 H-36 K-02 K-36 M-02 M-36 P-02 P-36 R-02 R-36 T-02 T-36 U-35 V-02 V-36 X-02 X-36 Z-02 Z-36 AB-02 AB-36 AD-02 AD-36 AF-02 AF-36 AH-02 AJ-07 AJ-09 AJ-13 AJ-17 AJ-21 AJ-25 AJ-27 AJ-31 AJ-37 AL-37 AM-08 AM-10 AM-12 AM-14 AM-16 AM-18 AM-20 AM-22 AM-24 AM-26 AM-28 AM-30 AN-37
Pin No.
AL-35 AM-34 AK-32 AN-33 AL-33 AM-32 AK-30 AN-31 AL-31 AL-29 AK-28 AL-27 AK-26 AL-25 AK-24 AL-23 AK-22 AL-21 AF-34 AH-36 AE-33 AG-35 AJ-35 AH-34 AG-33 AK-36 AK-34 AM-36 AJ-33
Pin Name
A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BF0 BF1 BF2 BOFF# BRDY# BRDYC# BREQ CACHE# CLK D/C# EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IGNNE# INIT INTR INV KEN# LOCK# M/IO# NA# NMI PCD PCHK# PWT RESET SCYC SMI# SMIACT# STPCLK#
VCC2DET VCC2H/L#
W/R# WB/WT#
AK-08 AJ-05 AM-02 V-04 AE-05 AL-09 AK-10 AL-11 AK-12 AL-13 AK-14 AL-15 AK-16 Y-33 X-34 W-35 Z-04 X-04 Y-03 AJ-01 U-03 AK-18 AK-04 AM-04 W-03 Q-05 AN-07 AK-06 AL-05 AJ-03 AB-04 AA-35 AA-33 AD-34 U-05 W-05 AH-04 T-04 Y-05 AC-33 AG-05 AF-04 AL-03 AK-20 AL-17 AB-34 AG-03 V-34 AL-01 AN-05 AM-06 AA-05
M-34 N-35 N-33 P-34 Q-33
Parity
AP DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 AK-02 D-36 D-30 C-25 D-18 C-07 F-06 F-02 N-05
INC
C-01 H-34 Y-35 Z-34 AC-35 AL-07 AN-01 AN-03
RSVD
J-33 L-35 P-04 Q-03 Q-35 R-04 S-03 S-05 AA-03 AC-03 AC-05 AD-04 AE-03 AE-35
KEY
AH-32
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Pin Designations
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41
Package Specifications
The package specifications for the AMD-K6 processor remain unchanged with the integration of 0.25-micron process technology. For information about the package specifications of the AMD-K6 processor Model 7, see Chapter 20, "Package Specifications" on page 271.
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Package Specifications
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42
Ordering Information
Standard AMD-K6(R) Processor Model 7 Products
AMD standard products are available in several operating ranges. The ordering part number (OPN) is formed by a combination of the elements below.
AMD-K6 /300 A FR Case Temperature R = 0C-70C Operating Voltage F = 2.1 V-2.3 V (Core) / 3.135 V-3.6 V (I/O) Package Type A = 321-pin CPGA
Performance Rating /300 /266 /233 /200 Family/Core AMD-K6
Table 72. Valid Ordering Part Number Combinations
OPN AMD-K6/300AFR AMD-K6/266AFR AMD-K6/233AFR AMD-K6/200AFR
Notes:
Package Type 321-pin CPGA 321-pin CPGA 321-pin CPGA 321-pin CPGA
Operating Voltage 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 2.1V-2.3V (Core) 3.135V-3.6V (I/O)
Case Temperature 0C-70C 0C-70C 0C-70C 0C-70C
This table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly-released combinations.
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Index
Numerics
0.25-micron process technology . . . . . . . . . . . . . . . . . 1, 3, 275 0.35-micron process technology . . . . . . . . . . . . . . . . . 1, 3, 275 321-Pin Staggered CPGA Package Specification. . . . . . . . 271 60-MHz Bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 250 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 66-MHz Bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 246 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Block Diagram, AMD-K6 Processor . . . . . . . . . . . . . . . . . . . 10 BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87, 150 Locked Operation with . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . 205, 299 BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Branch execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 prediction . . . . . . . . . . . . . . . . . . . . . . . 5-6, 9, 20, 277-278 prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 167, 237 BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Buffer Characteristics, I/O . . . . . . . . . . . . . . . . . . . . . 237, 309 Buffer Model, I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Burst Reads, Pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Burst Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Burst Ready Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 167 Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Bus address . . . . . . . . . . . . . 82-85, 94, 121, 142, 146, 148, 183 arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 136 backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121, 289 cycles, special. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 data . . . . . . . . . . . . . . . . . . . . . . 82, 85, 88, 92-93, 108, 111 . . . . . . . . . . . . . . . . . . . . . . . . . .124-126, 142, 148, 152 enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 hold request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Bus States address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data-NA# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BYPASS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
A
A[20:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237-238 A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 194 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . 187 Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 305 Acknowledge, Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Parity Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Stack, Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address Bus . . . . . . . . . . . 81-85, 94, 121, 142, 146, 148, 183 ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81, 237-238 ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, 224 -initiated inquire hit to modified line. . . . . . . . . . . . . . . 146 -initiated inquire hit to shared or exclusive line . . . . . . 144 -initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Airflow Consideration, Layout and . . . . . . . . . . . . . . . . . . . 262 Airflow Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Allocate, Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 AMD-K6 MMX Enhanced Processor . . . . . . . . . . . . . . . . 5, 277 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 instructions supported . . . . . . . . . . . . . . . . . . . . . . . . 49, 283 microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . . 7 Model 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 275 Model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 275 AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APCHK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Application Note, I/O Model . . . . . . . . . . . . . . . . . . . . . . . . 239 Architecture, Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 279
B
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Base Address, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 167, 227 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Bits, Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 172
C
Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 flush. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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inhibit, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 MESI states in the data . . . . . . . . . . . . . . . . . . . . . . . . . . 172 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171, 293 snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 175 Cacheable Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Cacheable Page, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . 178 Cache-Line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177, 184 Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Capture-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Characteristics I/O buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237, 309 I/O Buffer AC and DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223, 301 Clock States halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161, 226-227 stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161, 225 stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Coherency States, Writethrough vs. Writeback. . . . . . . . . 187 Coherency, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Compatibility, Floating-Point and MMX instructions . . . . 191 Configuration and Initialization, Power-on . . . . . . . . 167, 291 Connection Requirements, Pin . . . . . . . . . . . . . . . . . . . . . . 231 Connections, Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . 229, 303 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control Unit, Scheduler/Instruction . . . . . . . . . . . . . . . . . . . . 9 Counter, Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Cycle, Hold and Hold Acknowledge . . . . . . . . . . . . . . . . . . 136 Cycle, Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Cycles bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121, 289 inquire . . . . . . . 79-84, 94, 98-99, 112, 116, 132, 136, 138 . . . . . . . . . . . . . . . . .140, 142, 144-146, 148, 150, 154 . . . . . . . . . . . . . . . . . . . . . . . . . 183-187, 215, 223-226 inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 136 interrupt acknowledge . . . . . . . . . . 80, 83, 85, 91, 106, 115 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 81 pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 writeback . . . . . . . . . . . . . . . . . .79, 81-82, 95, 98, 116, 132 . . . . . . . . . . . . . . . . . . . . . 140, 144, 146, 148, 150, 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174-175, 216, 226
Data Bus . . . . . . . . . . . . . . . . . . . . 82, 85, 88, 92-93, 108, 111 . . . . . . . . . . . . . . . . . . . . . . . . . .124-126, 142, 148, 152 Data Cache, MESI States in the . . . . . . . . . . . . . . . . . . . . . 172 Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Data Types floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data/Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234, 306 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 216 DR3-DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR5-DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Decode, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Descriptions, Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 287 Design, Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259, 313 Designations, Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 317 Device Identification Register . . . . . . . . . . . . . . . . . . 210, 300 Diagram, Pin Description . . . . . . . . . . . . . . . . . . . . . . 267, 315 Diagrams, Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210, 300 Disabling, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Dissipation, Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235, 307 DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DR3-DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR5-DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Drive Strength, Selectable . . . . . . . . . . . . . . . . . . . . . . . . . 237
E
EADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 305 Environment, Software . . . . . . . . . . . . . . . . . . . . . . . . . 21, 281 EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 224 Exception . . . . . 83-84, 93, 96, 108, 160, 191, 202, 220-222 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 floating-point . . . . . . . . . . . . . . . . . . . . . . . 96, 100, 189-191 machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Exception Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 handling floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 189 interrupts, and debug in SMM . . . . . . . . . . . . . . . . . . . . 202 MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Execution Unit, Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Execution Unit, Multimedia . . . . . . . . . . . . . . . . . . . . . . . . 191 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189, 295 External Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 External Write Buffer Empty . . . . . . . . . . . . . . . . . . . . . . . . 95 EXTEST instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
D
D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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F
FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 191 Fetch, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 288 Floating-Point and MMX instruction compatibility . . . . . . . . . . . . . . . . 191 and multimedia execution units . . . . . . . . . . . . . . . 189, 295 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189, 295 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . 97, 167, 184, 204, 224 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227, 242, 253 operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 91, 167 Frequency Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
G
Gate Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 48 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . 21, 281 Grounding, Power and . . . . . . . . . . . . . . . . . . . . . . . . . 229, 303
H
Halt State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . 189 Heat Dissipation Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 HIGHZ instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 History Table, Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Hit to Modified Line, AHOLD-Initiated Inquire . . . . . . . . 146 Hit to Modified Line, HOLD-Initiated Inquire . . . . . . . . . 140 Hit to Shared or Exclusive Line, AHOLD-Initiated Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Hit to Shared or Exclusive Line, HOLD-Initiated Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98, 237-238 HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Hold Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .99, 136-138 Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . 136 Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241, 255 HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 140 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I
I/O buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 237, 309 buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 135 model application note. . . . . . . . . . . . . . . . . . . . . . . . . . . 239 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 I/O Buffer AC and DC Characteristics . . . . . . . . . . . . . . . . 239 IBIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 IDCODE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 205, 277, 300 IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 25, 189, 277 IEEE 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 25, 189, 277 IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100, 191 Ignore Numeric Exception . . . . . . . . . . . . . . . . . . . . . . . . . 100 INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 224 INIT, State of Processor After . . . . . . . . . . . . . . . . . . . . . . 170 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Initialization, Power-on Configuration and . . . . . . . . 167, 291 INIT-Initiated Transition from Protected Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Input Setup and Hold Timings for 60-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Input Setup and Hold Timings for 66-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139, 141, 143, 223 cycles . . . . . . . . . . . . . . . . . . . . . 79-84, 94, 98-99, 112, 116 . . . . . . . . . . . . . 132, 136, 138, 140, 142, 144-146, 148 . . . . . . . . . . . . . . . . . 150, 154, 183-187, 215, 223-226 Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . 136 Inquire Cycle Hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Inquire Cycle Hit To Modified Line . . . . . . . . . . . . . . . . . . . 98 Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Inquire Miss, AHOLD-Initiated . . . . . . . . . . . . . . . . . . . . . 142 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Instruction Prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instructions Supported by the AMD-K6 Processor. . . 49, 283 Instructions, TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Integer Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Internal Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 279 Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Interrupt . . . . . . . . . . . . . . . . . . . 102, 111, 156, 160-161, 164 . . . . . . . . . . . . . . . . . 170, 189-191, 194, 202, 221, 226 acknowledge cycles . . . . . . . . . . . . 80, 83, 85, 91, 106, 115 descriptor table register . . . . . . . . . . . . . . . . . . . . . . . 39-40 flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 111 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 redirection bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 service routine . . . . . . . . . . . . . . . . . . . . . 102, 106, 190, 193 system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . 80, 88, 91, 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104, 108, 152, 156 Interrupt Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Interrupt, Type of. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupts 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 exceptions and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 224 INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Invalidation Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
K
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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20695H/0--March 1998
L
L1 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Limit, Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Line Fills, Cache- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Locked Operation with BOFF# Intervention . . . . . . . . . . . 154 Locked Operation, Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Logic branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 external support of floating-point exceptions . . . . . . . . 189 symbol diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 285
P
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . 271, 319 Package Thermal Specifications . . . . . . . . . . . . . . . . 259, 313 Page Cache Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Page Directory Entry (PDE) . . . . . . . . . . . . . . . . . . 43-44, 174 Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . 43, 45, 174 Page Writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Parity. . . . . . . . . . . . . . . . . . . . . . 77, 83, 85, 93, 108, 126, 285 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83, 93, 108 check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83-84, 93 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84, 108, 142, 206 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Parity Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273, 321 PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 174, 180 PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . 231 Pin Description Diagram. . . . . . . . . . . . . . . . . . . . . . . 267, 315 Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 317 Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 124-125, 130 Pipeline Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pipeline, Six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Pipelined. . . . . . . . . . . . 11, 106, 125, 130-131, 148, 171, 182 Pipelined Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pipelined Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 81, 92 Pipelined Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pointer, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . 229, 303 Power Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 229, 303 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235, 307 Power-on Configuration and Initialization . . . . . . . . 167, 291 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12, 172 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 181 PWT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
M
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Machine Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 170 MCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37-38, 170 Memory or I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Memory Read and Write, Misaligned Single-Transfer . . . 128 Memory Read and Write, Single-Transfer . . . . . . . . . . . . . 126 Memory Reads and Writes. . . . . . . . . . . . . . . . . . . . . . . . . . 126 MESI. . . . . . . . . . . . . 5, 11, 136, 140, 172, 182, 185, 187, 277 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12, 172-173 states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Microarchitecture Overview, AMD-K6 Processor . . . . . . . . . 7 Microarchitecture, Enhanced RISC86 . . . . . . . . . . . . . . . . . . 8 Misaligned I/O Read and Write. . . . . . . . . . . . . . . . . . . . . . 135 Misaligned Single-Transfer Memory Read and Write. . . . 128 MMX exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 instruction compatibility, floating-point and . . . . . . . . . 191 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode, Tri-State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 204, 299 Model 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 275 Model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 275 Model-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 281 Multimedia Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . 191
R
Ranges, Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 305 Ratings, Absolute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 305 Read and Write, Basic I/O. . . . . . . . . . . . . . . . . . . . . . . . . . 134 Read and Write, Misaligned I/O . . . . . . . . . . . . . . . . . . . . . 135 Reads, Burst Reads and Pipelined Burst. . . . . . . . . . . . . . 130 Register boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 bypass (BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 data Types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . 28 debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 216 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 general-purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 281 SYSCALL/SYSRET Target Address (STAR) . . . . . . . . . 282 Registers . . . . . . . . . . . . . . . . . . . . . . 9, 21, 168, 191, 281, 291 descriptors and gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 device identification (DIR) . . . . . . . . . . . . . . . . . . . 210, 300 DR3-DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR5-DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 extended feature enable register (EFER). . . . . . . . . . . 282
N
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 224 No-connect Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 231 Non-Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Non-Pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127, 176
O
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 305 Operation, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273, 321 Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . 273, 321 Organization, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 171, 293 Output Delay Timings for 60-MHz Bus Operation . . . . . . . 248 Output Delay Timings for 66-MHz Bus Operation . . . . . . . 244 Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168, 291
326
Index
Preliminary Information
20695H/0--March 1998
AMD-K6(R) Processor Data Sheet
IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 memory management . . . . . . . . . . . . . . . . . . . . . . . . . 39, 283 MMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 TAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206, 300 TR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 283 Regulator, Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Replacement, Cache-Line . . . . . . . . . . . . . . . . . . . . . . 177, 184 Requirements, Pin Connection . . . . . . . . . . . . . . . . . . . . . . 231 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 168, 224 and Test Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 252 signals sampled during. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 state of processor after. . . . . . . . . . . . . . . . . . . . . . . 168, 291 Return Address Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision Identifier, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RSM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199, 202 RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
S
SAMPLE/PRELOAD instruction . . . . . . . . . . . . . . . . . . . . . 212 Scheduler, Centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Scheduler/Instruction Control Unit . . . . . . . . . . . . . . . . . . . . 9 SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Sector, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . .24, 45-47 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment, Task State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Shift-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 287 Signal Switching Characteristics. . . . . . . . . . . . . . . . . 241, 311 Signal Timing, RESET and Test . . . . . . . . . . . . . . . . . . . . . 252 Signals A[20:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237-238 A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 194 ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81, 237-238 ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, 224 AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APCHK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 227 BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87, 150 BRDY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 237 BREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CACHE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 175 CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 224 FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 191
FLUSH# . . . . . . . . . . . . . . . . . . . . . . 97, 167, 184, 204, 224 HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 237-238 HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100, 191 INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 224 INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 224 INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LOCK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 M/IO#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 NA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 224 PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PWT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 224 RSVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 193, 224 SMIACT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112, 193 STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113, 225 TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 287 VCC2H/L#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 W/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 237-238 WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Signals Sampled During RESET . . . . . . . . . . . . . . . . . . . . 167 Signals, Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168, 291 Signals, TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Single-Transfer Memory Read and Write . . . . . . . . . . . . . 126 SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 193, 224 SMIACT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112, 193 SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 297 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 default register values. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 halt restart slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 I/O trap DWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 I/O trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Snoop. . . . . . . . . . . . . . . . . . . . . . 112, 116, 132, 183, 185-186 Snooping, Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Snooping, Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Software Environment. . . . . . . . . . . . . . . . . . . . . . . . . . 21, 281 Special Bus Cycle. . . . . . . . . . . . . 88, 113, 158-161, 200, 225 Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Special Cycle . . . . . . . . . . . . . . . . . 95, 97, 113, 119, 132, 158 . . . . . . . . . . . . . . . . . . . . . . . . . . 160-161, 176, 224-225 Specifications, Package. . . . . . . . . . . . . . . . . . . . . . . . 271, 319 Specifications, Package Thermal . . . . . . . . . . . . . . . . 259, 313 Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Stack, Return Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 State Machine Diagram, Bus. . . . . . . . . . . . . . . . . . . . . . . . 123 State of Processor After INIT . . . . . . . . . . . . . . . . . . . 170, 291 State of Processor After RESET . . . . . . . . . . . . . . . . 168, 291 States, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 State-Save Area, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Index
327
Preliminary Information AMD-K6(R) Processor Data Sheet
20695H/0--March 1998
Stop Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . .161, 226-227 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . 223-226 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . .161, 225-226 STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113, 225 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 241 60-MHz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 66-MHz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings for 60-MHz bus . . . . . . . . 250 input setup and hold timings for 66-MHz bus . . . . . . . . 246 output delay timings for 60-MHz bus . . . . . . . . . . . . . . . 248 output delay timings for 66-MHz bus . . . . . . . . . . . . . . . 244 Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241, 311 valid delay, float, setup, and hold timings . . . . . . . . . . . 243 SYSCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282-283 SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282-283 SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 System Design, Airflow Management in a . . . . . . . . . . . . . 264 System Management Interrupt . . . . . . . . . . . . . . . . . . . . . . 111 System Management Interrupt Active . . . . . . . . . . . . . . . . 112 System Management Mode (SMM) . . . . . . . . . . . . . . . 193, 297
Test-Logic-Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235, 260-264, 307 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259, 313 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 layout and airflow consideration . . . . . . . . . . . . . . . . . . 262 measuring case temperature . . . . . . . . . . . . . . . . . . . . . 262 package specifications . . . . . . . . . . . . . . . . . . . . . . 259, 313 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TR12 . . . . . . . . . . . . . . . . . . . . 37-38, 170, 174-175, 180, 215 Transition from Protected Mode to Real Mode, INIT-Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . 171 Trap Dword, I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 204, 299 TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-38, 170, 224-225 TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41, 47-48, 197, 220
V
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 287 VCC2H/L#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Voltage . . . . . . . . . . . . . . . . 115, 122, 229, 233-234, 238, 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287, 303, 305-306 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262-263 Voltage Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
T
Table, Branch History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205, 299 TAP Controller States Capture-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Capture-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Shift-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Shift-IR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Update-DR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Update-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206, 300 Instruction Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . 206 TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Target Cache, Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Temperature . . . . . . . . . . . . . . . . 233, 259-260, 262, 305, 313 case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Test Access Port, Boundary-Scan. . . . . . . . . . . . . . . . . 205, 299 Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203, 299 Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Test Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Test Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Test Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Test Mode, Tri-State . . . . . . . . . . . . . . . . . . . . . . . . . . . 204, 299 Test Register 12 (TR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Test Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
W
W/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 237-238 WAE15M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 WAELIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 WCDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 178, 181 WHCR . . . . . . . . . . . . . . . . . . . . . . . 37, 39, 170, 179, 181, 283 Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 177-182 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 178 enable limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 178 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 logic mechanisms and conditions . . . . . . . . . . . . . . . . . . 180 Write Handling Control Register (WHCR) . . . . . . . . . 39, 283 Write to a Cacheable Page . . . . . . . . . . . . . . . . . . . . . . . . . 178 Write to a Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Writeback . . . . . . . . . . . . . 90, 92-93, 103, 109, 112, 116, 119 . . . . . . . . .132-133, 158, 171, 176, 182, 185, 187, 228 burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 cycles . . . . . . . . . . . . . . . . . . . . . 79, 81-82, 95, 98, 116, 132 . . . . . . . . . . . . . . . . . . . . . 140, 144, 146, 148, 150, 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174-175, 216, 226 Writeback Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Writeback or Writethrough . . . . . . . . . . . . . . . . . . . . . . . . 116 Writethrough vs. Writeback Coherency States. . . . . . . . . 187
328
Index


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