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ISL22326WMVEP
Dual Digitally Controlled Potentiometers (XDCPTM)
Data Sheet December 17, 2007 FN6623.0
Low Noise, Low Power, I2C(R) Bus, 128 Taps
The ISL22326WMVEP integrates two digitally controlled potentiometers (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up, the device recalls the contents of the two DCP's IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments and signal processing.
Features
* Specifications per DSCC VID V62/08604-01XE * Full Mil-Temp Electrical Performance from -55C to +125C * Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site * Full Homogeneous Lot Processing in Wafer Fab * No Combination of Wafer Fabrication Lots in Assembly * Full Traceability Through Assembly and Test by Date/Trace Code Assignment * Enhanced Process Change Notification * Enhanced Obsolescence Management * Eliminates Need for Up-Screening a COTS Component * Two Potentiometers in One Package * 128 Resistor Taps * I2C Serial Interface - Three Address Pins, Up To Eight Devices/Bus * Non-volatile Storage of Wiper Position * Wiper Resistance: 70 Typical @ 3.3V * Shutdown Mode * Shutdown Current 5A Max
Device Information
The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Supply Center in Columbus (DSCC). "Hot-links" to the applicable VID and other supporting application information are provided on our website.
Pinout
ISL22326WMVEP (14 LD TSSOP) TOP VIEW
VCC SHDN RH0 RL0 RW0 A2 SCL 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A1 A0 RH1 RL1 RW1 GND SDA
* Power Supply: 2.7V to 5.5V * 10k Total Resistance * High Reliability - Endurance: 1,000,000 Data Changes Per Bit Per Register - Register Data Retention: - 10 years @ T +125C - 15 years @ T +90C - 50 years @ T +55C * 14 Ld TSSOP
Ordering Information
VENDOR PART NUMBER (Notes 1, 2) VENDOR ITEM DRAWING PART MARKING ISL22326WMVEP NOTES: 1. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Devices must be procured to the VENDOR PART NUMBER. V62/08604-01XE 22326 WMVEP RESISTANCE OPTION (k) 10 TEMP. RANGE (C) -55 to +125 PACKAGE PKG. DWG. #
14 Ld TSSOP M14.173
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22326WMVEP Block Diagram
VCC
SCL SDA A0 A1 A2 I2C INTERFACE POWER-UP INTERFACE, CONTROL AND STATUS LOGIC WR1
RH1 RW1 RL1
RH0 NONVOLATILE REGISTERS WR0 RW0 RL0
SHDN
GND
Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL VCC SHDN RH0 RL0 RW0 A2 SCL SDA GND RW1 RL1 RH1 A0 A1 Power supply pin Shutdown active low input "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 Device address input for the I2C interface Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device ground pin "Wiper" terminal of DCP1 "Low" terminal of DCP1 "High" terminal of DCP1 Device address input for the I2C interface Device address input for the I2C interface DESCRIPTION
2
FN6623.0 December 17, 2007
ISL22326WMVEP Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
D E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN6623.0 December 17, 2007

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