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DDR12 Series | Tracking Dual Output DC-DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25 A @ 2.5 V for Vddq supply and 8 A @ 1.25 V for Vtt termination Tracking dual output voltages (1.25 V @ 8 A, 2.5 V @ 25 A) Output voltage remote sense Sink capability for logic terminations Power good output signal Overvoltage protection Overcurrent protection Remote ON/OFF Available RoHS compliant The dual output DDR12-25D08-AJ is specifically designed to meet the power needs of double data rate memory DIMMS and associated memory control logic. The Vtt output tracks the Vddq output, while the Vtt output can sink current as required by logic terminations.This converter offers Remote sense on Vddq and remote ON/OFF facilities are included as standard, and the converter is protected against overcurrent and over-voltage conditions. typical efficiencies greater than 84% when operated at 50% load or greater. This model features a wide input range as well as trimmable output voltages. [ 2 YEAR WARRANTY ] 1 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | SXA10 Series | 15W DC/DC Tracking Dual Output DC-DC Converters Stresses in excess of the maximum ratings can cause permanent damage to the device. Operation of the device is not implied at these or any other conditions in excess of those given in the specification. Exposure to absolute maximum ratings can adversely affect device reliability. Absolute Maximum Ratings Characteristic Input voltage - continuous Input voltage - nominal Operating temperature Symbol Vin (cont) Vin (nom) Top Tstorage Iddq (max) Itt (max) 0 Min -0.3 12 80 C Refer to derating guidelines and Note 1 Typ Max 13.2 Units Vdc Notes and Conditions Vin(+) - Vin(-) Storage temperature Output current -40 125 25 8 C A A All specifications are typical at Vin(nom), Vddq = 2.5 V, Vtt = 1.25 V and full load. Tests were performed at 25 C unless otherwise stated. Input Characteristics Characteristic Input voltage - operating Input current - min. load Input current - Quiescent Symbol Vin (oper) lin lin (off) Min 10.8 Typ 12 400 20 Max 13.2 Units Vdc mAdc mAdc Vin (min) - Vin (max), enabled Converter disabled Notes and Conditions Turn On/Off Characteristic Input voltage - turn on Input voltage - turn off Turn on delay - enabled, then power applied Symbol Vin (on) Vin (off) Tdelay (power) Min 10 9.7 Typ 10.2 9.9 5 Max 10.4 10.1 Units Vdc Vdc ms With the enable signal asserted, this is the time from when the input voltage reaches the minimum specified operating voltage until the POWER GOOD is asserted high Vin = Vin (nom), then enabled. This is the time taken until the POWER GOOD is asserted high Output voltage in full regulation to POWER GOOD asserted high Notes and Conditions Turn on delay - power applied, then enabled Tdelay (enable) 5 ms Output to POWER GOOD delay Rise time Tdelay Trise 3 2 ms ms 2 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters Signal Electrical Interface Characteristic - Signal Name Symbol At remote/control ON/OFF pin Open collector or equivalent compatible High level input voltage Vih 2.0 V Min Typ Max Units Notes and Conditions See Notes 2 and 3 See Application Note 133 for Remote ON/OFF details Converter guaranteed on when OUTEN pin is greater than Vih (max) Converter guaranteed off when OUTEN pin is less than Vil (max) ViI = 0.0 V Low level input voltage ViI 0.80 V Low level input current Iil (max) 1 mA Reliability and Service Life Characteristic Mean time between failure Symbol MTBF Min TBD Typ Max Units Hours Notes and Conditions Telcordia SR-332 3 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | SXA10 Series | 15W DC/DC Tracking Dual Output DC-DC Converters Other Specifications Characteristic Switching frequency Weight Symbol Fsw Min Typ 300 34 Max Units kHz g Notes and Conditions Fixed frequency Referenced ETSI standards: ETS 300 019: Environmental conditions and environmental tests for telecommunications equipment ETS 300 019: Part 1-3 (1997) Classification of environmental conditions stationary use at weather protected locations ETS 300 019: Part 2-3 (1997) Specification of environmental tests stationary use at weather protected locations EMC Electromagnetic Compatibility Phenomenon Immunity: ESD Enclosure EN61000-4-2 6 kV contact 8 kV air As per ETS 300 386-1 table 5 Port Standard Test level Criteria Notes and conditions Performance criteria: NP: Normal Performance: EUT shall withstand applied test and operate within relevant limits as specified without damage. RP: Reduced Performance: EUT shall withstand applied test. Reduced performance is permitted within specified limits, resumption to normal performance shall occur at the cessation of the test. LFS: Loss of Function (self recovery): EUT shall withstand applied test without damage, temporary loss of function permitted during test. Unit will self recover to normal performance after test. Referenced ETSI standards: ETS 300 386-1 table 5 (1997): Public telecommunication network equipment, EMC requirements ETS 300 132-2 (1996): Power supply interface at the input to telecommunication equipment: Part 2 operated by direct current (dc) ETR 283 (1997): Transient voltages at interface A on telecommunication direct current (dc) power distributions Material Ratings Characteristic - Signal Name Notes and Conditions Flammability rating Material type UL94V-0 FR4 PCB Model Numbers Model Number DDR12-25D08-AJ Input Voltage 10.8-13.2 Vdc Output Voltage 2.32-2.75 Vdc 1.16-1.375 Vdc Output Current (Max.) 25 A 8A Typical Efficiency 84% Load Regulation 1.0% See Tracking Spec. 4 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters Input Characteristics Characteristic Input current - operating Reflected ripple current Symbol Iin Iin (ripple) Min Typ 7.2 35 50 420 Max Units Adc mA rms measured with external filter. mA pk-pk See Application Note 133 for details F Notes and Conditions Input capacitance - internal filter Input capacitance - external filter Cinput Cbypass 10 F Use large value ceramic Electrical Charact. - Vddq O/P Characteristic Nominal set-point voltage Output voltage range Symbol Vddq (nom) Vddq Min Typ 2.316 2.316 2.750 Max Units Vdc Vdc Notes and Conditions With no external trim resistor For details on trimming the output voltage see Application Note 133 Using 1% trim resistors measured at minimum load Vary load with line held constant (Voltage typically drops with load) Vary line with load held constant Vary load on Vtt with load on Vddq held constant Temperature co-efficient Ripple and noise 0.2 50 mV/C mV pk-pk With recommended external load capacitance and 5 Hz to 20 MHz bandwidth % Peak deviation for 75% to 100% step load, di/dt = 0.04 A/s Settling time to within 1% of output setpoint voltage for 75% to 100% step load Recommended 3 x 560 F with total ESR of 5 m and additional high-quality ceramic capacitors. Consult factory for other capacitance Nominal output at turn-on Output set-point accuracy 1.5 2.5 % Load regulation +0/-1 +1/-2 % Line regulation Cross regulation 0.1 0.4 0.2 0.6 % Load transient response peak deviation Load transient response recovery 3 200 s External load capacitance Cext (Vddq) 1000 1680 3000 F Overshoot Undershoot Output current - continuous Output current - short circuit Iddq Isc-ddq 1.5 0 2.0 150 25 % mVdc Adc A rms Latching short circuit protection power or enable needs to be cycled 5 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | SXA10 Series | 15W DC/DC Tracking Dual Output DC-DC Converters Electrical Charact. - Vtt O/P Characteristic Tracking accuracy Symbol Min Typ 12 Max 25 Units mV Notes and Conditions Measured at converter pins (=Vddq/2 - Vtt) Ripple and noise 30 mV pk-pk With recommended external load capacitance and 5 Hz to 20 MHz bandwidth % Peak deviation for 75% to 100% step load, di/dt = 8 A/s Settling time to within 1% of output setpoint voltage for 75% to 100% step load Recommended 3 x 560 F with total ESR of 5 m and additional high-quality ceramic capacitors. Consult factory for other capacitance Load transient response peak deviation Load transient response recovery 3 200 s External load capacitance Cext (Vtt) 1000 1680 3000 F Output current - continuous Output current - short circuit Itt Isc-tt 0 0 8 Adc A rms Latching short circuit protection power or enable needs to be cycled Protection and Control Features Characteristic Overcurrent limit inception Symbol Iddq Itt Min Typ 36 14 Max Units Adc Adc Notes and Conditions Efficiency Characteristic Efficiency Symbol Min Typ 84 Max Units % Notes and Conditions Full load 6 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters OUTPUT CURRENT (A) 25 92 EFFICIENCY (%) 90 88 86 84 82 20 30 40 50 60 70 80 Low Line Nom Line High Line 20 15 10 5 AMBIENT TEMPERATURE (C) 0 m/s (0 LFM) 0.5 m/s (100 LFM) 1 m/s (200 LFM) 1.5 m/s (300 LFM) 2 m/s (400 LFM) 0 20 40 60 80 100 FULL LOAD CURRENT (%) Figure 1: Thermal Derating Curve Figure 2: Efficiency vs Load and Line Figure 3: Typical Ripple & Noise Channel 1: Vddq Output Ripple, Channel 2: Vtt Output Ripple Figure 4: Typical Power-up Channel 1: Vddq Output Channel 2: Vtt Output Channel 3: Power Good Signal Figure 5: Transient Response 75-100% Vtt Source, Rising Edge (Channel 2: Vtt Output Voltage Deviation, Channel 4: Current load step at 1 A/div) Figure 6: Transient Response 75-100% Vtt Source, Falling Edge (Channel 2: Vtt Output Voltage Deviation, Channel 4: Current load step at 1 A/div) 7 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | SXA10 Series | 15W DC/DC Tracking Dual Output DC-DC Converters Figure 7: Transient Response 75-100% Vddq Rising Edge, (Channel 1: Vddq Output Voltage Deviation, Channel 4: Current load step at 2 A/div) Figure 8: Transient Response 75-100% Vddq Falling Edge, (Channel 1: Vddq Output Voltage Deviation, Channel 4: Current load step at 2 A/div) Figure 9: Input Ripple Voltage measurement, Vin = 12 V, Vddq = 25 A, Vtt = 8 A (Channel 1: Vin Ripple Voltage) 8 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters 0.500 (12.67) Ref 0.260 (6.71) 3.000 (76.20) 0.062 (1.57) PCB 0.025 (0.64) TYP. 0.150 (3.81) Typ 1.200 (30.48) 0.170 (4.39) 0.050 (1.30) TYP. PIN 1 PIN 7 PIN 8 0.025 (0.64) Typ 0.100 (2.54) Typ PIN 22 0.250 (6.35) 1.100 (27.94) Dimensions in Inches (mm) Tolerances (unless otherwise specified) 2 Places 0.02 (0.51) 3 Places 0.010 (0.25) Pin Connections Pin No. J1-1 J1-2 J1-3 J1-4 J1-5 J1-6 J1-7 J2-1 J2-2 J2-3 J2-4 Function Power Good Output Enable Ground Ground 12V Input 12V Input 12V Input Vtt Ref. Vtt Vtt Ground Pin No. J2-5 J2-6 J2-7 J2-8 J2-9 J2-10 J2-11 J2-12 J2-13 J2-14 J2-15 Function Ground Ground Ground Ground Vddq Sense Vddq Sense + Vddq Vddq Vddq Vddq Vddq Figure 10: Mechanical Drawing and Pinout Table 9 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | SXA10 Series | 15W DC/DC Tracking Dual Output DC-DC Converters Note 1 For maximum reliability temperature at the Thermal Reference Point, shown in Figure 11, should not exceed 100 C. Thermal Reference Point Note 2 The control pin is referenced to Vin- Note 3 The DDR12 is supplied as standard with active High logic. Control input pulled low: Unit Disabled Control input left open: Unit Enabled Note 4 Thermal reference set up: Unit mounted on an edge card test board 215 mm x 115 mm. Test board mounted vertically. For test details and recommended set-up see Application Note 133. Figure 11: Thermal Reference Points CAUTION: Hazardous internal voltages and high temperatures. Ensure that unit is accessible only to trained personnel. The user must provide the recommended fusing in order to comply with safety approvals. 10 10 File Name: lf_ddr12.pdf Rev: 29 Nov 2005 DDR12 Series | Tracking Dual Output DC-DC Converters NORTH AMERICA e-mail: sales.us@artesyn.com 800 769 7274 + 508 628 5600 EUROPEAN LOCATIONS e-mail: sales.europe@artesyn.com IRELAND + 353 24 93130 AUSTRIA + 43 1 80150 FAR EAST LOCATIONS e-mail: sales.asia@artesyn.com HONG KONG + 852 2699 2868 Longform Datasheet (c) Artesyn Technologies(R) 2005 The information and specifications contained in this datasheet are believed to be correct at time of publication. However, Artesyn Technologies accepts no responsibility for consequences arising from printing errors or inaccuracies. Specifications are subject to change without notice. No rights under any patent accompany the sale of any such product(s) or information contained herein. 11 www.artesyn.com File Name: lf_ddr12.pdf Rev: 29 Nov 2005 |
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