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| www..com CO FI N EN D AL TI Eureka Microelectronics, Inc. www..com EK7309 256-Outputs Gate Driver CO FI N EN D AL TI 6F, NO.12, INNOVATION 1 ST. RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. http://www.eureka.com.tw EUREKA Contents EK7309 Page 1.GENERALDESCRIPTION........................................................................1 2.FEATURES........................................................................................... 1 www..com 3.BLOCK DIAGRAM.................................................................................. 1 4.PIN CONFIGURATION............................................................................ 2 5.PIN FUNCTION DESCRIPTIONS...............................................................3 6.FUNCTION OPERATIONS ........................................................................4 6.1 Power supply's 6.2 Shift direction 6.3 OE function 6.4 XDON function 7.TIMING DIAGRAM.............................................................................. ... 5 8.ABSOLUTE MAXIMUM RATINGS....................................... ............ 8.1 Absolute maximum ratings 8.2 Recommended operating conditions 9. DC ELECTRICAL CHARACTERISTICS............... 9.1 9.2 9.3 9.4 Supply current Input pin I/O pin Output pin ...............................................10 ..................................... 8 ...... 7 10. AC ELECTRICAL CHARACTERISTICS... CO FI N EN D AL TI EUREKA TFT Gate Driver (256 Outputs) 1. GENERAL DESCRIPTION EK7309 is a TFT LCD gate driver with 256 outputs for XGA/SXGA display systems. The logic and control portion is implemented in standard CMOS circuits while the output drivers use high voltage CMOS design. The low voltage part includes a 256stage bidirectional shift register with right and left shift I/O for cascading. The output of the shift register is then level translated to drive the high voltage output www..com buffer. There are four supply voltages for EK7309. VDD/VSS are the supply voltages for logic interfaces. Typically VDD is at 3.3V while VSS is 0V. VGG and VEE are the supply voltages for the output driver. VEE is the most negative supply voltage for the internal substrate of EK7309. EK7309 allows three output enable controls (OE13) and one global enable signal (XON). 2. FEATURES * * * * * * * EK7309 256 gate drive outputs Bidirectional shift control and cascadable Output enable and global on control Maximum shift clock frequency up to 100KHz 3.3V CMOS logic I/O High voltage output drive Operating supply range Logic (VDD-VSS: 3.3V) Output Drive (VGG -VEE: 40V) * TCP package 3. BLOCK DIAGRAM X1 X256 VGG High voltage output and level shifters VEE VDD VSS Low voltage logic and IO XON DIO1 CO FI N EN D AL TI OE3 OE2 OE1 DIO2 SCLK RL May 2003 -01- Preliminary Rev 0.2 EUREKA 4. PIN CONFIGURATION EK7309 VEE VEE www..com X1 X2 X3 X4 VSS DIO1 XON RL SCLK OE1 OE2 OE3 DIO2 VDD VGG EK7309 X253 X254 X255 X256 CO FI N EN D AL TI IC top view. This diagram shows EK7309's pin configuration only. It does not necessarily correspond to the pad layout on the chip. Figure-1 May 2003 -02- Preliminary Rev 0.2 EUREKA 5. PIN FUNCTION DESCRIPTION Name SCLK RL Pin I I Description EK7309 Shift clock. This is a 3.3V CMOS level input for shift register clock. The rising edge of SCLK is used. Right/Left shift control. RL=1 is shift right (X1 -> X256), RL=0 is shift left (X256 -> X1). DIO1 DIO2 Output Input DIO1 DIO2 www..com OE1, I/O RL = "H" RL = "H" Input Output OE2, OE3 XON X [1-256] VDD VSS VGG VEE I Output enable control. The output is forced low when OE is high. OE1 controls output 1,4,...,253,256. The control is asynchronous to SCLK. OE2 controls output 2,5,...,251,254. The control is asynchronous to SCLK. OE3 controls output 3,6,...,252,255. The control is asynchronous to SCLK. Global on control. When XON=0, all outputs are forced high. XON is asychronous to SCLK. Output drive. These are the gate drive outputs.The high level is VGG and the low level is VEE. Positive supply voltage for LV logic . This is typically 3.3V. Negative supply voltage for LV logic. This is typically 0V. Positive supply voltage for the output driver. This is typically the most positive supply voltage to EK7309. Negative supply voltage for the output drive and the substrate. This is the most negative supply voltage to EK7309. I O P P P P LCD drive output VGG LV logic VDD VSS VEE CO Figure-2 FI N EN D AL TI May 2003 -03- Preliminary Rev 0.2 EUREKA 6. FUNCTIONAL DESCRIPTION EK7309 6.1 When RL is "HIGH" and a start pulse inputs the DIO1 pin, this pulse is shifted right by the shift control register at the rising edge of SCLK. While the output of the shift control register is "HIGH", the Xn [n=1, 2, 3,..., 256] is pulled to VGG. If the output of the shift control register is "LOW", Xn [n=1, 2, 3,..., 256] is pushed to VEE; DIO2 is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at the falling edge of the 257th clock of SCLK. Please refer to operating waveform (1). 6.2 When RL is "LOW" and a start pulse inputs the DIO2 pin, this pulse is shifted left by the shift control register at the rising edge of SCLK. While the output of the shift control register is "HIGH", the Xn [n=256, 255, 254,..., 1] is pulled to VGG. If the output of the shift control register is "LOW", Xn [n=256, 255, 254,..., 1] is www..com pushed to VEE; DIO1 is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at the falling edge of the 257th clock of SCLK. Please refer to operating waveform (2). 6.3 OE1, OE2, and OE3 can disable Xn [n=1, 2, 3,..., 256]. They are asynchronous to SCLK. Xn [n=1, 4, 7,..., 253, 256] is pushed to VEE when OE1 is "HIGH". Xn [n=2, 5, 8,..., 251, 254] is pushed to VEE when OE2 is "HIGH". Xn [n=3, 6, 9,..., 252, 255] is pushed to VEE when OE3 is "HIGH". Please refer to operating waveform (1) and (2). 6.4 The global on control XON can enable Xn [n=1, 2, 3,..., 256]. It is asynchronous to SCLK. Whenever XON is "LOW", all outputs of EK7309 are pulled to VGG at the same time. Please refer to operating waveform (3). CO FI N EN D AL TI May 2003 -04- Preliminary Rev 0.2 EUREKA 7. TIMING DIAGRAM RL=1, shift right 1 SCLK DIO1 OE1 OE2 2 3 4 5 254 255 256 257 EK7309 www..com OE3 X1 X2 X3 X256 DIO2 Figure-3 Operating Waveforms (1) RL=0, shift left 1 SCLK DIO2 OE1 OE2 OE3 X256 X255 X254 2 3 4 5 254 255 256 257 CO FI N EN D AL TI X1 DIO1 Figure-4 Operating Waveforms (2) May 2003 -05- Preliminary Rev 0.2 EUREKA XON=0, RL=1 1 SCLK DIO1 OE1 OE2 OE3 XON X1 X2 X3 2 3 4 5 254 255 256 257 EK7309 www..com X256 DIO2 Figure-5 Operating Waveforms (3) CO FI N EN D AL TI May 2003 -06- Preliminary Rev 0.2 EUREKA 8. ABSOLUTE MAXIMUM RATING 8.1 ABSOLUTE MAZIMUM RATING EK7309 VLL = 0V Symbol VDD VGG VEE VIN www..com a Parameter Logic Supply Voltage Positive Supply Voltage Most Negative Supply Voltage Logic Input Voltage Operation Ambient Temperature Storage Temperature Range Rating -0.3 ~ +7.0 -0.3 ~ +45 VGG-45 ~ +0.3 -0.3 ~ VDD +0.3 -30 ~ +85 -55 ~ +120 Unit V V V V C C T Tstg 8.2 RECOMMENDED OPERATING RANGE VLL = 0V Symbol VDD VGG VEE Ta Parameter Logic Supply Voltage Positive Supply Voltage Most Negative Supply Voltage Operation Ambient Temperature Min 3.0 10 -25 -20 Typ 3.3 Max 3.6 VEE + 40 -5 +70 Unit V V V C Note: Power ON/OFF sequence is as below: 1. Power ON sequence: VSS VDD VEE VGG. 2. Power OFF sequence: VGG VEE VDD VSS. Voltage VDD VSS Time VEE VGG Figure-6 CO FI N EN D AL TI May 2003 -07- Preliminary Rev 0.2 EUREKA 9. DC ELECTRICAL CHARACTERISTICS 9.1 Supply current EK7309 Ta = 25 Symbol IVDD1 Operating current IVGG1 www..com , VSS = 0V Unit A Parameter Condition fSCLK = 15.7KHz fSL = 60Hz VDD = 3.3V VEE = -15V VGG = 15V no loading VDD = 3.3V Min Typ Max 800 300 600 100 A A A IVDD Standby current IVGG2 VEE = -15V VGG = 15V 9.2 Input pin: RL, SCLK, OE1, OE2, OE3, XON Ta = 25 Symbol VIH1 VIL1 ILI1 Parameter Input Voltage, HIGH Input Voltage, LOW Input Leakage Current XON except Condition Min 0.8xVDD 0 , VSS = 0V Unit V V A Typ Max VDD 0.2xVDD -2 +2 9.3 I/O pin: DIO1, DIO2 Ta = 25 Symbol VIH2 VIL2 VOH VOL Parameter Input Voltage, HIGH Input Voltage, LOW Output Voltage, HIGH Output Voltage, LOW -100A 100A Condition Min 0.8xVDD 0 VDD-0.4 , VSS = 0V Unit V V V V Typ Max VDD 0.2xVDD CO FI N EN D AL TI 0.4 May 2003 -08- Preliminary Rev 0.2 EUREKA 9.4 Output pin: X1 ~ X256 EK7309 Ta = 25C, VSS = 0V Symbol ILO1 Parameter Output Leakage Current Condition Min -50 Typ Max 50 Unit RON-VGG VGG = 15V VEE = -15V VOM = VGG -0.5V VOM is X1-X256 Output ON Resistance VGG =15V VEE = -10V VOM =VEE+0.5V VOM is X1-X256 600 1000 ohm www..com RON-VGG 600 1000 ohm CO FI N EN D AL TI May 2003 -09- Preliminary Rev 0.2 EUREKA 10. AC CHARACTERISTICS Symbol tSCLK tWH tWL tr tf www..com tsu tn tpd1 tpd2 tpd3 Parameter Shift Clock Period Shift Clock Pulse Width, HIGH Shift Clock Pulse Width, LOW Shift Clock Rise Time Shift Clock Fall Time DIO1/DIO2 Input Setup Time DIO1/DIO2 Input Hold Time DIO1/DIO2 Output Delay Time Xn Output Delay Time Xn Output Delay Time (XON only) CL = 50pF CL = 300pF CL = 300pF 50 350 Condition Min 10 4 4 Typ EK7309 Ta = 25C, VSS = 0V Max Unit s s s 100 100 ns ns ns ns 300 800 1000 ns ns ns CO FI N EN D AL TI May 2003 -10- Preliminary Rev 0.2 EUREKA AC Characteristics Waveforms EK7309 tWL tWH 80% 80% tSCLK 90% 50% 20% 10% 90% 50% 10% SCLK 20% 20% tr tsu www..com tf th 80% 80% DIO1/DIO2 Input tpd1 DIO1/DIO2 Output 50% tpd1 50% tpd2 Xn 50% 80% OEm 20% tpd2 Xn tpd2 50% 50% XON 20% 80% tpd3 50% CO tpd3 50% FI N EN D AL TI Xn Figure-7 May 2003 -11- Preliminary Rev 0.2 EUREKA DEFINITIONS EK7309 Data Sheet status Objective specification This data sheet contains target or goal specification for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specification. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS www..com These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Eureka for any damages resulting from such improper use or sale. CO FI N EN D AL TI May 2003 -12- Preliminary Rev 0.2 |
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