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DOC Title EK7304 DATA SHEET
DOC NO TDS7304-01 REV 1.2 1/1 Page
/ Revision History REV.
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REV Date
Eff. Date
REV. Page 2 3 1112
// Revise item / Content 1. Fig.2. Pin Diagram 2. Pin List 3. Pin description 1. TOPR=-20 to +75 1. OE function 2. XDON function
1.0
1.1
2001/08/29 2001/08/29 2001/10/22 2001/10/22
1.2
2002/07/09 2002/07/10
6 7

Eureka
Microelectronics, Inc.
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EK7304
256 Output TFT Gate Driver IC
6F, NO.12, INNOVATION 1 . RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. TEL886-3-5799255 FAX886-3-5799253 http://www.eureka.com.tw
ST

EUREKA
256- Output TFT Gate Driver IC
DESCRIPTION The EK7304 is a 256-output TFT gate driver IC suitable for driving large/medium scale of TFT LCD panels. Through the use of TCP, it substantially
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EK7304
decreases the size of the frame section of LCD module.
FEATURES Output channels: Driver operating frequency: LCD drive voltage: Driver output levels:
256 outputs max. 1200kHz max. VEE+43V two ("L" level
is changeable) Incorporates bi-directional shift register. Supports multi chip operation via output pins. Pulse width modulation function.
BLOCK DIAGRAM X1 X256
VGG VOFF VEE High voltage output and level shifters
VDD VSS XDON DIO1 Low voltage logic and IO
OE3 OE2 OE1 DIO2
FX
RL
Fig. 1. Block diagram
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PINNING INFORMATION Table 1. Pin List
Terminal Name 1 Dummy 2 X196 3 X195 4 X194 5 X193 6 X192 7 X191 8 X190 www..com 9 X189 10 X188 11 X187 12 X186 13 X185 14 X184 15 X183 16 X182 17 X181 18 X180 19 X179 20 X178 21 X177 22 X176 23 X175 24 X174 25 X173 26 X172 27 X171 28 X170 29 X169 30 X168 31 X167 32 X166 33 X165 34 X164 35 X163 36 X162 37 X161 38 X160 39 X159 40 X158 41 X157 42 X156 43 X155 Terminal Terminal 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Terminal Name X154 X153 X152 X151 X150 X149 X148 X147 X146 X145 X144 X143 X142 X141 X140 X139 X138 X137 X136 X135 X134 X133 X132 X131 X130 X129 X128 X127 X126 X125 X124 X123 X122 X121 X120 X119 X118 X117 X116 X115 X114 X113 X112 X111 Terminal 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Terminal Name X111 X110 X109 X108 X107 X106 X105 X104 X103 X102 X101 X100 X099 X098 X097 X096 X095 X094 X093 X092 X091 X090 X089 X088 X087 X086 X085 X084 X083 X082 X081 X080 X079 X078 X077 X076 X075 X074 X073 X072 X071 X070 X069 Terminal 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Terminal Name X068 X067 X066 X065 X064 X063 X062 X061 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy X060 X059 X058 X057 X056 X055 X054 X053 X052 X051 X050 X049 X048 X047 X046 X045 X044 X043 X042 Terminal 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 Terminal Name X041 X040 X039 X038 X037 X036 X035 X034 X033 X032 X031 X030 X029 X028 X027 X026 X025 X024 X023 X022 X021 X020 X019 X018 X017 X016 X015 X014 X013 X012 X011 X009 X008 X007 X006 X005 X004 X003 X002 X001 Dummy VOFF VEE Terminal 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258
EK7304
Terminal Name VEE VSS DIO1 RL FX OE1 OE2 OE3 DIO2 XDON VDD VGG Dummy X256 X255 X254 X253 X252 X251 X250 X249 X248 X247 X246 X245 X244 X243 X242 X241 X240 X239 X238 X237 X236 X235 X234 X233 X232 X231 X230 X229 X228 X227 Terminal 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 Terminal Name X226 X225 X224 X223 X222 X221 X220 X219 X218 X217 X216 X215 X214 X213 X212 X211 X210 X209 X208 X207 X206 X205 X204 X203 X202 X201 X200 X199 X198 X197 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
Notes: 1. With the chip name EM7301 orientated normal the pin 1 is in the upper right corner. 2. Counting is anticlockwise.
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Table 2 Pin description PIN NO SYMBOL I/O 212 to 154 X001-X256 O 137 to 2 288 to 229 214 VOFF 215, 216 VEE 217 VSS 219 I www..com RL 218 224 225 220 221 222 223 226 227 DIO1 DIO2 XDON FX OE1 OE2 OE3 VDD VGG Function TFT gate driver output
EK7304
DESCRIPTION Under the control of the shift register data, OE1 or OE2 or OE3, and DIO1 or DIO2, the driver outputs are VGG or VOFF and change their value at the rising edge of FX Supply Power supply for TFT driver output low level Supply Negative power supply for Level shifters. Chip ground Supply Logic ground, Reference of the voltages Shift direction RL = "H" : X1 X256 (Shift left) selection signal RL = "L" : X256 X1 (Shift right) I/O Start pulse input DIO1 DIO2 and output RL = "H" Input Output RL = "L" Output Input I Negative active When XDON = "L" then the driver outputs are at the VGG input pin level independant of any other input or register value. I Shift register The start pulse is sampled at the rising edge of FX, clock input The carry pulse changes at the falling edge of FX. I Negative active When OEN = "H" then the associated outputs are set to VOFF input pin independent of the register data. This function is not synchronized with FX. Supply Logic positive power Supply High voltage power and TFT driver output high level
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FUNCTIONAL DESCRIPTION Power supply's The TFT voltage is relative to the logic ground, it can be a negative voltage value.
EK7304
VGG
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VDD VSS VOFF VEE
Fig. 2. Relative position of the different supply voltages Shift direction The input signals OE1,2,3 and the shift data control the value of the outputs (X1 till X256). Their value can be either VGG or VOFF. The signal LR controls the shift direction of the shift register. The shift register takes its value from one of the input/output pins DIO at the rising edge of the clock FX and shifts the value to the other input/output pin DIO where it is presented at the falling edge of FX. Table 2. RL shift direction relation RL Start pulse taken from: RL="H" DIO1 RL="L" DIO2 Data shift direction X1 X256 X256 X1 Output pulse given at: DIO2 DIO1
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EK7304
OE function When the OE1, OE2, OE3 inputs are "H" than the outputs are driven to VOFF regardless of the contents of the shift register. Each of the three inputs drives it own set of outputs. This function is not synchronized with FX. The signal XDON can override this function. In the Table below the relation between each OE1,2,3 and their related outputs is given. Table 3. OE1,2,3 to Output relation Non-signal input Symbol www..com OE1 X(3i+1) i =0~85 OE2 X(3i+2) i =0~84 OE3 X(3i+3) i =0~84 LCD driver outputs X1,X4,X7,X10, X247,X250,X253,X256 X248,X251,X254 X2,X5,X8,X11, X3,X6,X9,X12, X249,X252,X255
1
2
3
4
5
254
255
256
257
FX
DIO 1
O E1
O E2
O E3
X1
X2
X3
X4
X256
DIO 2
Fig. 3. OEn Functionality
RL= "H"
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1 2 3 4 5 254 255 256 FX
EK7304
257
DIO2
OE1
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OE2
OE3
X256
X255
X254
X253
X1
DIO1
Fig. 4. OEn Functionality
RL= "L"
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with FX.
EK7304
XDON function When XDON input is "L" then all outputs are driven to the VGG level. This function is overriding all other inputs. With this input all TFT gates are set to high to enable a display off function. This function is not synchronized
1
2
3
4
5
254
255
256
257
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DIO1
OE1
OE2
OE3
XDON
X1
X2
X3
X4
X256
DIO2
Fig. 5. XDON Functionality RL= "H"
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CIRCUIT DIAGRAMS Input/Output Circuit VGG VDD
EK7304
I
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To Internal Circuit
VEE
VSS
(Applicable pins) XDON, RL, FX OE1, OE2, OE3 Fig. 6. Input Circuit
To Internal Circuit
VGG
VDD Output Signal
I/O
Control Signal VEE VSS Fig. 7. Input/Output Circuit(1) (Applicable pins) DIO1, DIO2
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VGG VGG Control Signal 1
EK7304
O
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Control Signal 3
VEE (Applicable pins) X1 to X 256
VEE
VOFF
VEE
VEE
Fig. 8. TFT driver circuit
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EK7304
PRECAUTIONS Precaution when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The detail is as follows. When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD
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drive power.
ABSOLUTE MAXIMUM RATINGS Table 4. Absolute maximum Ratings In accordance with the Absolute Maximum Ratings System (IEC 134); See notes 1 and 2 Parameter Symbol Applicable Pins Ratings Unit NOTE 1, 2 Supply voltage(1) VDD VDD VSS -0.3 to +7.0 V Supply voltage(2) VGG VGG -0.3 to +45.0 V VEE VEE VGG -45 to VGG+0.3 V VOFF VOFF VEE -0.3 to VGG+0.3 V VDD VDD VEE -0.3 to VGG+0.3 V VSS VEE -0.3 to VGG+0.3 V VSS Input voltage EO1, EO2, EO3, DIO1 VSS -0.3 to VDD+0.3 VI V DIO2, RL, FX, XDON VEE -0.3 to VGG+0.3 Storage temperature Tstg -45 to +125 Notes: 1. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device 2. Parameters are valid over operating temperature range unless otherwise specified. RECOMMENDED OPERATING CONDITIONS Table 5. Recommended operating conditions Parameter Symbol Applicable pins Min. Typ. Supply voltage(1) VDD VDD +2.5 Supply voltage(2) VGG VGG +10.0 Supply voltage(2) VEE VEE -25 Operating temperature TOPR -20 Notes: 1. All voltages are with respect to VSS unless otherwise noted (0 V).
Max. +5.5 +42.0 -5 +75
Unit V V V
NOTE 1, 2
2. Ensure that voltages are set such that VEE VSSON C
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EK7304
ELECTRICAL CHARACTERISTICS Table 6. DC Characteristics (VSS=0 V, VDD=+2.5V to +5.5V, VGG=+15.0 to +42.0 V, TOPR=-20 to +75 ) Parameter Symbol Conditions Applicable Min. Typ. Max. Unit pins Operating Supply IDD fFX=15.7kHz 800 A VDD Current fSL=60Hz VDD=3.3V www..com VEE=-15V VGG=15V Output with no load Operating Supply IGG VGG 300 A Current VDD Standby quiescent IDS Standby 600 A supply current VDD=3.3V VEE=-15V VGG=15V Standby quiescent IGS VGG 100 A Supply Current Input pin RL,FX, H input voltage VIH1 0.8xVDD VDD V OE1~3, L input voltage VIL1 0 0.2xVDD V XDON Input leakage current VLI1 -10 10 A Output pin H input voltage VIH3 0.8xVDD VDD V DIO1, DIO2 L input voltage VIL3 0.2xVDD V H output voltage VOH IO = -100 A VDD-0.4 V L output voltage VOL IO = 100 A 0.4 V Liquid crystal driving voltage input pin Input leakage current VLI2 VOFF -100 100 A Liquid crystal driving output pin X1~X256 Output leakage current VLO1 -50 50 A 600 1000 Output ON resistance RON- VGG=15V VGG VEE=-15V VOM=VGG-0.5V VOM is X1~X256 600 1000 RON- VGG=15V VEE=-15V VOFF VOFF=-10v VOM=VOFF+0.5V VOM is X1~X256
Note
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AC Characteristics (VSS= 0 V, VDD=+2.5V to +5.5V, VGG-VEE=+30.0 to +42.0 V, TOPR=-20 to +75 ) Parameter Symbol Conditions Min. Clock period tFX 833 Pulse width of clock H level Pulse width of clock L level DIO data set up time
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EK7304
Typ. Max. Unit ns ns ns ns ns 300 800 ns ns
tWH tWL tsu th tpd1 tpd2 CL=50pF CL=300pF
350 350 50 350
DIO data hold time DIO output delay time Xn output delay time Timing Chart
tWL
tWH 20% tsu 80% 80% th 80% 50% 20%
tFX 50%
FX
20%
80%
DIO input
tpd1 tpd1 60% tpd2 60% 40% 40%
DIO output
Xn
80% tpd2
OEm
20% tpd2 40% 60%
Xn
XDON
10% tpd2
90% tpd2 60% 40%
Xn
Fig. 9. Timing
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EK7304
DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary This data sheet contains preliminary data; supplementary data may be published specification later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification.
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LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Eureka for any damages resulting from such improper use or sale.
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