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Intel386 TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT (PQFP SUPPLEMENT)
Y
Y
Y
Y
Y
Y
Flexible 32-Bit Microprocessor 8 16 32-Bit Data Types 8 General Purpose 32-Bit Registers Very Large Address Space 4 Gigabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Protection Fully Compatible with 80286 Object Code Compatible with All 8086 Family Microprocessors Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System Hardware Debugging Support
Y
Optimized for System Performance Pipelined Instruction Execution On-Chip Address Translation Caches 20 25 and 33 MHz Clock 40 50 and 66 Megabytes Sec Bus Bandwidth Numerics Support via Intel387 TM DX Math Coprocessor Complete System Development Support Software C PL M Assembler System Generation Tools Debuggers PSCOPE ICE TM -386 High Speed CHMOS IV Technology 132 Pin PQFP Package
(See Packaging Specification Order 231369)
Y
Y
Y Y
The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes (2 46) of virtual memory The integrated memory management and protection architecture includes address translation registers multitasking hardware and a protection mechanism to support operating systems Instruction pipelining on-chip address translation ensure short average instruction execution times and maximum system throughput The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code execution or data accesses for powerful debugging of even ROM-based systems Object-code compatibility with all 8086 family members (8086 8088 80186 80188 80286) means the Intel386 DX offers immediate access to the world's largest microprocessor software base
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Intel386 TM DX Pipelined 32-Bit Microarchitecture
Intel386TM DX and Intel387TM DX are Trademarks of Intel Corporation MS-DOS and Windows are Trademarks of MICROSOFT Corporation
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
January 1994
Order Number 241267-003
Intel386 TM DX Microprocessor High-Performance 32-Bit CHMOS Microprocessor with Integrated Memory Management (PQFP Supplement)
CONTENTS
1 0 PIN ASSIGNMENT 1 1 Pin Description Table 1 2 Float Pin Description 2 0 MECHANICAL DATA 2 1 Package Physical Dimensions 2 2 Package Thermal Specifications PAGE
3 5 7 8 8 11
CONTENTS
3 0 D C A C SPECIFICATIONS 3 1 D C Specifications 3 2 A C Specifications 3 2 1 A C Spec Definitions 3 2 2 A C Specification Tables 3 2 3 A C Test Loads 3 2 4 A C Timing Waveforms 3 2 5 Typical Output Valid Delays 3 2 6 Typical Output Valid Delays 3 2 7 Typical Output Valid Delays 3 2 8 Typical Output Rise Times
PAGE
12 12 13 13 14 20 20 22 22 23 23
2
Intel386 TM DX PQFP MICROPROCESSOR
This document should be used in conjunction with the Intel386 TM DX Microprocessor data sheet (order number 231630-011 October 1993) The circuit board should include VCC and GND planes for power distribution and all VCC and VSS pins must be connected to the appropriate plane NOTE Pins identified as ``N C '' should remain completely unconnected
10
PIN ASSIGNMENT
The Intel386 DX pinout as viewed from the top side of the component is shown by Figure 1-1 VCC and GND connections must be made to multiple VCC and VSS (GND) pins Each VCC and VSS must be connected to the appropriate voltage level
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Figure 1-1
Intel386 TM
DX PQFP Pinout
View from Top Side
3
Intel386 TM DX PQFP MICROPROCESSOR
Table 1-1 Intel386 TM DX PQFP Pinout Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 67 68 69 70 71 72 74 75 76 77 78 79 81 82 84 86 87 88 89 93 94 95 96 97 98 100 101 102 103 104 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Data 20 19 18 17 15 14 13 12 9 7 6 5 4 3 131 130 129 128 126 125 124 121 120 119 118 116 115 113 112 109 108 107 Control ADS BE0 BE1 BE2 BE3 BS16 BUSY CLK2 DC ERROR FLT HLDA HOLD INTR LOCK M IO NA NMI PEREQ READY RESET WR
Functional Grouping NC 27 31 32 33 38 29 46 24 41 47 54 8 28 53 42 40 30 52 50 26 45 43 36 37 39 59 60 61 62 63 VSS 1 10 11 21 23 25 35 44 48 51 55 57 64 65 66 80 83 90 91 92 105 111 114 122 132 VCC 2 16 22 34 49 56 58 73 85 99 106 110 117 123 127
4
Intel386 TM DX PQFP MICROPROCESSOR
1 1 Pin Description Table
The following table lists a brief description of each pin on the Intel386 DX The following definitions are used in these descriptions The named signal is active LOW I O IO Input signal Output signal Input and Output signal No electrical connection Symbol CLK2 D31 -D0 A31 -A2 BE0 -BE3 WR DC Type I IO O O O O Name and Function CLK2 provides the fundamental timing for the Intel386 DX DATA BUS inputs data during memory I O and interrupt acknowledge read cycles and outputs data during memory and I O write cycles ADDRESS BUS outputs physical memory or port I O addresses BYTE ENABLES indicate which data bytes of the data bus take part in a bus cycle WRITE READ is a bus cycle definition pin that distinguishes write cycles from read cycles DATA CONTROL is a bus cycle definition pin that distinguishes data cycles either memory or I O from control cycles which are interrupt acknowledge halt and instruction fetching MEMORY I O is a bus cycle definition pin that distinguishes memory cycles from input output cycles BUS LOCK is a bus cycle definition pin that indicates that other system bus masters are denied access to the system bus while it is active ADDRESS STATUS indicates that a valid bus cycle definition and address (W R DC M IO BE0 BE1 BE2 BE3 and A31 -A2) are being driven at the Intel386 DX pins NEXT ADDRESS is used to request address pipelining BUS READY terminates the bus cycle BUS SIZE 16 input allows direct connection of 32-bit and 16-bit data buses BUS HOLD REQUEST input allows another bus master to request control of the local bus
M IO LOCK ADS
O O O
NA READY BS16 HOLD
I I I I
5
Intel386 TM DX PQFP MICROPROCESSOR
1 1 Pin Description Table (Continued)
Symbol HLDA BUSY ERROR PEREQ FLT Type O I I I I Name and Function BUS HOLD ACKNOWLEDGE output indicates that the Intel386 DX has surrendered control of its local bus to another bus master BUSY signals a busy condition from a processor extension ERROR signals an error condition from a processor extension PROCESSOR EXTENSION REQUEST indicates that the processor extension has data to be transferred by the Intel386 DX FLOAT is an input which forces all bidirectional and output signals including HLDA to the tri-state condition This allows the electrically isolated 386 DX PQFP to use On-Circuit Emulation (ONCE) directly on the motherboard The FLT pin has an internal pull-up resistor if the FLT pin is not used it should not be connected INTERRUPT REQUEST is a maskable input that signals the Intel386 DX to suspend execution of the current program and execute an interrupt acknowledge function NON-MASKABLE INTERRUPT REQUEST is a non-maskable input that signals the Intel386 DX to suspend execution of the current program and execute an interrupt acknowledge function RESET suspends any operation in progress and places the Intel386 DX in a known reset state See Interrupt Signals for additional information NO CONNECT should always remain unconnected Connection of a N C pin may cause the processor to malfunction or be incompatible with future steppings of the Intel386 DX I I SYSTEM POWER provides the a 5V nominal D C supply input SYSTEM GROUND provides 0V connection from which all inputs and outputs are measured
INTR NMI
I I
RESET NC
I
VCC VSS
6
Intel386 TM DX PQFP MICROPROCESSOR
nized it aborts the current bus cycle and floats the outputs of the processor (Figure 1-2) FLT must be held low for a minimum of 16 CLK2 cycles Reset should be asserted and held asserted until after FLT is deasserted This will ensure that the Intel386 DX CPU will exit float in a valid state Asserting the FLT input unconditionally aborts the current bus cycle and forces the processor into the FLOAT mode and is therefore not guaranteed to enter FLOAT in a valid state After deactivating the processor is not guaranteed to exit FLT FLOAT mode in a valid state This is not a problem as the FLT pin is meant to be used only during ONCE After exiting FLOAT the processor must be reset to return it to a valid state Reset should be asserted before FLT is deasserted This will ensure that the processor will exit float in a valid state FLT has an internal pull-up resistor and if it is not used it should be unconnected
1 2 Float Pin Description
Activating the FLT input floats all Intel386 DX bidirectional and output signals including HLDA Asserting FLT isolates the Intel386 DX microprocessor from the surrounding circuitry Packaged in a surface mount PQFP it cannot be removed from the motherboard when In-Circuit Emulation (ICE) is needed The FLT input allows the Intel386 CPU to be electrically isolated from the surrounding circuitry This allows connection of an emulator to the processor without removing it from the PCB This method of emulation is referred to as ONCircuit Emulation (ONCE) ENTERING AND EXITING FLOAT FLT is an asynchronous active-low input It is recognized on the rising edge of CLK2 When recog-
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Figure 1-2 Entering and Exiting FLT
7
Intel386 TM DX PQFP MICROPROCESSOR
20
MECHANICAL DATA
2 1 Package Dimensions
The Intel386 DX is available in a 132 lead plastic quad flat pack (PQFP) package Table 2 1 and Figures 2 1-2 5 show the physical dimensions of this package Table 2 1 Intel Case Outline Dimensions for 132 Lead Plastic Quad Flat Pack 0 025 Inch Pitch Symbol A A1 DE D1 E1 D2 E2 D3 E3 L1 Issue Description Min Package Height Standoff Terminal Dimension Package Body Bumper Distance Lead Dimension Foot Length 0 160 0 020 1 075 0 947 1 097 Inch Max 0 170 0 030 1 085 0 953 1 103 Min 4 06 0 51 27 31 24 05 27 86 mm Max 4 32 0 76 27 56 24 21 28 02
0 800 REF 0 020 0 030 0 51
20 32 REF 0 76
IWS Preliminary 1 15 87 Symbol List
Letter or Symbol A A1 DE D1 E1 D2 E2 D3 E3 L1
Description of Dimensions Package Height Distance from Seating Plane to Highest Point of Body Standoff Distance from Seating Plane to Base Plane Overall Package Dimension Lead Tip to Lead Tip Plastic Body Dimension Bumper Distance Footprint Foot Length
NOTES 1 All dimensions and tolerances conform to ANSI Y14 5M-1982 2 Datum plane H located at the mold parting line and coincident with the bottom of the lead where lead exits plastic body 3 Datums A B and D to be determined where center leads exit plastic body at datum plane H 4 Controlling Dimension Inch 5 Dimensions D1 D2 E1 and E2 are measured at the mold parting line and do not include mold protrusion Allowable mold protrusion is 0 18 mm (0 007 in) per side 6 Pin 1 identifier is located within one of the two zones indicated
8
Intel386 TM DX PQFP MICROPROCESSOR
mm (inch)
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Figure 2 1 Principal Dimensions and Datums
mm (inch)
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Figure 2 2 Molded Details
mm (inch)
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Figure 2 3 Terminal Details
9
Intel386 TM DX PQFP MICROPROCESSOR
mm (inch)
Detail J
Detail L
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Figure 2 4 Typical Lead
mm (inch)
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Figure 2 5 Detail M
10
Intel386 TM DX PQFP MICROPROCESSOR
Tj e Tc a P ijc Ta e Tj b P ija Tc e Ta a P ija b ijc
2 2 Package Thermal Specifications
The Intel386 DX Microprocessor is specified for operation when case temperature is within the range of 0 C-100 C The case temperature may be measured in any environment to determine whether the Intel386 DX Microprocessor is within specified operating range The case temperature should be measured at the center of the top surface The ambient temperature is guaranteed as long as Tc is not violated The ambient temperature can be calculated from the ijc and ija from the following equations
Values for ija and ijc are given in Table 2 2 for the 100 lead fine pitch ija is given at various airflows Table 2 3 shows the maximum Ta allowable (without exceeding Tc) at various airflows
Table 2 2 Thermal Resistances ( C Watt) ijc and ija ija versus Airflow - ft min (m sec) Package ijc 0 (0) 31 0 200 (1 01) 24 5 400 (2 03) 21 5 600 (3 04) 19 0 800 (4 06) 17 0 1000 (5 07) 16 0
132 Lead PQFP
90
Table 2 3 Maximum Ta at various airflows TA( C) versus Airflow - ft min (m sec) Package Frequency 0 (0) 71 65 60 200 (1 01) 79 75 72 400 (2 03) 83 80 78 600 (3 04) 87 84 82 800 (4 06) 89 87 85 1000 (5 07) 90 89 87
132 Lead PQFP
20 MHz 25 MHz 33 MHz
NOTE The numbers in Table 2 3 were calculated using worst case ICC at TC e 100 C with the outputs unloaded
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Intel386 TM DX PQFP MICROPROCESSOR
Table 3-1 is a stress rating only and functional operation at the maximums is not guaranteed Functional operating conditions are given in 3 1 D C Specifications and 3 2 A C Specifications Extended exposure to the Maximum Ratings may affect device reliability Furthermore although the Intel386 DX contains protective circuitry to resist damage from static electric discharge always take precautions to avoid high static voltages or electric fields
30
D C A C SPECIFICATIONS
Table 3-1 Maximum Ratings
Parameter Intel386TM DX 20 25 33 MHz Maximum Rating
b 65 C to a 150 C b 65 C to a 110 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V
Storage Temperature Case Temperature Under Bias Supply Voltage with Respect to VSS Voltage on Other Pins
3 1 D C Specifications
Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-2 Intel386 TM DX D C Characteristics Symbol Parameter Intel386 TM DX 20 MHz 25 MHz 33 MHz Min VIL VIH VILC VIHC Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage 20 MHz 25 MHz and 33 MHz Output Low Voltage IOL e 4 mA A2-A31 D0-D31 IOL e 5 mA BE0 -BE3 W R D C M IO LOCK ADS HLDA Output High Voltage IOH e 1 mA A2-A31 D0-D31 IOH e 0 9 mA BE0 -BE3 W R D C M IO LOCK ADS HLDA Input Leakage Current (For All Pins except BS16 PEREQ BUSY and ERROR ) Input Leakage Current (PEREQ Pin) Input Leakage Current (BS16 BUSY and ERROR Pins) Output Leakage Current Supply Current CLK2 e 40 MHz with 20 MHz Intel386 TM DX CLK2 e 50 MHz with 25 MHz Intel386 TM DX CLK2 e 66 MHz with 33 MHz Intel386 TM DX Input or I O Capacitance Output Capacitance CLK2 Capacitance
b0 3
Unit
Test Conditions (Note 1) (Note 1)
Max 08 VCC a 0 3 08
V V V V V V V
20 b0 3
VCC b 0 8 VCC a 0 3 37 VCC a 0 3 0 45 0 45
VOL
VOH
24 24
g15
V V mA 0V s VIN s VCC
ILI
IIH IIL ILO ICC
200
b 400
g15
mA VIH e 2 4V (Note 2) mA VIL e 0 45 (Note 3) mA 0 45V s VOUT s VCC (Note 4) mA ICC Typ e 200 mA mA ICC Typ e 240 mA mA ICC Typ e 300 mA pF FC e 1 MHz pF FC e 1 MHz pF FC e 1 MHz
CIN COUT CCLK
260 320 390 10 12 20
NOTES 1 The min value b0 3 is not 100% tested 2 PEREQ input has an internal pulldown resistor 3 BS16 BUSY and ERROR inputs each have an internal pullup resistor 4 CHMOS IV Technology
12
Intel386 TM DX PQFP MICROPROCESSOR
The minimum Intel386 DX delay times are hold times provided to external circuitry Intel386 DX input setup and hold times are specified as minimums defining the smallest acceptable sampling window Within the sampling window a synchronous input signal must be stable for correct Intel386 DX operation Outputs NA WR DC M IO LOCK A2 - A31 and HLDA only change at BE0 - BE3 the beginning of phase one D0 - D31 (write cycles) only change at the beginning of phase two The READY HOLD BUSY ERROR PEREQ and D0 - D31 (read cycles) inputs are sampled at the beginning of phase one The NA BS16 INTR and NMI inputs are sampled at the beginning of phase two
32
A C SPECIFICATIONS
3 2 1 A C Spec Definitions
The A C specifications given in Tables 3-3 3-4 and 3-5 consist of output delays input setup requirements and input hold requirements All A C specifications are relative to the CLK2 rising edge crossing the 2 0V level A C spec measurement is defined by Figure 3-1 Inputs must be driven to the voltage levels indicated by Figure 3-1 when A C specifications are measured Intel386 DX output delays are specified with minimum and maximum limits measured as shown
241267 - 7
NOTES 1 Input waveforms have tr s 2 0 ns from 0 8V to 2 0V 2 See section 9 5 8 for typical output rise time versus load capacitance
Figure 3-1 Drive Levels and Measurement Points for A C Specifications
13
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-3 33 MHz Intel386 TM DX A C Characteristics Symbol Parameter 33 MHz Intel386 TM DX Min Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t9 t10 t10a t11 t12 t12a t13 t14 t15 t16 t17 t18 t19 t20 CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A2-A31 Valid Delay A2-A31 Float Delay BE0 -BE3 BE0 -BE3 WR ADS WR M IO LOCK LOCK DC Valid Delay Float Delay Valid Delay 4 4 4 4 4 4 ADS Float Delay 4 7 2 4 4 5 2 5 2 7 4 17 20 ns ns ns ns ns ns ns ns 8 15 0 6 25 45 6 25 45 4 4 15 20 15 20 15 14 5 20 24 Max 33 3 62 5 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-3 3-3 3-3 3-3 3-3 3-3 3-3 3-5 3-6 3-5 3-6 3-5 3-5 3-6 at 2V at 3 7V at 2V at 0 8V 3 7V to 0 8V (Note 3) 0 8V to 3 7V (Note 3) CL e 50 pF (Note 1) CL e 50 pF (Note 1) CL e 50 pF CL e 50 pF (Note 1) Half of CLK2 Frequency Unit Ref Fig Notes
Valid Delay M IO DC
D0-D31 Write Data Valid Delay D0-D31 Write Data Hold Time D0-D31 Float Delay HLDA Valid Delay NA NA BS16 BS16 READY READY Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time
3-5a CL e 50 pF (Note 4) 3-5b CL e 50 pF 3-6 3-6 3-4 3-4 3-4 3-4 3-4 3-4 (Note 1) CL e 50 pF
14
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES (Continued) Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-3 33 MHz Intel386 TM DX A C Characteristics (Continued) Symbol Parameter 33 MHz Intel386 TM DX Min t21 t22 t23 t24 t25 t26 t27 t28 t29 t30
NOTES 1 Float condition occurs when maximum output current becomes less than ILO in magnitude Float delay is not 100% tested 2 These inputs are allowed to be asynchronous to CLK2 The setup and hold specifications are given for testing purposes to assure recognition within a specific CLK2 period 3 Rise and fall times are not tested 4 Min time not 100% tested
Unit
Ref Fig 3-4 3-4 3-4 3-4 3-7 3-7 3-4 3-4 3-4 3-4
Notes
Max ns ns ns ns ns ns ns ns ns ns
D0-D31 Read Setup Time D0-D31 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI INTR Setup Time NMI INTR Hold Time PEREQ ERROR PEREQ ERROR FLT FLT BUSY BUSY Setup Time Hold Time
5 3 11 2 5 2 5 5 5 4
(Note 2) (Note 2) (Note 2) (Note 2)
15
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES (Continued) Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-4 25 MHz Intel386 TM DX A C Characteristics Symbol Parameter 25 MHz Intel386 TM DX Min Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t8a t9 t10 t11 t12 t12a t13 t14 t15 t16 t17 t18 t19 t20 CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A2-A31 Valid Delay A2-A31 Float Delay BE0 -BE3 LOCK Valid Delay 4 4 4 4 Float Delay ADS ADS Valid Delay Float Delay 4 4 4 7 2 4 4 7 3 7 3 9 4 22 22 ns ns ns ns ns ns ns ns 4 20 7 4 7 5 7 7 21 30 24 21 30 21 30 27 Max 25 125 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-3 3-3 3-3 3-3 3-3 3-3 3-3 3-5 3-6 3-5 3-5 3-6 3-5 3-6 at 2V at 3 7V at 2V at 0 8V 3 7V to 0 8V 0 8V to 3 7V CL e 50 pF (Note 1) CL e 50 pF CL e 50 pF (Note 1) CL e 50 pF (Note 1) Half of CLK2 Frequency Unit Ref Fig Notes
Valid Delay LOCK DC DC
BE0 -BE3 WR WR M IO M IO
D0-D31 Write Data Valid Delay D0-D31 Write Data Hold Time D0-D31 Float Delay HLDA Valid Delay NA NA BS16 BS16 READY READY Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time
3-5a CL e 50 pF 3-5b CL e 50 pF 3-6 3-6 3-4 3-4 3-4 3-4 3-4 3-4 (Note 1) CL e 50 pF
16
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES (Continued) Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-4 25 MHz Intel386 TM DX A C Characteristics (Continued) Symbol Parameter 25 MHz Intel386 TM DX Min t21 t22 t23 t24 t25 t26 t27 t28 t29 t30
NOTES 1 Float condition occurs when maximum output current becomes less than ILO in magnitude Float delay is not 100% tested 2 These inputs are allowed to be asynchronous to CLK2 The setup and hold specifications are given for testing purposes to assure recognition within a specific CLK2 period 3 Symbol Parameter Min t30 PEREQ ERROR FLT BUSY Hold Time 4 TC e 0 C t30 PEREQ ERROR FLT BUSY Hold Time 5 TC e a 100 C
Unit
Ref Fig 3-4 3-4 3-4 3-4 3-7 3-7 3-4 3-4 3-4 3-4
Notes
Max ns ns ns ns ns ns ns ns ns ns
D0-D31 Read Setup Time D0-D31 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI INTR Setup Time NMI INTR Hold Time PEREQ ERROR PEREQ ERROR FLT FLT BUSY BUSY Setup Time Hold Time
7 5 15 3 10 3 6 6 6 5
(Note 2) (Note 2) (Note 2) (Notes 2 3)
17
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES (Continued) Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-5 20 MHz Intel386 TM DX A C Characteristics Symbol Parameter Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A2-A31 Valid Delay A2-A31 Float Delay BE0 -BE3 Valid Delay BE0 -BE3 Float Delay WR ADS WR ADS LOCK LOCK 4 4 4 4 6 6 4 4 6 9 14 13 21 12 4 11 6 17 5 12 20 MHz Intel386 TM DX Min 4 25 8 5 8 6 8 8 30 32 30 32 28 30 38 27 28 Max 20 125 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-3 3-3 3-3 3-3 3-3 3-3 3-3 3-5 3-6 3-5 3-6 3-5 3-6 3-5c 3-6 3-6 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-7 at 2V at (VCC b 0 8V) at 2V at 0 8V (VCC b 0 8V) to 0 8V 0 8V to (VCC b 0 8V) CL e 120 pF (Note 1) CL e 75 pF (Note 1) CL e 75 pF (Note 1) CL e 120 pF (Note 1) CL e 75 pF Half of CLK2 Frequency Unit Ref Fig Notes
M IO D C Valid Delay M IO D C Float Delay
D0-D31 Write Data Valid Delay D0-D31 Float Delay HLDA Valid Delay NA NA BS16 BS16 READY READY Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time
D0-D31 Read Setup Time D0-D31 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time
18
Intel386 TM DX PQFP MICROPROCESSOR
3 2 2 A C SPECIFICATION TABLES (Continued) Functional Operating Range VCC e 5V g5% TCASE e 0 C to a 100 C Table 3-5 20 MHz Intel386 TM DX A C Characteristics (Continued) Symbol Parameter 20 MHz Intel386 TM DX Min t26 t27 t28 t29 t30 RESET Hold Time NMI INTR Setup Time NMI INTR Hold Time PEREQ ERROR FLT BUSY Setup Time PEREQ ERROR FLT BUSY Hold Time 4 16 16 14 5 Max ns ns ns ns ns 3-7 3-4 3-4 3-4 3-4 (Note 2) (Note 2) (Note 2) (Note 2) Unit Ref Fig Notes
NOTES 1 Float condition occurs when maximum output current becomes less than ILO in magnitude Float delay is not 100% tested 2 These inputs are allowed to be asynchronous to CLK2 The setup and hold specifications are given for testing purposes to assure recognition within a specific CLK2 period
19
Intel386 TM DX PQFP MICROPROCESSOR
3 2 3 A C TEST LOADS
3 2 4 A C TIMING WAVEFORMS
241267 - 8 CL e 120 pF on A2 - A31 D0 - D31 CL e 75 pF on BE0 - BE3 WR LOCK HLDA CL includes all parasitic capacitances M IO DC ADS
241267 - 9
Figure 3-2 A C Test Load
Figure 3-3 CLK2 Timing
241267 - 10
Figure 3-4 Input Setup and Hold Timing
20
Intel386 TM DX PQFP MICROPROCESSOR
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Figure 3-5 Output Valid Delay Timing
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241267 - 13
Figure 3-5a Write Data Valid Delay Timing (25 MHz 33 MHz)
Figure 3-5b Write Data Hold Timing (25 MHz 33 MHz)
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Figure 3-5c Write Data Valid Delay Timing (20 MHz)
21
Intel386 TM DX PQFP MICROPROCESSOR
3 2 5 TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (CL e 120 pF)
241267 - 15
NOTE This graph will not be linear outside of the CL range shown
3 2 6 TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (CL e 75 pF)
241267 - 16
NOTE This graph will not be linear outside of the CL range shown
22
Intel386 TM DX PQFP MICROPROCESSOR
3 2 7 TYPICAL OUTPUT VALID DELAY VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE (CL e 50 pF)
241267 - 17
NOTE This graph will not be linear outside of the CL range shown
3 2 8 TYPICAL OUTPUT RISE TIME VERSUS LOAD CAPACITANCE AT MAXIMUM OPERATING TEMPERATURE
241267 - 18
NOTE This graph will not be linear outside of the CL range shown
23
Intel386 TM DX PQFP MICROPROCESSOR
241267 - 19
Figure 3-6 Output Float Delay and HLDA Valid Delay Timing
241267 - 20 The second internal processor phase following RESET high-to-low transition (provided t25 and t26 are met) is w2
Figure 3-7 RESET Setup and Hold Timing and Internal Phase
24

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