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| 2 W530-02 Frequency Multiplying, Peak Reducing EMI Solution Features * Cypress PREMISTM family offering * Generates an EMI optimized clocking signal at the output * Selectable frequency range and multiplication factor * Single 1.25%, 2.5%, 5%, or 10%, down or center spread output * Integrated loop filter components * Operates with a 3.3V or 5V supply * Low power CMOS design * Higher drive strength, higher frequency support than W530 * Available in 20-pin SSOP Table 2. Modulation Width Selection MW2 0 0 0 0 1 1 1 1 MW1 0 0 1 1 0 0 1 1 MW0 0 1 0 1 0 1 0 1 Output Fin Fout Fin -1.25% Favg + 0.625% Fout Favg - 0.625% Fin Fout Fin - 2.5% Favg + 1.25% Fout Favg - 1.25% Fin Fout Fin - 5% Favg + 2.5% Fout Favg - 2.5% Fin Fout Fin - 10% Favg + 5% Fout Favg - 5% Key Specifications Supply Voltages: .......................................VDD = 3.3V 0.3V or VDD = 5V 10% Frequency Range: .........................13 MHz Fout 166 MHz Cycle to Cycle Jitter: ....................................... 250 ps (max.) Output Duty Cycle: ............................... 40/60% (worst case) Table 1. Output Frequency Range Selection OR2 0 0 1 1 OR1 0 1 0 1 Output Range (Multiplication Factor Selection) reserved 13 MHz FOUT 30 MHz 25 MHz FOUT 60 MHz 50 MHz FOUT 166 MHz Table 3. Input Frequency Range Selection IR2 0 0 1 1 IR1 0 1 0 1 Input Range reserved 13 MHz FIN 30 MHz 25 MHz FIN 60 MHz 50 MHz FIN 166 MHz Simplified Block Diagram 3.3V or 5.0V Pin Configuration[1] SSOP X1 XTAL Input X2 W530-02 Spread Spectrum Output (EMI suppressed) X1 X2 AVDD MW0^ STOP^ OR1^ NC GND OR2* SSON# 1 2 3 4 5 6 20 19 18 17 16 15 14 13 12 11 REFOUT VDD GND IR1* IR2* SSOUT MW1* GND VDD MW2^ W530-02 7 8 9 3.3V or 5.0V 10 Oscillator or Reference Input X1 W530-02 Spread Spectrum Output (EMI suppressed) Note: 1. Pins that are marked with [*] have internal pull-up resistors. Pins that are marked with [^] have internal pull-down resistors. PREMIS is a trademark of Cypress Semiconductor. Cypress Semiconductor Corporation Document #: 38-07190 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised November 14, 2001 W530-02 Pin Definitions Pin Name SSOUT REFOUT Pin No. 15 20 Pin Type O O Pin Description Output Modulated Frequency: Frequency modulated signal. Frequency of the output is selected as shown in Table 1. Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature regardless of the state of logic input SSON#. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: Input connection for an external crystal. If using an external reference signal, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection: When the Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal (see Table 2). MW0: DOWN, MW1: UP, MW2: DOWN. Reference Frequency Selector: The logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. No Connection: Leave this pin unconnected. Output Disable: When pulled HIGH, stops all outputs at logic low voltage level. This pin has an internal pull-down. Output Frequency Selection Bits: These pins select the frequency of operation for the output. Refer to Table 1. OR1: DOWN, OR2: UP. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common ground plane. CLKIN or X1 1 I NC or X2 SSON# 2 10 I I MW0:2 4, 14, 11 I IR1:2 17,16 I NC STOP OR1:2 VDD GND 7 5 6,9 3, 12, 19 8, 13, 18 NC I I P G Document #: 38-07190 Rev. ** Page 2 of 8 W530-02 Overview The W530-02 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. The W530-02 also allows for frequency multiplication in order to determine the relationship between the input and output frequencies. Simply compare the min. frequency of the input and output ranges selected (use 12.5 instead of 13 for this calculation, though). The multiplication options are: 0.25, 0.5,1.0, 2.0 and 4.0. to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (IR1:2, OR1:2 pins), the frequency range can be set (see Tables 1 and 3). Spreading percentage is set with pins MW0:2 as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. Functional Description The W530-02 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back VDD Clock Input Freq. Divider Q Phase Detector Charge Pump Reference Input VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Conceptual Block Diagram Document #: 38-07190 Rev. ** Page 3 of 8 W530-02 Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX - XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. When the SSON# pin is asserted (active LOW) the spreading feature is enabled. Spreading feature is disabled when SSON# is set HIGH (VDD). Frequency Span (MHz) Center Spread Figure 2. Typical Clock and SSFTG Comparison 100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100% Frequency Shift 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% Time Figure 3. Modulation Waveform Profile Document #: 38-07190 Rev. ** 100% Page 4 of 8 W530-02 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W Parameter VDD, VIN TSTG TA TB PD Description Voltage on any Pin with Respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 0.3V Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 80 25 Note 2 Note 2 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V 15 15 7 2.4 -100 10 2.4 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 18 Max. 32 5 0.8 Unit mA ms V V V V A A mA mA pF k Note: 2. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor. Document #: 38-07190 Rev. ** Page 5 of 8 W530-02 DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10% Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 80 25 Note 2 Note 2 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V 24 24 7 2.4 -100 10 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 30 Max. 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF k AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 0.3V Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Test Condition Input Clock Spread Off VDD, 15-pF load, 0.8V-2.4V VDD, 15-pF load, 2.4V-0.8V 15-pF load 40 40 250 Min. 14 13 2 2 Typ. Max. 166 166 5 5 60 60 300 Unit MHz MHz ns ns % % ps AC Electrical Characteristics: TA = 0C to +70C, VDD = 5V10% Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Test Condition Input Clock Spread Off VDD, 15-pF load, 0.8V-2.4V VDD, 15-pF load, 2.4V-0.8V 15-pF load 45 40 100 Min. 14 13 2 2 Typ. Max. 166 166 5 5 55 60 200 Unit MHz MHz ns ns % % ps Ordering Information Ordering Code W530-02 Package Name H Package Type 20-Pin Plastic SSOP (209-mil) Document #: 38-07190 Rev. ** Page 6 of 8 W530-02 Package Diagram 20-Pin Small Shrink Outline Package (SSOP, 209-mil) Document #: 38-07190 Rev. ** Page 7 of 8 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W530-02 Document Title: W530-02 Frequency Multiplying, Peak Reducing EMI Solution Document Number: 38-07190 REV. ** ECN NO. 110591 Issue Date 01/07/02 Orig. of Change DSG Description of Change Change from Spec number: 38-01062 to 38-07190 Document #: 38-07190 Rev. ** Page 8 of 8 |
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