View FAN6208_5066613.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
November 2010
FAN6208 Secondary-Side Synchronous Rectifier Controller for LLC Topology
Features
Specialized SR Controller for LLC or LC Resonant Converters Secondary-Side Timing Detection with Timing Estimator Gate-Shrink Function to Prevent Shoot-Through During Load and Line Transient Green-Mode Function for Higher Efficiency at LightLoad Condition Programmable Dead Time between Primary-Side Gate Drive Signal and SR Drive Signal Advanced Output-Short / Overload Protection Based on the Feedback Information Internal Over-Temperature Protection (OTP) VDD Pin Over-Voltage Protection (OVP)
Description
FAN6208 is a synchronous rectification (SR) controller for isolated LLC or LC resonant converters that can drive two individual SR MOSFETs emulating the behavior of rectifier diodes. FAN6208 measures the SR conduction time of each switching cycle by monitoring the drain-to-source voltage of each SR and determines the optimal timing of the SR gate drive. FAN6208 uses the change of opto-coupler diode current to adaptively shrink the duration of SR gate drive signals during load transients to prevent shoot-through. To improve lightload efficiency, Green-Mode operation is employed, which disables the SR drive signals, minimizing gate drive power consumption at light-load condition. Optimal timing circuits and protection functions are integrated in an 8-pin SOP package, which allows highefficiency power supply design with fewer components.
Applications
LCD TV PC Power Open-Frame SMPS
Ordering Information
Part Number
FAN6208MY
Operating Temperature Range
-40C to +105C
Package
8-Pin Small Outline Package (SOP)
Packing Method
Tape & Reel
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Application Diagram
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1 www.fairchildsemi.com 2
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Marking Information
6208 6208 TPM
F- Fairchild Logo Z- Plant Code X- Year Code Y- Week Code TT: Die Run Code T - Package Type (M = SOP) P - Y: Green Package M - Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Assignments
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
DETL1 DETL2 RP FD VDD GATE2 GND GATE1
Description
Low Detect provides low-voltage detection of VDS of SR MOSFET1. Low Detect provides low-voltage detection of VDS of SR MOSFET2. Dead Time Programming Resistor programs H/L frequency version and dead time. Feedback Detection is used for short-circuit protection and gate shrink. Power Supply Driver Output. The totem-pole output driver for driving the SR MOSFET2. Ground Driver Output. The totem-pole output driver for driving the SR MOSFET1.
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 3
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VFD VLV PD JA JT TJ TSTG TL ESD Supply Voltage Voltage on FD Pin
Parameter
Min.
Max.
30 30
Unit
V V V
Voltage on DETL1, DETL2, RP Pins Power Dissipation Junction-to-Ambient Thermal Resistance Junction-to-Top Thermal Characteristics Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101
-0.3 350Mw at TA=90C
7.0 1000mW at TA=25C 130 45
C/W C/W C C C kV
-40 -55
+125 +150 +260 6 2
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
C
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 4
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
VDD=20V, TA=25C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
VDD Section VDD IDD-OP1 IDD-OP2 IDD-ST
Parameter
DC Supply Voltage Operating Current Operating Current Startup Current
Conditions
Min.
VTH-OFF
Typ.
Max.
28
Units
V mA mA A V V V V s
VDD=12V, DETL=50KHz, CL=6nF, RRP=24K VDD=12V, DETL=100KHz VDD=8V
7.0 2.4 180 9.3 8.3 26 1.3 30
8.5 3.2 300 9.7 8.8 27 1.8 60
10.0 4.0 500 10.1 9.3 28 2.3 100
VTH-ON1 VTH-ON2 On Threshold Voltage VTH-OFF1 VTH-OFF2 VDD-OVP1 VDD-OVP2 VDD-OVP-HYS1 VDD-OVP-HYS2 tOVP1,tOVP2 DETL Section VDETL1 VDETL2 tSR-ON-DETL1 tSR-ON-DETL2 Threshold Voltage for LOW VDD=12V, DETL=50KHz, Detection of DETL CL=6nF, RRP=24K Delay from DETL LOW to SR Gate Turn-On tDB+ tPD+ tR VDD=12V, DETL Pin Floating VDETL1=0V Off Threshold Voltage VCC Over-Voltage Protection VCC Over-Voltage Protection Hysteresis VCC Over-VoltageProtection Debounce
1.7 300 4.5 40
2.0 350
2.3 400
V ns V
VDETL-FLOATING1 DETL Floating Voltage VDETL-FLOATING2 IDETL-SOURCE1 IDETL-SOURCE2 tDETL_Green_LF1 tDETL_Green_LF2 DETL Source Current DETL LOW Time Threshold for Green Mode at Low-Frequency Operation
50
60
A
VRP < 1.5V
3.50
3.75
4.00
s
DETL LOW Time tDET(L)_Green_HF1 Threshold for Green Mode tDET(L)_Green_HF2 at High-Frequency Operation Thermal Shutdown TSHUTDOWN TSTARTUP Shutdown Temperature Hysteresis Startup Temperature
VRP > 1.5V
1.75
1.90
2.05
s
Temperature Rising, VDD=15V Before Startup
140 20 120
Continued on the following page...
C
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 5
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
VDD=20V, TA=25C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Gate Section VZ1 VZ2 VOL1 VOL2 VOH1VOH2 tR1 tR2 tF1 tF2 tPD_HIGH_DETL1 tPD_HIGH_DETL2 tPD_LOW_ DETL1 tPD_LOW_ DETL2 tON_MAX1 tON_MAX2 tINHIBIT_LF1 tINHIBIT_LF2 tINHIBIT_HF1 tINHIBIT_HF2 tBLANKING1 tBLANKING2 KR
Parameter
Gate Output Voltage Maximum (Clamping) Gate Output Voltage LOW Gate Output Voltage HIGH Rising Time Falling Time Propagation Delay to Gate Output HIGH (DETL Trigger) Propagation Delay to Gate Output LOW (DETL Trigger) Maximum On-Time Gate Inhibit Time (from Turn-Off to Next Turn-On) Gate Inhibit Time (from Turn-Off to Next Turn-On) Blanking Time for SR TurnOff Triggered by DETL High (Minimum On-Time) Gate ON-Time Increase Rate Between Two Consecutive Cycles Detection Window for Insufficient Dead Time (from Gate Turn-Off to DETL HIGH) Gate Shrink Time by Insufficienct Dead Time Dead Time by Timing Estimator (70kHz ~ 140kHz, VRP < 1.5V) Dead Time by Timing Estimator (160kHz ~ 240kHz, VRP > 1.5V) DETL HIGH-to-LOW Debounce Time for Gate Turn-on Trigger Gate Shrink by DETL Ringing around Zero DETL Pull-HIGH Time Threshold for Green Mode
Conditions
Min.
Typ.
Max.
Units
VDD=20V VDD=12V; IO=100mA VDD=12V; IO=100mA VDD=12V; CL=6nF; VGATE=2V to 9V VDD=12V; CL=6nF; VGATE=9V to 2V tR: 0V~2V, VDD=12V (DET Floating) tF: 100%~90%, VDD=12V (DET Floating) Trim Maximum On-Time VRP < 1.5V VRP > 1.5V
10
12
14 0.5
V V V
9 30 30 70 50 120 120 70
ns ns ns
120 9.0 1.8 1.25 10.5 2.1 1.45 300 12.0 2.5 1.70
ns s s s ns
tON(n) / tON(n-1) %
140
%
Timing Estimator Section tDW 80 125 150 ns
tSHRINK-DT
RRP=20K, tDETL=5s tDETL=4s, RRP=20K tDETL=6s, RRP=20K tDETL=2.5s, RRP=43K tDETL=3.8s, RRP=43K
1.00 210 570 220 560
1.25 300 720 320 670 150 1.2
1.50 390 870 420 780
s
tDEAD
ns
tDB tSHRINK-RNG tGreen_DH
ns s 30 s
18
24
Continued on the following page...
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1 www.fairchildsemi.com 6
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
VDD=20V, TA=25C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Feedback Increase Threshold for Gate Shrink Gate Shrink by Feedback Detection Gate-Shrink Duration by Feedback Detection Short-Circuit Protection (SCP) Threshold by Feedback Detection Debounce Time for ShortCircuit Protection (SCP) RP Source Current RP Open Protect RP Short Protect RP Open/Short Debounce H/L Frequency Threshold
Conditions
Min.
Typ.
Max.
Units
Feedback Detection (FD) Section V1% V2% tSHRINK-FD tD-SHRINK-FD VDD-VFD.SCP tDB-SCP RP Section IRP VRPO VRPS tRPOS VRPHL 38.5 3.40 0.25 1.6 1.40 41.5 3.65 0.30 2.0 1.46 44.5 3.90 0.35 2.4 1.52 A V V s V [(VDD-VFD)n+1/(VDD-VFD)n] 120 1.4 60 200 12 90 270 16 120 340 20 % s s mV s
Figure 5. tDEAD vs. tDETL RP Curve for LF Mode
Figure 6. tDEAD vs. tDETL RP Curve for HF Mode
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 7
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Function Description
Operation Principle
FAN6208 is a secondary-side synchronous rectifier controller for LLC or LC resonant converters that drive two synchronous rectifier MOSFETs. Figure 7 is the simplified circuit diagram of an LLC converter. The FAN6208 determines SR MOSFET turn-on/off timing by detecting the drain-to-source voltage of each SR MOSFET. The key waveforms for LLC resonant converter for below resonance and above resonance are shown in Figure 8 and Figure 9, respectively.
VIN Secondary-Side Synchronous Rectifiers SR1 IP Lr Lm
DETL1 GATE1 DETL2 GND RP GATE2 VDD
VO
Cr
FD
FAN6208
LLC Resonant Converter
SR2
Figure 7. Simplified Schematic of LLC Converter
Figure 9. Key Waveforms of LLC Resonant Converter for
Above Resonance Operation
Timing Estimator
Figure 10 shows the timing diagram for FAN6208. Once the body diode of SR begins conducting, the drain-tosource voltage drops to zero, which causes DETL pin voltage to drop to zero. FAN6208 turns on the MOSFET after tON-ON-DETL (about 350ns), when voltage on DETL drops below 2V. As depicted in Figure 11, the turn-on delay (after tSR-ON-DETL) is the sum of debounce time (150ns) and propagation delay (200ns). FAN6208 measures the SR conduction duration (tDETL), during which DETL stays lower than 2V, and uses this information to determine the turn-off instant of SR gates of the next switching cycle. The turn-off timing is obtained by subtracting a dead time (tDEAD) from the measured SR conduction duration of the previous switching cycle. The dead time can be programmed using a resistor on the RP pin and the relationship between the dead time and SR conduction duration (tDETL) for different resistor values on RP pin is given in Figure 5. Figure 8. Key Waveforms of LLC Resonant Converter for
Below Resonance Operation
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 8
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
side MOSFETs takes place before the turn-off command of SR is given. To prevent the shoot-through, FAN6208 has gate-shrink functions. Gate shrink occurs under three conditions: (a) When insufficient dead time is detected in the previous switching cycle. When the DETL goes HIGH within 125ns of detection window after SR gate is turned off, the SR gate drive signal in the next switching cycle is reduced by tSHRINK-DT (about 1.25s) to increase the dead time, as shown in Figure 12. Figure 10. SR Gate Timing Diagram
Figure 12. Gate Shrink by Minimum Dead Time Detection Window (b) When the feedback information changes fast. FAN6208 monitors the current through the optocoupler diode by measuring the voltage across the resistor in series with the opto-coupler diode, as depicted in Figure 13. If the feedback current through the opto-coupler diode increases by more than 20% of the feedback current of the previous switching cycle, the SR gate signal is shrunk by tSHRINK-FD (about 1.4s) for tD-SHRINK-FD (about 90s), as shown in Figure 14.
Figure 11. DETL Debounce (Blanking) Time
Gate-Shrink Functions
In normal operation, the turn-off instant is determined by subtracting a dead time (tDEAD) from the measured SR conduction duration of the previous switching cycle, as shown in Figure 10. This allows proper driving timing for SR MOSFETS when the converter is in steady state and the switching frequency does not change much. However, this control method may cause shoot-through of SR MOSFETs when the switching frequency increases fast and switching transition of the primary(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
Figure 13. Typical Application Circuit
www.fairchildsemi.com 9
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Figure 14. Gate Shrink by Feedback Detection (c) When the DETL voltage has ringing around zero. As depicted in Figure 8, the drain voltage of SR has ringing around zero at light-load condition after the switching transition of the primary-side switches. When DETL voltage rises above 2V within 350ns after DETL voltage drops to zero and stays above 2V longer than 150ns, the gate is shrunk by 1.2s (tSHRINK-RNG), as shown in Figure 15.
Figure 16.
RP Pin Operation
To handle abnormal conditions for IC pins, the RP pin also provides open/short protection. When VRP is less than VRPS (0.3V) or VRP is higher than VRPO (3.65V), the protection is triggered. Figure 17 shows the RP pin short protection timing sequence. If VRP < VRPS (0.3V) for longer than tRPOS (2s), FAN6208 is disabled. Figure 18 shows the RP pin open protection timing sequence. If VRP > VRPO (3.65V) for longer than tRPOS (2s), FAN6208 is disabled.
Figure 15. Gate Shrink by DETL Voltage Ringing Around Zero
Figure 17. RP Pin Short Protection
RP Pin Function
The RP pin programs the level of green mode and tDEAD. Figure 16 shows how the mode is selected by the voltage on the RP pin (open protection, short protection, and HF/LF mode). When RRP is less than 36K, FAN6208 operates in low-frequency mode. Green mode is enabled when tDETL is smaller than 3.75s. When RRP is larger than 36K, high-frequency mode is selected and green mode is enabled for tDETL < 1.90s. tDEAD can be also adjusted by a resistor on the RP pin. Figure 5 shows the relationship between tDEAD and tDETL for different RP resistors.
Figure 18. RP Pin Open Protection
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 10
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Green Mode
Switching frequency increases in LLC topology at lightload condition, which increases the power consumption for the SR gate drive. Green mode reduces power loss at light load. FAN6208 has two ways to enable green mode. Green mode is triggered when DETL voltage is pulled LOW for less than 3.75s (LF mode) or 1.90s (HF mode) for seven switching cycles. FAN6208 resumes normal SR gate driving when DETL voltage is pulled LOW for longer than 3.75s (LF mode) or 1.90s (HF mode) for seven switching cycles. When DETL voltage is pulled HIGH for longer than 24s. This occurs when the LLC resonant converter operates in burst mode (skipping mode).
VDD Pin Over-Voltage Protection
Over-voltage conditions are usually caused by an open feedback loop. VDD over-voltage protection prevents damage of SR MOSFET. When the voltage on the VDD pin exceeds 27V, FAN6208 disables gate output.
Internal Over-Temperature Protection
Internal over-temperature protection prevents the SR gate from fault triggering in high temperatures. If the temperature is over 140C, the SR gate is disabled until the temperature drops below 120C.
Short-Circuit Protection
As depicted in Figure 13, FAN6208 monitors the current through the opto-coupler diode by measuring the voltage across the resistor in series with the optocoupler diode. When the output of the power supply is short circuited, the output voltage drops and the cathode of the shunt regulator (KA431) is saturated to HIGH. No current flows through the opto coupler diode. The output short protection is triggered when the voltage between VDD and FD is smaller than 0.3V, as shown in Figure 19.
Figure 19. Output Short Protection by Feedback Detection
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 11
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Typical Performance Characteristics
Figure 20. VTH_ON1 vs. TA
Figure 21. VTH_ON2 vs. TA
Figure 22. VTH_OFF1 vs. TA
Figure 23. VTH_OFF2 vs. TA
Figure 24. IDD_ST vs. TA
Figure 25. IDD_OP1 vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 12
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Typical Performance Characteristics (Continued)
Figure 26. tSR_ON_DETL1 vs. TA
Figure 27. tSR_ON_DETL2 vs. TA
Figure 28. VZ1 vs. TA
Figure 29. VZ2 vs. TA
Figure 30. VDETL1 vs. TA
Figure 31. VDETL2 vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 13
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Typical Performance Characteristics (Continued)
Figure 32. tDW1 vs. TA
Figure 33. tDW2 vs. TA
Figure 34. VSHRINK_DT1 vs. TA
Figure 35. VSHRINK_DT2 vs. TA
Figure 36. IDETL_Source1 vs. TA
Figure 37. IDETL_Source2 vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 14
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Typical Performance Characteristics (Continued)
Figure 38. tDEAD1 (RRP=20k, 6s) vs. TA
Figure 39. tDEAD2 (RRP=20k, 6s) vs. TA
Figure 40. tDEAD1 (RRP=43k, 2.5s) vs. TA
Figure 41. tDEAD2 (RRP=43k, 2.5s) vs. TA
Figure 42. IRP vs. TA
Figure 43. VRPHL vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 15
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Typical Application Circuit (LLC Converter with SR)
Application Fairchild Devices
FAN7621 FAN6208
Input Voltage Range
Output
TV Power
350~400VDC
24V/8A
Figure 44. Application Circuit
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 16
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 45.
8-Lead, SOIC, JEDEC MS-012, .150-Inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1 www.fairchildsemi.com 17
FAN6208 --Secondary-Side Synchronous Rectifier Controller for LLC Topology
(c) 2010 Fairchild Semiconductor Corporation FAN6208 * Rev. 1.0.1
www.fairchildsemi.com 18

▲Up To Search▲

Price & Availability of FAN6208

	To Download FAN6208 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .