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| PCA8576C Universal LCD driver for low multiplex rates Rev. 1 -- 22 July 2010 Product data sheet 1. General description The PCA8576C is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCA8576C is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing and by hardware subaddressing. AEC-Q100 compliant for automotive applications. 2. Features and benefits Single-chip LCD controller and driver 40 segment drives: Up to twenty 7-segment alphanumeric characters Up to ten 14-segment alphanumeric characters Any graphics of up to 160 elements Versatile blinking modes No external components required (even in multiple device applications) Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 12, or 13 Internal LCD bias generation with voltage-follower buffers 40 x 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Wide logic LCD supply range: From 2 V for low-threshold LCDs Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption May be cascaded for large LCD applications (up to 2560 segments possible) No external components Separate or combined LCD and logic supplies Optimized pinning for plane wiring in both and multiple PCA8576C applications Power-saving mode for extremely low power consumption in battery-operated and telephone applications 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 16. NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Package Name PCA8576CH/Q900/1 LQFP64 Description plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 Type number 4. Marking Table 2. Marking codes Marking code PCA8576CQ900 Type number PCA8576CH/Q900/1 5. Block diagram BP0 BP2 BP1 BP3 S0 to S39 40 VDD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY LATCH VLCD LCD BIAS GENERATOR SHIFT REGISTER PCA8576C CLK TIMING SYNC DISPLAY CONTROLLER OSC OSCILLATOR POWERON RESET COMMAND DECODER INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER DATA POINTER BLINKER INPUT BANK SELECTOR DISPLAY RAM 40 x 4 BITS OUTPUT BANK SELECTOR VSS SCL SDA SA0 A0 A1 A2 013aaa273 Fig 1. Block diagram of PCA8576C PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 2 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning 64 S33 63 S32 62 S31 61 S30 60 S29 59 S28 58 S27 57 S26 56 S25 55 S24 54 S23 53 S22 52 S21 51 S20 50 S19 49 S18 n.c. S34 S35 S36 S37 S38 S39 n.c. n.c. 1 2 3 4 5 6 7 8 9 48 n.c. 47 S17 46 S16 45 S15 44 S14 43 S13 42 S12 41 S11 40 S10 39 S9 38 S8 37 S7 36 S6 35 S5 34 S4 33 n.c. PCA8576CH SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16 A1 17 A2 18 SA0 19 VSS 20 VLCD 21 n.c. 22 n.c. 23 n.c. 24 BP0 25 BP2 26 BP1 27 BP3 28 S0 29 S1 30 S2 31 S3 32 013aaa274 Top view. For mechanical details, see Figure 29. Fig 2. Pin configuration for LQFP64 (PCA8576CH/Q900/1) PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 3 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol Pin description Pin LQFP64 (PCA8576CH/Q900/1) SDA SCL SYNC CLK VDD OSC A0 to A2 SA0 VSS VLCD 10 11 12 13 14 15 16 to 18 19 20 21 Type input/output input input/output input/output supply input input input supply supply output I2C-bus serial data input and output I2C-bus serial clock input cascade synchronization input and output external clock input/output supply voltage internal oscillator enable input subaddress inputs I2C-bus address input; bit 0 ground supply voltage LCD supply voltage LCD backplane outputs LCD segment outputs not connected; do not connect and do not use as feed through Description BP0, BP2, 25 to 28 BP1, BP3 S0 to S39 n.c. 2 to 7, 29 to 32, 34 to 47, output 49 to 64 1, 8, 9, 22 to 24, 33, 48 - PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 4 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7. Functional description The PCA8576C is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 3. Example of displays suitable for PCA8576C The possible display configurations of the PCA8576C depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 4. Table 4. Number of Backplanes 4 3 2 1 Icons 160 120 80 40 Digits/Characters 7-segment 20 15 10 5 14-segment 10 7 5 2 Dot matrix/ Elements 160 dots (4 x 40) 120 dots (3 x 40) 80 dots (2 x 40) 40 dots (1 x 40) Selection of possible display configurations PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 5 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates VDD R tr 2CB SDA SCL OSC VDD VLCD 40 segment drives LCD PANEL HOST MICROPROCESSOR/ MICROCONTROLLER PCA8576C 4 backplanes (up to 160 elements) A0 VSS A1 A2 SA0 V SS 013aaa275 Fig 4. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCA8576C. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application. 7.1 Power-On-Reset (POR) At power-on the PCA8576C resets to the following starting conditions: * * * * * * All backplane and segment outputs are set to VDD The selected drive mode is 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset (as defined in Table 8) The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator The full-scale LCD voltage (Voper) is obtained from VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin VLCD. Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three series resistors connected between VDD and VLCD. The center resistor can be switched out of the circuit to provide a 12 bias voltage level for the 1:2 multiplex configuration. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 6 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Table 5. LCD drive mode static Biasing characteristics LCD bias Backplanes Levels configuration 1 2 3 4 4 4 static 1 1 1 1 2 3 3 3 Number of: V off ( RMS ) -----------------------V LCD 0 0.354 0.333 0.333 0.333 V on ( RMS -----------------------) V LCD 1 0.791 0.745 0.638 0.577 V on ( RMS ) D = -----------------------V off ( RMS ) 2.236 2.236 1.915 1.732 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = a 2 + 2a + n ----------------------------2 n x (1 + a) (1) V LCD where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2) V LCD Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ---------------------- = V off ( RMS ) PCA8576C (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1) Rev. 1 -- 22 July 2010 2 (3) (c) NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet 7 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1 1 2 2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with 21 bias is ---------- = 1.528 . 3 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: * 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS ) --------------------* 1:4 multiplex (12 bias): V LCD = ( 4 x 3 ) = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 8 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 5. Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V -VLCD VLCD state 2 0V -VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = VSn+1(t) - VBP0(t). Voff(RMS) = 0 V. Fig 5. Static drive mode waveforms PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 9 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA8576C allows the use of 12 bias or 13 bias (see Figure 6 and Figure 7). Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD Fig 6. Waveforms for the 1:2 multiplex drive mode with 12 bias PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 10 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl747 LCD segments state 1 state 2 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD Vstate2(t) = VSn(t) - VBP1(t) Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:2 multiplex drive mode with 13 bias PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 11 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure 8. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:3 multiplex drive mode with 13 bias PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 12 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 9. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments Sn Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 Sn+3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 9. Waveforms for the 1:4 multiplex mode with 13 bias PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 13 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8576C are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data rate of 100 kHz, fclk should be chosen to be above 125 kHz. 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCA8576C in the system. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. Remark: A clock signal must always be supplied to the device. Removing the clock, freezes the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The timing of the PCA8576C sequences the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCA8576Cs in the system. The timing also generates the LCD frame frequency which is derived as an integer division of the clock frequency (see Table 6). The frame frequency is set by the mode-set command (see Table 9) when an internal clock is used or by the frequency applied to the pin CLK when an external clock is used. Table 6. LCD frame frequencies [1] Frame frequency f clk f fr = -----------2880 f clk f fr = --------480 Nominal frame frequency (Hz) 69 [2] 65 [3] PCA8576C mode Normal-power mode Power-saving mode [1] [2] [3] The possible values for fclk see Table 16. For fclk = 200 kHz. For fclk = 31 kHz. The ratio between the clock frequency and the LCD frame frequency depends on the power mode in which the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power consumption. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 14 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. When a device is unable to process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. 7.8 Shift register The shift register transfers display information from the display RAM to the display register while previous data is displayed. 7.9 Segment outputs The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data residing in the display register. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.10 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. * In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left as an open-circuit. * In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. * In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. * In static drive mode: the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.11 Display RAM The display RAM is a static 40 x 4-bit RAM which stores LCD data. There is a one-to-one correspondence between * the bits in the RAM bitmap and the LCD elements * the RAM columns and the segment outputs * the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 15 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates The display RAM bit map Figure 10 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. display RAM addresses (columns)/segment outputs (S) 0 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 mbe525 1 2 3 4 35 36 37 38 39 The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs; and between the bits in a RAM row and the backplane outputs. Fig 10. Display RAM bit map When display data is transmitted to the PCA8576C, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 11; the RAM filling organization depicted applies equally to other LCD types. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 16 of 44 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 1 -- 22 July 2010 17 of 44 PCA8576C NXP Semiconductors drive mode LCD segments LCD backplanes display RAM filling order columns display RAM address/segment outputs (s) byte1 transmitted display byte Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6 e d f a b g c Sn+1 Sn Sn+7 DP BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n c x x x n+1 b x x x n+2 a x x x n+3 f x x x n+4 g x x x n+5 e x x x n+6 d x x x n+7 DP x x x MSB cba f LSB g e d DP BP0 Sn 1:2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. a f g b columns display RAM address/segment outputs (s) byte1 byte2 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP Sn+1 multiplex Sn+2 Sn+3 e d c BP1 DP Sn+1 1:3 Sn+2 f a b g BP0 Sn n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2c 3x columns display RAM address/segment outputs (s) byte1 byte2 byte3 n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB Universal LCD driver for low multiplex rates multiplex e d c BP1 DP BP2 e Sn 1:4 f a b g columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 BP0 BP2 n rows display RAM 0 a rows/backplane 1c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB egd multiplex e c d PCA8576C BP1 DP Sn+1 001aaj646 x = data bit unchanged. Fig 11. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates The following applies to Figure 11: * In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. * In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. * In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. * In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 of two successive 4-bit RAM words. 7.12 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 10). After this, the data byte is stored starting at the display RAM address indicated by the data pointer (see Figure 11). Once each byte is stored, the data pointer is automatically incremented based on the selected LCD configuration. The contents of the data pointer are incremented as follows: * * * * In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two. If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. 7.13 Sub-address counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Table 11). If the contents of the subaddress counter and the hardware subaddress do not match then data storage is blocked but the data pointer will be incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA8576C occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 18 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.14 Bank selector 7.14.1 Output bank selector The output bank selector (see Table 12), selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. * In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially by the contents of row 1, row 2, and then row 3. * In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially. * In 1:2 multiplex mode: rows 0 and 1 are selected. * In the static mode: row 0 is selected. The PCA8576C includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14.2 Input bank selector The input bank selector (see Table 12) loads display data into the display RAM based on the selected LCD drive configuration. Using the bank-select command, display data can be loaded in row 2 into static drive mode or in rows 2 and 3 into 1:2 multiplex drive mode. The input bank selector functions independently of the output bank selector. 7.15 Blinker The display blinking capabilities of the PCA8576C are very versatile. The whole display can be blinked at frequencies selected by the blink-select command. The blinking frequencies are integer fractions of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7). Table 7. Blink frequencies Normal-power mode ratio f clk f blink = --------------92160 f clk f blink = ------------------184320 f clk f blink = ------------------368640 Power-saving mode ratio f clk f blink = --------------15360 f clk f blink = --------------30720 f clk f blink = --------------61440 Blink frequency blinking off 2 Hz Blinking mode off 1 2 1 Hz 3 0.5 Hz An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the blink-select command (see Table 13). PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 19 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blink frequency, this can be done using the mode-set command to set and reset the display enable bit E at the required rate (see Table 9). 7.16 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 12. SDA SCL data line stable; data valid change of data allowed mba607 Fig 12. Bit transfer 7.16.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 13. SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 13. Definition of START and STOP conditions PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 20 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.16.3 System configuration A device generating a message is a transmitter and a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is illustrated in Figure 14. MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 14. System configuration 7.16.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. * A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. * A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). * A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 15. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 21 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 15. Acknowledgement of the I2C-bus 7.16.5 PCA8576C I2C-bus controller The PCA8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA8576C are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme so that no two devices with a common I2C-bus slave address have the same hardware subaddress. In the power-saving mode it is possible that the PCA8576C is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCA8576C forces the SCL line LOW until its internal operations are completed. This is known as the clock synchronization feature of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. 7.16.6 Input filter To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.17 I2C-bus protocol Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCA8576C. The least significant bit of the slave address that a PCA8576C responds to is defined by the level tied at its input SA0. Therefore, two types of PCA8576C can be distinguished on the same I2C-bus which allows: * Up to 16 PCA8576Cs on the same I2C-bus for very large LCD applications. * The use of two types of LCD multiplex on the same I2C-bus. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 22 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCA8576C slave addresses available. All PCA8576Cs with the corresponding SA0 level acknowledge in parallel with the slave address but all PCA8576Cs with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, one or more command bytes follow which define the status of the addressed PCA8576Cs. The last command byte is tagged with a cleared most significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCA8576Cs on the bus. After the last command byte, a series of display data bytes may follow. These display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCA8576C device. The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA8576C. After the last display byte, the I2C-bus master issues a STOP condition (P). R/W slave address S 0 1 1 1 0 0A 0AC 0 1 byte acknowledge by all addressed PCA8576Cs acknowledge by A0, A1 and A2 selected PCA8576C only S COMMAND A DISPLAY DATA A P n 1 byte(s) n 0 byte(s) update data pointers and if necessary, subaddress counter 013aaa276 Fig 16. I2C-bus protocol 7.18 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Figure 17. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. MSB C REST OF OPCODE LSB msa833 (1) C = 0; last command (2) C = 1; commands continue Fig 17. General format of the command byte The five commands available to the PCA8576C are defined in Table 8. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 23 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Definition of PCA8576C commands Operation Code 7 C C C C C 6 1 0 1 1 1 5 0 P[5:0] 1 1 1 0 1 1 0 1 0 A[2:0] 0 AB I O BF[1:0] 4 LP 3 E 2 B 1 M[1:0] 0 Section 7.18.1 Section 7.18.2 Section 7.18.3 Section 7.18.4 Section 7.18.5 Reference Table 8. Command Bit mode-set load-data-pointer device-select bank-select blink-select 7.18.1 Mode-set command Table 9. Bit 7 6 to 5 4 Mode-set command bit description Symbol C LP 0 1 3 E 0 1 2 B 0 1 1 to 0 M[1:0] 01 10 11 00 [1] [2] Value 0, 1 10 Description see Figure 17 fixed value power dissipation (see Table 6) normal-power mode power-saving mode display status disabled[1] enabled LCD bias configuration[2] 1 1 3 2 bias bias LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2 1:4 multiplex; BP0, BP1, BP2, BP3 The possibility to disable the display allows implementation of blinking under external control. Bit B is not applicable for the static LCD drive mode. 7.18.2 Load-data-pointer command Table 10. Bit 7 6 5 to 0 Load-data-pointer command bit description Symbol C P[5:0] Value 0, 1 0 000000 to 100111 Description see Figure 17 fixed value 6 bit binary value, 0 to 39; transferred to the data pointer to define one of forty display RAM addresses PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 24 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 7.18.3 Device-select command Table 11. Bit 7 6 to 4 3 to 0 Device-select command bit description Symbol C A[2:0] Value 0, 1 1100 000 to 111 Description see Figure 17 fixed value 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses 7.18.4 Bank-select command Table 12. Bit 7 6 to 2 1 Bank-select command bit description Symbol C I 0 1 0 O 0 1 [1] Value 0, 1 11110 Description Static see Figure 17 fixed value input bank selection; storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex[1] output bank selection; retrieval of LCD display data The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. 7.18.5 Blink-select command Table 13. Bit 7 6 to 3 2 Blink-select command bit description Symbol C AB 0 1 1 to 0 BF[1:0] 00 01 10 11 [1] [2] Value 0, 1 1110 Description see Figure 17 fixed value blink mode selection normal blinking[1] alternate RAM bank blinking[2] blink frequency selection off 1 2 3 Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.19 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA8576C and coordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 25 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 8. Internal circuitry VLCD VSS SDA, SCL CLK, OSC, A0 to A2, SA0, SYNC VDD BP0 to BP3, S0 to S39 013aaa109 Fig 18. Device protection diagram PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 26 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VLCD VI supply voltage LCD supply voltage input voltage [1] Conditions Min -0.5 Max +8.0 +8.0 Unit V V V VDD - 8.0 VDD -0.5 on each of the pins SCL, SDA, CLK, SYNC, SA0, OSC and A0 to A2 on each of the pins S0 to S39 and BP0 to BP3 [1] VO II IO IDD ISS IDD(LCD) Ptot Po VESD output voltage input current output current supply current ground supply current LCD supply current total power dissipation output power electrostatic discharge voltage -0.5 -20 -25 -50 -50 -50 - +8.0 +20 +25 +50 +50 +50 400 100 4000 200 500 1000 150 +150 +85 V mA mA mA mA mA mW mW V V V V mA C C HBM MM CDM all pins corner pins [2] [3] [4] - Ilu Tstg Tamb [1] [2] [3] [4] [5] [6] latch-up current storage temperature ambient temperature operating device [5] [6] -65 -40 Values with respect to VDD. Pass level; Human Body Model (HBM), according to Ref. 5 "JESD22-A114". Pass level; Machine Model (MM), according to Ref. 6 "JESD22-A115". Pass level; Charged-Device Model (CDM), according to Ref. 7 "JESD22-C101". Pass level; latch-up testing according to Ref. 8 "JESD78" at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see Ref. 9 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 27 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 10. Static characteristics Table 15. Static characteristics VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD - 6.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD IDD IDD(lp) Logic VIL VIH VOL VOH IOL LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current on pins CLK, SYNC, OSC, A0 to A2 and SA0 on pins CLK, SYNC, OSC, A0 to A2 and SA0 IOL = 0 mA IOH = 0 mA output sink current; VOL = 1.0 V; VDD = 5.0 V; on pins CLK and SYNC VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 VI = VDD VI = 1.0 V; VDD = 5.0 V; on pins A0 to A2 and OSC [3] [4] Parameter supply voltage LCD supply voltage supply current: low-power mode supply current Conditions Min 2.0 [1] Typ - Max 6.0 120 60 Unit V A A VDD - 6.0 - VDD - 2.0 V fclk = 200 kHz VDD = 3.5 V; VLCD = 0 V; fclk = 35 kHz; A0, A1 and A2 connected to VSS [2] VSS 0.7VDD 1 - 0.3VDD VDD 0.05 - V V V V mA VDD - 0.05 - IL IL(OSC) Ipd RSYNC_N VPOR CI I2C-bus; VIL VIH IOH(CLK) IOL(SDA) leakage current leakage current on pin OSC pull-down current SYNC resistance power-on reset voltage input capacitance pins SDA and SCL LOW-level input voltage HIGH-level input voltage HIGH-level output current on pin CLK LOW-level output current on pin SDA -1 -1 15 20 VSS 0.7VDD 50 50 1.0 - +1 +1 150 150 1.6 7 0.3VDD 6.0 - A A A k V pF V V mA mA output source current; VOH = 4.0 V; VDD = 5.0 V output sink current; VOL = 0.4 V; VDD = 5.0 V 1 3 PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 28 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Table 15. Static characteristics ...continued VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD - 6.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VBP VS RBP RS [1] [2] [3] [4] [5] Parameter voltage on pin BP voltage on pin S resistance on pin BP resistance on pin S Conditions Cbpl = 35 nF; on pins BP0 to BP3 Csgm = 5 nF; on pins S0 to S39 VLCD = VDD - 5 V; on pins BP0 to BP3 VLCD = VDD - 5 V; on pins S0 to S39 [5] [5] Min -20 -20 - Typ - Max +20 +20 5 7.5 Unit mV mV k k LCD outputs VLCD VDD - 3 V for 13 bias. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. Resets all logic when VDD < VPOR. Periodically sampled, not 100 % tested. Outputs measured one at a time. 10.1 Typical supply current characteristics mbe530 mbe529 50 ISS (A) 40 normal mode 50 -IDD(LCD) (A) 40 30 30 20 power-saving mode 10 20 10 0 0 100 ffr (Hz) 200 0 0 100 ffr (Hz) 200 VDD = 5 V; VLCD = 0 V; Tamb = 25 C VDD = 5 V; VLCD = 0 V; Tamb = 25 C Fig 19. ISS as a function of ffr Fig 20. -IDD(LCD) as a function of ffr PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 29 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 50 ISS (A) 40 normal mode fclk = 200 kHz mbe528 50 -IDD(LCD) (A) 40 85 C 30 25 C mbe527 30 20 20 10 power-saving mode fclk = 35 kHz -40 C 10 0 0 5 VDD (V) 10 0 0 5 VDD (V) 10 VLCD = 0 V; external clock; Tamb = 25 C VLCD = 0 V; external clock; Tamb = 25 C Fig 21. ISS as a function of VDD Fig 22. -IDD(LCD) as a function of VDD 10.2 Typical LCD output characteristics mbe532 mbe526 10 RO(max) (k) 2.5 RO(max) (k) RS RS 2.0 RBP 1 1.5 RBP 1.0 0.5 10-1 0 3 VDD (V) 6 0 -40 0 40 80 120 Tamb (C) VLCD = 0 V; Tamb = 25 C VDD = 5 V; VLCD = 0 V Fig 23. RO(max) as a function of VDD Fig 24. RO(max) as a function of Tamb PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 30 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 11. Dynamic characteristics Table 16. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol fclk Parameter clock frequency Conditions normal-power mode; VDD = 5 V power-saving mode; VDD = 3 V tclk(H) tclk(L) tSYNC_NL tPD(drv) tBUF tHD;STA tSU;STA tLOW tHIGH tr tf Cb tSU;DAT tHD;DAT tSU;STO [1] [2] [1] Min 125 21 1 1 1 Typ 200 31 - Max 315 48 400 30 1 0.3 400 - Unit kHz kHz s s ns s s s s s s s s s pF ns ns s Timing characteristics: driver timing waveforms (see Figure 25) clock HIGH time clock LOW time SYNC LOW time driver propagation delay bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line data set-up time data hold time set-up time for STOP condition VLCD = 5 V [2] tPD(SYNC_N) SYNC propagation delay 4.7 4.0 4.7 4.7 4.0 250 0 4.0 Timing characteristics: I2C-bus (see Figure 26) fclk < 125 kHz, I2C-bus maximum transmission speed is derated. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 31 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 1/fCLK tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S39 (VDD = 5 V) 0.5 V tPD(drv) mce424 tPD(SYNC_N) Fig 25. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 26. I2C-bus timing waveforms PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 32 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 12. Application information 12.1 Cascaded operation In large display configurations, up to 16 PCA8576Cs can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 17. Cluster 1 Addressing cascaded PCA8576C Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Cascaded PCA8576Cs are synchronized. They can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA8576Cs of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 27). PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 33 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates VDD SDA SCL SYNC CLK OSC VLCD 40 segment drives LCD PANEL PCA8576C BP0 to BP3 (open-circuit) (up to 2560 elements) A0 VLCD VDD R tr 2Cb SDA SCL SYNC CLK OSC A0 A1 A1 A2 SAO VSS VDD VLCD 40 segment drives HOST MICROPROCESSOR/ MICROCONTROLLER PCA8576C 4 backplanes BP0 to BP3 VSS A2 SA0 VSS 013aaa277 Fig 27. Cascaded PCA8576C configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCA8576Cs. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the defining a multiplex mode when PCA8576Cs with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCA8576C asserts the SYNC line and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCA8576C to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCA8576C are shown in Figure 28. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 34 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse can be countered by an external pull-up resistor. Fig 28. Synchronization of the cascade for the various PCA8576C drive modes PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 35 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 29. Package outline SOT314-2 (LQFP64) of PCA8576CH PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 36 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 37 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 15.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 Table 18. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 19. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 38 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 39 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 16. Abbreviations Table 20. Acronym AEC CDM DC HBM I2C IC LCD LSB MM MOS MSB MSL PCB POR RC RAM RMS SCL SDA SMD Abbreviations Description Automotive Electronics Council Charged-Device Model Direct Current Human Body Model Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display Least Significant Bit Machine Model Metal-Oxide Semiconductor Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Resistance-Capacitance Random Access Memory Root Mean Square Serial Clock Line Serial DAta line Surface-Mount Device PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 40 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 17. References [1] [2] [3] [4] [5] [6] [7] [8] [9] AN10365 -- Surface mount reflow soldering description IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD22-C101 -- Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components JESD78 -- IC Latch-Up Test NX3-00092 -- NXP store and transport requirements [10] SNV-FA-01-02 -- Marking Formats Integrated Circuits [11] UM10204 -- I2C-bus specification and user manual 18. Revision history Table 21. Revision history Release date 20100722 Data sheet status Product data sheet Change notice Supersedes Document ID PCA8576C v.1 PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 41 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 42 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA8576C All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 -- 22 July 2010 43 of 44 NXP Semiconductors PCA8576C Universal LCD driver for low multiplex rates 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.14.1 7.14.2 7.15 7.16 7.16.1 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.17 7.18 7.18.1 7.18.2 7.18.3 7.18.4 7.18.5 7.19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Power-On-Reset (POR) . . . . . . . . . . . . . . . . . . 6 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Display register . . . . . . . . . . . . . . . . . . . . . . . . 15 Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sub-address counter . . . . . . . . . . . . . . . . . . . 18 Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output bank selector . . . . . . . . . . . . . . . . . . . 19 Input bank selector . . . . . . . . . . . . . . . . . . . . . 19 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Characteristics of the I2C-bus. . . . . . . . . . . . . 20 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 START and STOP conditions . . . . . . . . . . . . . 20 System configuration . . . . . . . . . . . . . . . . . . . 21 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCA8576C I2C-bus controller. . . . . . . . . . . . . 22 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Command decoder . . . . . . . . . . . . . . . . . . . . . 23 Mode-set command . . . . . . . . . . . . . . . . . . . . 24 Load-data-pointer command. . . . . . . . . . . . . . 24 Device-select command . . . . . . . . . . . . . . . . . 25 Bank-select command . . . . . . . . . . . . . . . . . . 25 Blink-select command . . . . . . . . . . . . . . . . . . 25 Display controller . . . . . . . . . . . . . . . . . . . . . . 25 8 9 10 10.1 10.2 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Typical supply current characteristics . . . . . . Typical LCD output characteristics. . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Cascaded operation. . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 28 29 30 31 33 33 36 37 37 37 37 38 38 40 41 41 42 42 42 42 43 43 44 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 July 2010 Document identifier: PCA8576C |
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