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Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Datasheet
January 2007
Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--
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Leg al Li nes and Dis clai mers
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 2
January 2007 Order Number: 315876-002
Contents--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Contents
1.0 Introduction .............................................................................................................. 6 1.1 Terminology ....................................................................................................... 7 1.2 References .........................................................................................................8 1.3 State of Data ...................................................................................................... 9 Low Power Features ................................................................................................ 10 2.1 Clock Control and Low Power States .................................................................... 10 2.2 Enhanced Intel(R) SpeedStep(R) Technology (EIST) ................................................... 13 2.3 Extended Halt State (C1E) .................................................................................. 13 Electrical Specifications ........................................................................................... 15 3.1 Front Side Bus and GTLREF ................................................................................ 15 3.2 Power and Ground Pins ...................................................................................... 15 3.3 Decoupling Guidelines ........................................................................................ 15 3.4 Voltage Identification and Power Sequencing ........................................................ 16 3.5 Catastrophic Thermal Protection .......................................................................... 18 3.6 Signal Terminations and Unused Pins ................................................................... 18 3.7 FSB Frequency Select Signals (BSEL[2:0]) ............................................................ 18 3.8 FSB Signal Groups ............................................................................................. 19 3.9 CMOS Signals ................................................................................................... 20 3.10 Maximum Ratings.............................................................................................. 20 3.11 Processor DC Specifications ................................................................................ 20 Package Mechanical Specifications and Pin Information .......................................... 25 4.1 Package Mechanical Specifications ....................................................................... 25 4.2 Processor Pin-Out and Pin List............................................................................. 28 Thermal Specifications and Design Considerations .................................................. 61 5.1 Thermal Specifications ....................................................................................... 62
2.0
3.0
4.0
5.0
Figures
1 2 3 4 5 6 7 Package-Level Low Power States ................................................................................ 10 Core Low Power States ............................................................................................. 11 Active VCC and ICC Load Line for Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz.............. 22 Micro-FCPGA Package Top and Bottom Views ............................................................... 25 Micro-FCPGA Processor Package Drawing (Sheet 1) ...................................................... 26 Micro-FCPGA Processor Package Drawing (Sheet 2) ...................................................... 27 The Coordinates of the Processor Pins as Viewed From the Top of the Package ................. 29
Tables
1 2 3 4 5 6 7 8 9 10 11 Terminology .............................................................................................................. 7 References ................................................................................................................ 8 Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz VID Map ................................................ 16 BSEL[2:0] Encoding for BCLK Frequency ..................................................................... 18 FSB Pin Groups ........................................................................................................ 19 Processor DC Absolute Maximum Ratings .................................................................... 20 Voltage and Current Specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz.. 21 AGTL+ Signal Group DC Specifications ........................................................................ 22 CMOS Signal Group DC Specifications ......................................................................... 23 Open Drain Signal Group DC Specifications.................................................................. 24 Signal Description .................................................................................................... 30
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Contents
12 13 14 15 16 17 18 19
Quad-Pumped Signal Groups......................................................................................32 DINV[3:0]# Assignment To Data Bus ..........................................................................32 Alphabetical Signal Listing .........................................................................................37 Alphabetical Pin Listing..............................................................................................49 Power Specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz......................61 Thermal Diode Interface ............................................................................................63 Thermal "Diode" Parameters using Diode Mode.............................................................63 Thermal "Diode" ntrim and Diode Correction Toffset .......................................................64
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 4
January 2007 Order Number: 315876-002
Revision History--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Revision History
Date November 2006 January 2007
Revision 001 002 Initial public release.
Description
Added information for Intel(R) Celeron(R) Processor 1.83 GHz
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 5
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Introduction
1.0
Introduction
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz is a single-core, low-power processor designed for embedded, communications infrastructure and storage applications. The processor is manufactured on Intel's advanced 65 nanometer process technology with copper interconnect. The following list provides some of the key features on this processor: * Single core * Uniprocessor support only * 36-bit physical addressing * Address, Data, and Response Parity on the Front Side Bus (FSB) * Supports Intel Architecture with Dynamic Execution * On-die, 32 kB Level 1 instruction cache and 32 kB write-back data cache * On-die, 1 MB, ECC protected, Level 2 cache with Advanced Transfer Cache Architecture * Data Prefetch Logic * Streaming SIMD Extensions 2 (SSE2) and Streaming Single Instruction Multiple Data (SIMD) Extensions 3 (SSE3) * 667 MT/s (megatransfers/second), Source-Synchronous FSB * Digital Thermal Sensor (DTS) * Intel Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2) * Micro-FCPGA packaging technologies * Execute Disable Bit support for enhanced security The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz maintains support for MMXTM Technology and Streaming SIMD instructions and full compatibility with IA32 software. The on-die, 32 kB Level 1 instruction and data caches and the 1 MB Level 2 cache with Advanced Transfer Cache Architecture enable performance improvement over existing low power processors. The processor's Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache request occurs, resulting in reduced bus cycle penalties and improved performance. The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz includes the Data Cache Unit Streamer, which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, Write Order Buffer depth is enhanced to help with write-back latency performance. In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions, which further extend the capabilities of Intel processor technology. These new instructions are called Streaming SIMD Extensions 3 (SSE3). These new instructions enhance the performance of optimized applications such as video, image processing and media compression technology. 3D graphics and other video intense applications have the opportunity to take advantage of these new instructions as platforms with the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz and SSE3 become available.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 6
January 2007 Order Number: 315876-002
Introduction--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz's 667 MHz front side bus (FSB) utilizes a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 5.33 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor also features the Auto Halt low power state (Extended Halt State - C1E). Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package technology. The Micro-FCPGA package plugs into a 478-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA478 socket. The processor supports the Execute Disable Bit capability. This feature combined with a support operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Note: The term AGTL+ is used to refer to Assisted GTL+ signaling technology on the processor.
1.1
Table 1.
Terminology
Terminology (Sheet 1 of 2)
Term Definition A "#" symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a non-maskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the "#" symbol implies that the signal is inverted. For example, D[3:0] = "HLHL" refers to a hex `A', and D[3:0]# = "LHLH" also refers to a hex "A" (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on the processor The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. A reference voltage level used on the system bus to determine the logical state of a signal. Megatransfers/second The maximum voltage observed for a signal at the device pad, measured with respect to the buffer reference voltage. The electrical contact point of a semiconductor die to the package substrate. A pad is only observable in simulations. A single package that contains one complete execution core
#
AGTL+
Front Side Bus (FSB)
GTLREF MT/s Overshoot Pad Processor
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Introduction
Table 1.
Terminology (Sheet 2 of 2)
Term Definition The voltage to which a signal transitions to just after reaching its maximum absolute value. Ringback may be caused by reflections, driver oscillations, or other transmission line phenomena. The minimum voltage extending below VSS observed for a signal at the device pad. Voltage Regulator-Down for the processor that supplies the required voltage and current to a single processor.
Ringback Undershoot VRD
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document.
Table 2.
References
Document Dual-Core Intel(R) Xeon(R) Processor LV and ULV Specification Update Order Number1 http://www.intel.com/ design/intarch/ specupdt/311392.htm ftp:// download.intel.com/ design/chipsets/ datashts/ 30300602.pdf http:// developer.intel.com/ design/intarch/ datashts/300641.htm http:// developer.intel.com/ design/intarch/ designgd/311395.htm http:// developer.intel.com/ design/intarch/ designgd/315745.pdf http:// developer.intel.com/ design/pentium4/ manuals/ index_new.htm 253665 253666 253667 253668 253669 http://www.intel.com/ support/processors/sb/ cs-009861.htm
Intel E7520 Memory Controller Hub (MCH) Datasheet
(R)
Intel(R) 6300ESB I/O Controller Datasheet
Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Thermal Design Guideline for Embedded Applications
Intel
(R)
64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture Volume 2A/2B: Instruction Set Reference Volume 3A/3B: System Programming Guide
Intel(R) Processor Identification and CPUID Instruction application note (AP-485) 1. Order numbers are subject to change
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 8
January 2007 Order Number: 315876-002
Introduction--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
1.3
State of Data
The data contained within this document represents the most accurate information available by the publication date.
Note:
All references to the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz in this document apply to the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz only, unless otherwise specified.
January 2007 Order Number: 315876-002
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Low Power Features
2.0
2.1
Low Power Features
Clock Control and Low Power States
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz supports the C1/AutoHALT, C1/ MWAIT, Stop Grant and Sleep states for optimal power management. C1/AutoHALT and C1/MWAIT are core-level low power states only, they do not have package-level behavior. Refer to Figure 1 for a visual representation of package level low-power states for a Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz. The single core Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz can enter the C1/AutoHALT/MWAIT at any time. Refer to Figure 2 for a visual representation of the core low-power states for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz. Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz implements two software interfaces for requesting low power states: the I/O mapped ACPI P_BLK register block and the Cstate extension to the MWAIT instruction. Either interface can be used at any time. The processor core presents an independent low power state request interface (ACPI P_BLK or MWAIT). Requests from the software running on the core puts into core-level low power state. The processor has logic for coordinating low power state requests from the processor core. This logic puts the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz into a package-level low-power state based on the highest core low power state, as desired. If the core encounters a break event while STPCLK# is asserted, it returns to C0 state by asserting the PBE# output signal. PBE# assertion signals to system logic that the processor needs to return to the Normal package-level state. This allows that core to return to the C0 state.
Figure 1.
Package-Level Low Power States
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 10
January 2007 Order Number: 315876-002
Low Power Features--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Figure 2.
Core Low Power States
STPCLK# asserted
Stop Grant
STPCLK# de-asserted
STPCLK# de-asserted
STPCLK# asserted
C1/ MWAIT
STPCLK# asserted Core state break or MONITOR STPCLK# de-asserted HLT instruction
C1/Auto Halt
MWAIT(C1) Halt break
C0
halt break = A20M#transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR MONITOR event) AND STPCLK# high (not asserted)
2.1.1
2.1.1.1
Core Low Power States
C0 State - Normal State
This is the normal operating state for the processor.
2.1.1.2
C1/AutoHALT Powerdown State
AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor transitions to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the system bus. RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state. While in AutoHALT Power Down state, the processor continues to processes system bus snoops.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Low Power Features
2.1.1.3
C1/MWAIT Powerdown State
MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide for more information.
2.1.2
Package Low Power States
The following sections describe all package level low power states for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz.
2.1.2.1
Normal State
This is the normal operating state for the processor. Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz enters the Normal state when its core is in the Normal, AutoHALT, or MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz, the processor core must be in the Stop Grant state before the deassertion of STPCLK#. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched and can be serviced by software upon exit from the Stop Grant state. RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant state. A transition back to the Normal state occurs with the de-assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should only be deasserted one or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the system bus A transition to the Sleep state occurs with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] is latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event is recognized upon return to the Normal state. While in Stop-Grant state, the processor processes snoops on the system bus and it latches interrupts delivered on the system bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear still causes assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 12
January 2007 Order Number: 315876-002
Low Power Features--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
2.1.2.3
Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state. During a snoop or interrupt transaction, the processor enters the Stop Grant Snoop state. The processor stays in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor returns to the Stop-Grant state.
2.1.2.4
Sleep State
The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor enters the Sleep state upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK period. The SLP# pin should only be asserted when the processor is in the Stop Grant state. For the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz, the SLP# pin may only be asserted the processor core is in the StopGrant state. SLP# assertions while the processor is not in the Stop-Grant state are out of specification and may results in illegal operation. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state results in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor resets itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. When the processor is in Sleep state, it does not respond to interrupts or snoop transactions.
2.2
Enhanced Intel(R) SpeedStep(R) Technology (EIST)
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz does not support this feature.
2.3
Extended Halt State (C1E)
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Extended Halt State (C1E) enables significant power savings. Extended HALT state is a low power state entered when the processor core has executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS. When the processor core executes the HALT instruction, the core is halted. The Extended HALT state is a lower power state than the HALT state or Stop Grant state.
Note:
The Extended HALT (C1E) state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. The processor automatically transitions to a lower core frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Low Power Features
is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus to core frequency ratio and then transition to the lower voltage (VID). While in the Extended HALT(C1E) state, the processor processes bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it first transitions the VID to the original value and then changes the bus to core frequency ratio back to the original value.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 14
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Electrical Specifications--Intel (R) Celeron(R) Processor 1.66 GHz/1.83 GHz
3.0
3.1
Electrical Specifications
Front Side Bus and GTLREF
Most Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz FSB signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz AGTL+ signals is VCCP= 1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (VCCP). The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system.
3.2
Power and Ground Pins
For clean, on-chip power distribution, the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce IR drop. The processor VCC pins must be supplied with the voltage determined by the VID (Voltage ID) pins.
3.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations or reduced lifetime of the component.
3.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Electrical Specifications
3.3.2
FSB AGTL+ Decoupling
The processor integrates signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation.
3.3.3
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[01:00] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz core frequency is a multiple of the BCLK[01:00] frequency. The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz bus ratio multiplier is set at its default ratio at manufacturing. The processor uses a differential clocking implementation.
3.4
Voltage Identification and Power Sequencing
The VID specification for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz is defined by the Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478. The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz are CMOS outputs driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding to the state of VID[5:0]. A `1' in this refers to a high-voltage level and a 0 refers to low-voltage level. For more details about VR design to support the Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz power supply requirements, please refer to the Embedded Voltage RegulatorDown (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478. Power source characteristics must be stable whenever the supply to the voltage regulator is stable.
Table 3.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz VID Map (Sheet 1 of 3)
VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) OFF 1.6000 1.5875 1.5750 1.5625 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 16
January 2007 Order Number: 315876-002
Electrical Specifications--Intel (R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Table 3.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz VID Map (Sheet 2 of 3)
VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 17
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Electrical Specifications
Table 3.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz VID Map (Sheet 3 of 3)
VID5 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 VCC (V) 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250
3.5
Catastrophic Thermal Protection
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of approximately 125 C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor.
3.6
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Table 15 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS ). Unused outputs can be left unconnected.
Note:
The TEST1 and TEST2 pins have unique signal termination requirements. It is mandatory that the TEST2 pin have a 51 +/-5% pull down resistor to VSS. Please refer to Table 11 for details.
3.7
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). The BSEL encoding for BCLK[1:0] is shown in Table 4.
Table 4.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2] L H BSEL[1] H BSEL[0] BCLK frequency 166 MHz RESERVED
All other combinations
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 18
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Electrical Specifications--Intel (R) Celeron(R) Processor 1.66 GHz/1.83 GHz
3.8
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 5 identifies which signals are common clock, source synchronous, and asynchronous.
Table 5.
FSB Pin Groups
Signal Group AGTL+ Common Clock Input Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, PREQ#, RESET#, RS[2:0]#, RSP#, TRDY# ADS#, AP[1:0]#,BINIT#, BNR#, BPM[3:0]#3, BR[0]#, DBSY#, DP[3:0], DRDY#, HIT#, HITM#, LOCK#, MCERR#, PRDY#3
AGTL+ Common Clock I/O
Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]# D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# AGTL+ Strobes CMOS Input Open Drain Output CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock
Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/ NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP#, PROCHOT# VID[5:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, ODTEN, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE
Notes: 1. Refer to Chapter 4.0 for signal descriptions and termination requirements. 2. BPM[2:1]# and PRDY# are AGTL+ output only signals.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 19
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Electrical Specifications
3.9
CMOS Signals
CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.11 for the DC for the CMOS signal groups.
3.10
Maximum Ratings
Table 6 lists the processor's maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from Electro-Static Discharge (ESD), one should always take precautions to avoid high static voltages of electric fields.
Table 6.
Processor DC Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS CMOS buffer DC input voltage with respect to VSS Min -40 -0.3 -0.1 -0.1 Max 85 1.6 1.6 1.6 Unit C V V V Notes 2 1 1, 2 1, 2
Notes: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long term reliability of the device. For functional operation, please refer to the processor case temperature specifications.
3.11
Note:
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 8. DC specifications for the CMOS group are listed in Table 9. Table 7 through Table 10 list the DC specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on a particular processor. Active mode load line specifications apply in all states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz are at Tjunction = 100 C. Care should be taken to read all notes associated with each parameter. The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz does not support Enhanced Intel SpeedStep(R) Technology (EIST), therefore HFM and LFM transitions are not supported.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 20
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Electrical Specifications--Intel (R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Table 7.
Voltage and Current Specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Symbol VCC VCC,BOOT VCCP VCCA ICCDES ICC IAH, ISGNT ISLP dICC/DT ICCA ICCP Parameter VCC CPU Core Voltage Default V CC Voltage for initial power up AGTL+ Termination Voltage PLL supply voltage ICC for Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Recommended Design Target ICC for Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz ICC Auto-Halt & Stop-Grant ISLP VCC power supply current slew rate ICC for VCCA supply ICC for VCCP supply before VCC stable ICC for VCCP supply after VCC stable 0.997 1.425 Min 1.1125 1.1 1.05 1.5 1.102 1.575 36 Typ Max 1.275 Unit V V V V A Notes 1, 2 2, 7, 9 2 2 5
34 23.2 23.2 600 120 6.0 2.5
A A A A/us mA A
3,11 3,4 3,4 6, 8
10
Notes: 1. These are VID values. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings. Actual voltage supplied to the processor should be as specified in the load lines in Figure 3. Adherence to load line specifications is required to ensure reliable processor operation. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or Extended Halt State). 2. The voltage specifications are assumed to be measured across VCCSENSE and V SSSENSE pins at socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-Mohm minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100 C TJ. 4. Specified at the VID voltage. 5. The ICCDES (max) specification comprehends only Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz HFM frequencies. Platforms should be designed to this specification. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC . Not 100% tested. 7. Refer to Figure 3 for a waveform illustration of this parameter. 8. Measured at the bulk capacitors on the motherboard. 9. VCC, boot tolerance is shown in Figure 3. 10. ICCP specification refers to the processor package on the front side bus. 11. Specified at the nominal voltage based on the loadline slope.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 21
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Electrical Specifications
Figure 3.
Active VCC and ICC Load Line for Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
V CC [V]
Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required.
V CC max V CC, DC max VCC nom V CC, DC min V CC min
10mV= RIPPLE
+/-VCC nom * 1.5% = VR St. Pt. Error
See Note
0
Note:
.
ICC [A]
ICC max
Vcc > 0.8250V (VID 111111)
Table 8.
AGTL+ Signal Group DC Specifications (Sheet 1 of 2)
Symbol VCCP GTLREF Parameter I/O Voltage Reference Voltage Min 1.00 2/3 VCCP -2% Typ 1.05 2/3 VCCP Max 1.10 2/3 VCCP +2% Unit V V 6 Notes
1
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified with on die RTT and RON are turned off. 9. Cpad includes die capacitance only. No package parasitics are included. 10. RTT for PREQ# is between 1.5k and 6.0k
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Electrical Specifications--Intel (R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Table 8.
AGTL+ Signal Group DC Specifications (Sheet 2 of 2)
VIH VIL VOH RTT RON ILI Cpad Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Buffer On Resistance Input Leakage Current Pad Capacitance 1.8 2.3 GTLREF+100 -100 VCCP - 100 45 22.3 50 25.5 VCCP 0 VCCP+100 GTLREF-100 VCCP 55 28.7 100 2.75 mV mV mV 3,6 2,4 6 7,10 5 8 9
W A pF
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified with on die RTT and RON are turned off. 9. Cpad includes die capacitance only. No package parasitics are included. 10. RTT for PREQ# is between 1.5k and 6.0k
.
Table 9.
CMOS Signal Group DC Specifications
Symbol VCCP VIL VIH VOL VOH IOL IOH ILI Cpad1 Cpad2 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Parameter I/O Voltage Input Low Voltage CMOS Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Leakage Current Pad Capacitance Pad Capacitance for CMOS Input 1.8 0.95 2.3 1.2 Min 0.997 -0.1 0.7 -0.1 0.9 1.3 1.3 Typ 1.05 0 1.05 0 VCCP Max 1.102 0.33 1.20 0.11 1.2 4.1 4.1 100 2.75 1.45 Unit V V V V V mA mA A pF pF 2, 3 2 2 2 4 5 6 7 8 Notes1
Unless otherwise noted, all specifications in this table apply to all processor frequencies. The VCCP referred to in these specifications refers to instantaneous VCCP. Refer to the processor I/O Buffer Models for I/V characteristics. Measured at 0.1*VCCP. Measured at 0.9*VCCP. For Vin between 0V and VCCP. Measured when the driver is tristated. Cpad1 includes die capacitance only for PWRGOOD. No package parasitics are included. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 23
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Electrical Specifications
Table 10.
Open Drain Signal Group DC Specifications
Symbol VOH VOL IOL ILEAK Cpad Notes: 1. 2. 3. 4. 5. Parameter Output High Voltage Output Low Voltage Output Low Current Leakage Current Pad Capacitance 1.8 2.3 Min 1.0 0 11.4 Typ 1.05 Max 1.10 0.20 50 200 2.75 Unit V V mA A pF 2 4 5 Notes1 3
Unless otherwise noted, all specifications in this table apply to all processor frequencies. Measured at 0.2 V VOH is determined by value of the external pull-up resistor to VCCP. For Vin between 0 V and VOH. Cpad includes die capacitance only. No package parasitics are included.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 24
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
4.0
Package Mechanical Specifications and Pin Information
Package Mechanical Specifications
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz is available in 478-pin Micro-FCPGA (Micro- Flip Chip PGA) package.
4.1
4.1.1
Package Mechanical Drawings
Different views of the Micro-FCPGA package are shown in Figure 4, Figure 5, and Figure 6.
Figure 4.
Micro-FCPGA Package Top and Bottom Views
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Figure 5.
Micro-FCPGA Processor Package Drawing (Sheet 1)
Note:
All dimensions are in millimeters [inches]. Values shown for reference only.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 26
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Figure 6.
Micro-FCPGA Processor Package Drawing (Sheet 2)
Note:
All dimensions are in millimeters [inches]. Values shown for reference only.
4.1.2
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted in the keepout areas. The location and quantity of the capacitors may change, but remains within the component keep-in. Refer to Figure 4, Figure 5, and Figure 6 for keep-out zones.
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Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 27
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
4.1.3
Package Loading Specifications
Maximum mechanical package loading specifications are given in Figure 5. These specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading. These limitations are more platform specific, and should be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or loadbearing surface for thermal and mechanical solution.
4.1.4
Processor Mass Specifications
The typical mass of the processor is given in Figure 6. This mass includes all the components that are included in the package.
4.2
Processor Pin-Out and Pin List
Figure 7 shows the top view pinout of the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz. The alphabetical pin listing is shown in Table 14. The alphabetical signal listing is shown in Table 15.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 28
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Figure 7.
AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AE AD
The Coordinates of the Processor Pins as Viewed From the Top of the Package
AC AB AA Y W V U T R P N M L K J H G F E D C B A
VID SKT VSS A A VSS A A VSS A A VSS COM COM A VSS A A VSS A RS VSS RSV RSV [5] OCC [35] [34] [29] [30] [14] [10] P P [8]# [5]# [4]# [3]# [0]# D D VID VID A VSS A A VSS A A VSS A A VSS RSV VSS REQ A VSS REQ REQ VSS RS RES VSS RSV FOR [3] [4] [31] [27] [21] [28] [25] [13] [12] D [0]# [7]# [2]# [4]# [1]# ET# D CEP VID VID A A VSS A A VSS A A VSS A A VSS RSV A[6] VSS REQ REQ VSS BNR HIT VSS RSV RSV VSS [1] [2] [32] [33] [26] [20] [23] [24] [16] [9]# D # [3]# [1]# # # D D PRE VID VSS TDI TDO VSS RSP AP VSS A A VSS A A BR0 VSS MCE HIT VSS RS LOC VSS STP RSV LINT PWR Q# [0] # [1]# [22] [19] [15] [11] # RR# M# [2]# K# CLK D 0 GOO VSS BPM PRD VSS TMS TCK VSS BINI AP VSS A RSV VSS A VSS BR1 BPRI VSS TRD DRD VSS SMI INIT VSS FER THE [3]# Y# T# [0]# [18] D [17] # # Y# Y# # # R# RMT BPM VSS BPM BPM VSS TRS V ADS RSV VSS ADS ADS VSS DEF DBS VSS ODT IGN VSS A20 LINT VSS CCP VSS VCCP VCCP VSS [0]# [1]# [2]# T# TB D TB # ER# Y# EN NE# M# 1 VCC VCC VCC VCC VSS VCC SEN SEN VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VCCP VSS VCCP VCCP VSS VSS VCC VCC RSV SLP VCC VCC D # VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC BSE BSE VCC VCC L[1] L[0]
D VSS DST DST VSS DST DST VSS DST DST VSS DST DST VSS D D VSS D IERR VSS BSE [62] BP BN BP BN BP BN BP BN [5]# [2]# [0]# # L[2]
D VSS D D VSS D D VSS D VSS D D VSS D D VSS D D VSS D THR THR [61] [54] [53] [48] [49] [33] [24] [15] [11] [10] [6]# [3]# [1]# MDA MDC
DV DIN D VSS D D VSS D D D VSS D D VSS D D VSS D D VSS TES VCC CCP VSS [8]# [7]# T2 A [63] V [55] [51] [52] [37] [32] [31] [14] [12] [13] [9]#
D D VSS D D VSS D D VSS D RSV VSS D DP VSS D D VSS D D VSS D DIN VSS TES [60] [59] [56] [47] [43] [41] [50] D [36] [3]# [25] [26] [23] [20] [17] V T1
D VSS D D VSS D D VSS DP VSS DP D VSS D DIN VSS D D VSS D PRO VSS VCCP RSV VSS D D [57] [46] [45] [40] [38] [39] [2]# [1]# [30] [29] V [21] [18] [4]# CHO D VSS DIN D VSS COM COM D VSS DP D VSS D D VSS D D VSS BCL BCL VCCP VSS GTL D VSS D REF [58] [44] [42] V [35] P P [34] [0]# [28] [27] [22] [19] [16] K[0] K[1]
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 29
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
4.2.1
Table 11.
Alphabetical Signals Reference
Signal Description (Sheet 1 of 7)
Name Type
36
Description A[35:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
A[35:3]#
Input/ Output
A20M#
Input
ADS#
Input/ Output
ADSTB[1:0]#
Input/ Output
Signals REQ[4:0]#, A[16:3]# A[35:17]#
Associated Strobe ADSTB[0]# ADSTB[1]#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[31:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all front side bus agents. The following table defines the coverage model of these signals. AP[1:0]# Input/ Output Request Signals A[35:24]# A[23:3]# REQ[4:0]# Subphase 1 AP0# AP1# AP1# Subphase 2 AP1# AP0# AP0#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 30
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 11.
Signal Description (Sheet 2 of 7)
Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. If BINIT# observation is enabled during power-on configuration and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# assertion. Once the BINIT# assertion has been observed, the bus agents re-arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz FSB agents.This includes debug or performance monitoring tools. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of all FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. The BR0# (Bus Request 0) pin drives the BREQ[0]# signals in the system. The BREQ[0]# signal is directly connected to the processor (symmetric agent) and the Memory Controller Hub - MCH (priority agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz operates at 667 MHz system bus frequency (166 MHz BCLK[2:0] frequency respectively). COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors.
BINIT#
Input/ Output
BNR#
Input/ Output
BPM[2:1]# BPM[3,0]#
Output Input/ Output
BPRI#
Input
BR0#
Input/ Output
BSEL[2:0]
Output
COMP[3:0]
Analog
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 31
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 11.
Signal Description (Sheet 3 of 7)
Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and is thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.
Table 12.
D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]#
Quad-Pumped Signal Groups
DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3
Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. Input/ Output DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all FSB agents. DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all processor front side bus agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent inverts the data bus signals if more than half the bits, within the covered group, change level in the next cycle.
DBSY#
DEFER#
Input
DP[3:0]#
Input/ Output
Table 13.
DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]#
DINV[3:0]# Assignment To Data Bus
Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DRDY#
Input/ Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 32
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Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 11.
Signal Description (Sheet 4 of 7)
Name Type Description Data strobe used to latch in D[63:0]#. Signals Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]#
DSTBN[3:0]#
Data strobe used to latch in D[63:0]#. Signals Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]#
DSTBP[3:0]#
FERR#/PBE#
Output
FERR# (Floating-point Error) PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point error when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it remains asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active also causes an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide and the Intel(R) Processor Identification and CPUID Instruction application note (AP-485) application note. The FORCEPR# input can be used by the platform to force the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz system bus to activate the Thermal Control Circuit (TCC). The TCC remains active until the system deasserts FORCEPR#. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3* VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor keeps IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
FORCEPR#
Input
GTLREF
Input Input/ Output Input/ Output
HIT# HITM#
IERR#
Output
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 33
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 11.
Signal Description (Sheet 5 of 7)
Name Type Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those (R) (R) names on the Intel Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it waits until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor front side bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: * Enabled or disabled. * Asserted, if configured, for internal errors along with IERR#. * Asserted, if configured, by the request initiator of a bus transaction after it observes an error. * Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide. Since multiple agents may drive this signal at the same time, MCERR# is a wireOR signal which must connect the appropriate pins of all processor front side bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, MCERR# is activated on specific clock edges and sampled on specific clock edges. ODTEN (On-die termination enable) should be connected to VCC to enable on-die termination for end bus agents. Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz is always the end bus agent because it supports uniprocessor configurations only. Whenever ODTEN is high, on-die termination is active, regardless of other states of the bus. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor.
IGNNE#
Input
INIT#
Input
LINT[1:0]
Input
LOCK#
Input/ Output
MCERR#
Input/ Output
ODTEN
Input
PRDY# PREQ#
Output Input
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 34
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 11.
Signal Description (Sheet 6 of 7)
Name Type Description PROCHOT# (Processor Hot) goes active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated. This signal may require voltage translation on the motherboard. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification and be followed by a 2 ms (minimum) RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents deasserts their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55 ohm (nominal) on die pull-up resistor on this signal. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all FSB agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor front side bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. SKTOCC# (Socket occupied) is pulled to ground by the processor to indicate that the processor is present. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state does not recognize snoops or interrupts. The processor recognizes only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor tristates its outputs.
PROCHOT#
Output
PWRGOOD
Input
REQ[4:0]#
Input/ Output
RESET#
Input
RS[2:0]#
Input
RSP#
Input
RSVD
Reserved/ No Connect Output
SKTOCC#
SLP#
Input
SMI#
Input
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 35
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 11.
Signal Description (Sheet 7 of 7)
Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TEST1 must have a stuffing option of separate pull down resistors to VSS. TEST2 must have a 51W +/- 5% pull down resistor to VSS. Thermal Diode Anode. Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor stops all execution when the junction temperature exceeds approximately 125 C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. VCCA provides isolated power for the internal processor core PLLs. Processor I/O Power Supply. VCCSENSE is an isolated low impedance connection to processor core power (VCC ). It can be used to sense or measure power near the silicon with little noise. VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC ). Unlike some previous generations of processors, these are CMOS signals driven by the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. Refer to Table 4 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise.
STPCLK#
Input
TCK TDI TDO TEST1 TEST2 THERMDA THERMDC
Input Input Output Input Input Other Other
THERMTRIP#
Output
TMS
Input
TRDY#
Input
TRST# VCC VCCA VCCP VCCSENSE
Input Input Input Input Output
VID[5:0]
Output
VSSSENSE
Output
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 36
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 1 of 12)
Pin Name A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[3]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A20M# ADS# ADSTB#[0] ADSTB#[1] AP[0]# AP[1]# BCLK[0] Pin Number T1 N4 R2 T2 U1 P4 R3 N5 T5 T4 Y3 AA2 U4 V3 U3 V2 AA3 AB2 W2 Y1 G1 W1 AD2 AD3 AC3 AB1 AC1 J1 K1 L3 K2 M1 P3 C6 L6 M6 R6 V5 W4 B26 Signal Buffer Type Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync CMOS Common Clock Source Sync Source Sync Common Clock Common Clock Bus Clock Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 37
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 2 of 12)
Pin Name BCLK[1] BINIT# BNR# BPM[0]# BPM[1]# BPM[2]# BPM[3]# BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2] COMP[3] D[0]# D[1]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# D[19]# D[2]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[3]# Pin Number A26 W5 F3 AF6 AD6 AC6 AE5 K5 M4 C20 D20 A21 P26 R26 P1 N1 D21 C22 H22 J22 K23 H23 L23 L22 D26 D24 E25 E26 F21 F24 F25 G26 G24 M22 K24 J24 H26 K26 J25 E22 Signal Buffer Type Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Direction Input Input/Output Input/Output Input/Output Output Output Input/Output Input Input/Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 38
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 3 of 12)
Pin Name D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[4]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[5]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[6]# D[60]# D[61]# D[62]# D[63]# D[7]# D[8]# D[9]# Pin Number L25 N23 P23 P22 N26 U26 N24 R23 U25 T25 C25 W25 V24 Y26 W24 AA26 Y25 AB25 AA24 U22 T22 G21 T24 V23 U23 W22 Y22 Y23 AB24 AC25 AC26 AD24 F22 AE24 AB22 AA21 AD23 D23 E23 G23 Signal Buffer Type Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 39
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 4 of 12)
Pin Name DBSY# DEFER# DINV#[0] DINV#[1] DINV#[2] DINV#[3] DP[0]# DP[1]# DP[2]# DP[3]# DRDY# DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR# FORCEPR# GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# MCERR# ODTEN PRDY# PREQ# PROCHOT# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# Pin Number H6 J6 C24 H25 V26 AA23 L26 M25 P25 M24 G5 J21 M21 R21 V21 K21 N21 T21 W21 B5 A2 AD26 E3 J4 C21 E6 D5 B4 B6 F4 K4 F6 AD5 AF4 B25 A4 L2 H3 H2 J3 Signal Buffer Type Common Clock Common Clock Source Sync Source Sync Source Sync Source Sync Common Clock Common Clock Common Clock Common Clock Common Clock Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Open Drain CMOS Power/Other Common Clock Common Clock Open Drain CMOS CMOS CMOS CMOS Common Clock Common Clock Power/Other Common Clock Common Clock Open Drain CMOS Source Sync Source Sync Source Sync Source Sync Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Input Output Input Output Input Input/Output Input/Output Input/Output Input/Output
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 40
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 5 of 12)
Pin Name REQ[4]# RESET# RS[0]# RS[1]# RS[2]# RSP# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SKTOCC# SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 THERMTRIP# THRMDA THRMDC TMS TRDY# TRST# VCC VCC VCC VCC VCC Pin Number G2 D2 F1 E2 G4 Y4 L5 M3 N2 P6 R5 B3 C4 D7 R24 AE25 D1 C1 B2 C3 AE1 C7 E5 D4 AA5 AC4 AB4 A24 B23 A5 B22 A22 AB5 H5 AA6 AC20 AD20 AE20 AF20 AA17 Signal Buffer Type Source Sync Common Clock Common Clock Common Clock Common Clock Common Clock Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power/Other CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Open Drain Power/Other Power/Other CMOS Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Output Output Input Input Input Input Input Output Direction Input/Output Input Input Input Input Input
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 41
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 6 of 12)
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Number AA18 AB17 AB18 AC17 AC18 AD17 AD18 AE17 AE18 AF17 AF18 AA15 AB15 AC15 AD15 AE15 AF15 AA13 AB14 AC13 AD14 AE13 AF14 AA12 AB12 AC12 AD12 AE12 AF12 AA9 AA10 AB9 AB10 AC9 AC10 AD9 AD10 AE9 AE10 AF9 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 42
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 7 of 12)
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Number AF10 AC7 AD7 AE7 AF7 A20 B20 E20 F20 A17 A18 B17 B18 C17 C18 D17 D18 E17 E18 F17 F18 A15 B15 C15 D15 E15 F15 A13 B14 C13 D14 E13 F14 A12 B12 C12 D12 E12 F12 A9 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 43
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 8 of 12)
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCP VCCP. VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VSS VSS Pin Number A10 B9 B10 C9 C10 D9 D10 E9 E10 F9 F10 A7 B7 E7 F7 A23 AC23 U6 AF25 AF26 AF23 AB21 AC22 AD21 AE21 AE22 AF22 AA20 AB20 V6 Y6 AA7 AE4 AF3 AE3 AF2 AE2 AF1 AA25 AB26 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS CMOS CMOS CMOS CMOS Power/Other Power/Other Output Output Output Output Output Output Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 44
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 9 of 12)
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number AD25 AE26 AB23 AC24 AE23 AF24 AA22 AC21 AD22 AF21 AA19 AB19 AC19 AD19 AE19 AF19 AA16 AB16 AC16 AD16 AE16 AF16 AA14 AB13 AC14 AD13 AE14 AF13 AA11 AB11 AC11 AD11 AE11 AF11 AA8 AB8 AC8 AD8 AE8 AF8 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 45
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 10 of 12)
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number AB6 AC5 AE6 AF5 AA4 AB3 AD4 AA1 AC2 AD1 A6 C5 D6 F5 G6 J5 K6 M5 N6 P5 T6 U5 W6 Y5 A3 D3 E4 G3 H4 K3 L4 N3 R4 T3 V4 W3 C2 E1 F2 H1 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 46
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 14.
Alphabetical Signal Listing (Sheet 11 of 12)
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number J2 L1 M2 P2 R1 U2 V1 Y2 A25 C26 D25 F26 B24 C23 E24 F23 B21 D22 E21 A19 B19 C19 D19 E19 F19 A16 B16 C16 D16 E16 F16 A14 B13 C14 D13 E14 F13 A11 B11 C11 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 47
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 14.
Alphabetical Signal Listing (Sheet 12 of 12)
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE Pin Number D11 E11 F11 A8 B8 C8 D8 E8 F8 G25 J26 K25 M26 N25 R25 T26 V25 W26 H24 J23 L24 M23 P24 T23 U24 W23 Y24 G22 H21 K22 L21 N22 P21 R22 U21 V22 Y21 AB7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 48
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 1 of 12)
Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 Pin Name FORCEPR# VSS PWRGOOD THERMTRIP# VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC BSEL[2] THRMDC VCCA TEST1 VSS BCLK[1] VSS A[21]# A[26]# VSS TCK TRST# VCCSENSE VSS VCC VCC VSS VCC VCC VSS Signal Buffer Type CMOS Power/Other CMOS Open Drain Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Power/Other Power/Other Test Power/Other Bus Clock Power/Other Source Sync Source Sync Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/Output Input/Output Input Output Input Output Direction Input
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 49
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 2 of 12)
Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 Pin Name VCC VSS VCC VCC VSS VCCP D[62]# VSS DINV#[3] D[47]# VSS D[44]# A[34]# A[27]# VSS TDO TMS VSS VSSSENSE VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCCP VCCP D[61]# VSS D[56]# D[46]# VSS A[35]# VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Input/Output Input/Output Input/Output Input/Output Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 50
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 3 of 12)
Pin Number AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Pin Name A[33]# TDI VSS BPM[2]# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS VCCP VCCP VSS D[57]# D[58]# VSS A[31]# A[32]# VSS PRDY# BPM[1]# VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS Signal Buffer Type Source Sync CMOS Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input/Output Input/Output Input/Output Input/Output Output Direction Input/Output Input
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 51
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 4 of 12)
Pin Number AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 Pin Name VCC VCC VSS VCC VCCP VSS D[63]# D[59]# VSS GTLREF SKTOCC# VID[4] VID[2] VID[0] BPM[3]# VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCCP VCCP VSS D[60]# RSVD VSS VID[5] VID[3] VID[1] PREQ# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other CMOS CMOS CMOS Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Reserved Power/Other CMOS CMOS CMOS Common Clock Output Output Output Input Input/Output Input Output Output Output Output Input/Output Input/Output Input/Output Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 52
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 5 of 12)
Pin Number AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Pin Name VSS BPM[0]# VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCCP VCCP VSS VCCP VCCP RSVD RSVD LINT0 FERR# LINT1 VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS Signal Buffer Type Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Reserved CMOS Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Input Output Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 53
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 6 of 12)
Pin Number B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 Pin Name VCC VSS THRMDA TEST2 VSS PROCHOT# BCLK[0] RSVD VSS RSVD RSVD VSS A20M# SLP# VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS BSEL[0] IERR# D[1]# VSS DINV#[0] D[4]# VSS RSVD RESET# VSS STPCLK# INIT# VSS RSVD Signal Buffer Type Power/Other Power/Other Power/Other Test Power/Other Open Drain Bus Clock Reserved Power/Other Reserved Reserved Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Open Drain Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Common Clock Power/Other CMOS CMOS Power/Other Reserved Input Input Input Input/Output Input/Output Output Output Input/Output Input Input Output Input Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 54
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 7 of 12)
Pin Number D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 Pin Name VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS BSEL[1] D[0]# VSS D[7]# D[17]# VSS D[16]# VSS RS[1]# HIT# VSS SMI# IGNNE# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Common Clock Common Clock Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input/Output Input/Output Input/Output Input/Output Output Input/Output Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 55
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 8 of 12)
Pin Number E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 Pin Name D[3]# D[8]# VSS D[18]# D[19]# RS[0]# VSS BNR# LOCK# VSS ODTEN VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC D[2]# D[6]# VSS D[20]# D[21]# VSS A[3]# REQ[4]# VSS RS[2]# DRDY# VSS D[5]# VSS D[9]# Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Source Sync Power/Other Source Sync Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Direction Input/Output Input/Output
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 56
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 9 of 12)
Pin Number G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 Pin Name D[23]# VSS D[22]# VSS REQ[2]# REQ[1]# VSS TRDY# DBSY# VSS D[10]# D[13]# VSS DINV#[1] D[27]# A[4]# VSS REQ[3]# HITM# VSS DEFER# DSTBN[0]# D[11]# VSS D[26]# D[29]# VSS A[5]# A[7]# VSS MCERR# BPRI# VSS DSTBP[0]# VSS D[12]# D[25]# VSS D[28]# VSS Signal Buffer Type Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Source Sync Common Clock Power/Other Common Clock Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Direction Input/Output
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 57
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 10 of 12)
Pin Number L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 Pin Name REQ[0]# A[6]# VSS RSVD ADS# VSS D[15]# D[14]# VSS D[30]# DP[0]# A[8]# VSS RSVD BR0# VSS ADSTB#[0] DSTBN[1#] D[24]# VSS DP[3]# DP[1]# VSS COMP[3] RSVD VSS A[11]# A[17]# VSS DSTBP[1]# VSS D[31]# D[36]# VSS D[34]# COMP[2] VSS A[9]# A[15]# VSS Signal Buffer Type Source Sync Source Sync Power/Other Reserved Common Clock Power/Other Source Sync Source Sync Power/Other Source Sync Common Clock Source Sync Power/Other Reserved Common Clock Power/Other Source Sync Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Power/Other Reserved Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Power/Other Source Sync Source Sync Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction Input/Output Input/Output
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 58
January 2007 Order Number: 315876-002
Package Mechanical Specifications and Pin Information--Intel(R) Celeron(R) Processor 1.66 GHz/ 1.83 GHz
Table 15.
Alphabetical Pin Listing (Sheet 11 of 12)
Pin Number P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 Pin Name RSVD VSS D[33]# D[32]# VSS DP[2]# COMP[0] VSS A[12]# A[16]# VSS RSVD ADSTB[1]# DSTBN[2]# VSS D[37]# RSVD VSS COMP[1] A[10]# A[13]# VSS A[19]# A[18]# VSS DSTBP[2]# D[49]# VSS D[50]# D[39]# VSS A[14]# VSS A[24]# A[22]# VSS VCCP VSS D[48]# D[52]# Signal Buffer Type Reserved Power/Other Source Sync Source Sync Power/Other Common Clock Power/Other Power/Other Source Sync Source Sync Power/Other Reserved Source Sync Source Sync Power/Other Source Sync Reserved Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Source Sync Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 59
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Package Mechanical Specifications and Pin Information
Table 15.
Alphabetical Pin Listing (Sheet 12 of 12)
Pin Number U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 Pin Name VSS D[38]# D[35]# VSS A[25]# A[23]# VSS AP[0]# VCCP DSTBN[3]# VSS D[51]# D[41]# VSS DINV[2]# A[30]# A[28]# VSS AP[1]# BINIT# VSS DSTBP[3]# D[53]# VSS D[43]# D[40]# VSS A[29]# VSS A[20]# RSP# VSS VCCP VSS D[54]# D[55]# VSS D[45]# D[42]# Signal Buffer Type Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Common Clock Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Common Clock Common Clock Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Common Clock Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 60
January 2007 Order Number: 315876-002
Thermal Specifications and Design Considerations--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
5.0
Thermal Specifications and Design Considerations
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (TJ) specifications at the corresponding thermal design power (TDP) value listed in Table 16 for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. Refer to the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Thermal Design Guideline for Embedded Applications document for more details on processor and system level cooling approaches. The maximum junction temperature is defined by an activation of the processor Intel(R) Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 16. The Intel thermal monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases the Intel thermal monitor feature must be enabled for the processor to remain within specification.
Table 16.
Power Specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz (Sheet 1 of 2)
Symbol TDP Symbol PAH, PSGNT Core Frequency & Voltage 1.66 GHz/1.83 GHz Parameter Auto Halt, Stop Grant Power Min Thermal Design Power 27 Typ Max 15.0 Unit W Unit W Notes 1, 4 Notes 2
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 61
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Thermal Specifications and Design Considerations
Table 16.
Power Specifications for the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz (Sheet 2 of 2)
Symbol PSLP TJ Core Frequency & Voltage Sleep Power Junction Temperature 0 Thermal Design Power 14.8 100 Unit W C Notes 2 3
Notes: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating to 50 C. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor's automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications.
5.1
Thermal Specifications
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz incorporates three methods of monitoring die temperature, the Digital Thermal Sensor, Intel Thermal Monitor and the Thermal Diode. The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached.
5.1.1
Thermal Diode
The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal "diode", with its collector shorted to ground. The thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific Register (MSR) and applied. Refer to Section 5.1.2 for more details. Please refer to Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted.
Note:
The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, does not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change. Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor's Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Model Specific Register (MSR). Table 17, Table 18, and Table 19 provide the "diode" interface and specifications. Two different sets of "diode" parameters are listed in Table 18. The Diode Model parameters (Table 18) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 19) have been added to support thermal sensors that use the transistor equation method. The
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 62
January 2007 Order Number: 315876-002
Thermal Specifications and Design Considerations--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external thermal sensor supplier for their recommendation. This thermal "diode" is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 17. Thermal Diode Interface
Signal Name THERMDA THERMDC Pin/Ball Number B22 A22 Signal Description Thermal diode anode Thermal diode cathode
Table 18.
Thermal "Diode" Parameters using Diode Mode
Symbol IFW n RT Parameter Forward Bias Current Diode Ideality Factor Series Resistance Min 5 1.000 2.79 1.009 4.52 Typ Max 200 1.050 6.24 Unit A Notes 1 2, 3, 4 2, 3, 5
Notes: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized across a temperature range of 50 - 100C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT -1) where IS = saturation current, q = electronic charge, V D = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N] where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge.
5.
When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 17. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called ntrim) is 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processor's diode ideality deviates from that of ntrim, each calculated temperature is offset by a fixed amount. This temperature offset can be calculated with the equation: Terror(nf) = Tmeasured X (1 - nactual/ntrim) Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device.
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 63
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Thermal Specifications and Design Considerations
5.1.2
Thermal Diode Offset
In order to improve the accuracy of diode based temperature measurements, a temperature offset value (specified as Toffset) is programmed into a Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz Model Specific Register (MSR) which contains thermal diode characterization data. During manufacturing, the processor thermal diode is evaluated for its behavior relative to a theoretical diode. Using the equation above, the temperature error created by the difference between ntrim and the actual ideality of the particular processor is calculated. If the ntrim value used to calculate Toffset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the actual ntrim as defined in the temperature sensor manufacturers' datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 19.
Table 19.
Thermal "Diode" ntrim and Diode Correction Toffset
Symbol ntrim Parameter Diode ideality used to calculate Toffset 1.01 Unit
5.1.3
Intel(R) Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum junction temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. A thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence.
Note:
The Intel thermal monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). After Automatic mode is enabled, the TCC activates only when the internal die temperature reaches the maximum allowed value for operation. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 takes precedence over TM1. However, if TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 also activates to help cool down the processor.
Note:
Intel recommends both Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2) be always enabled on Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 64
January 2007 Order Number: 315876-002
Thermal Specifications and Design Considerations--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor performs an voltage/frequency transition to a lower operating point. When the processor temperature drops below the critical level, the processor makes an voltage/frequency transition to the last requested operating point. Note: The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz only supports TM2 initiated voltage/ frequency transitions. Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz does not support Enhanced Intel(R) SpeedStep(R) Technology (EIST) therefore it does not support software or MSR based EIST transitions. Likewise, when TM1 is enabled, and a high temperature situation exists, the clocks are modulated by alternately turning the clocks off and on at a 50% duty cycle (automatic mode). Cycle times are processor speed dependent and decreases linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance is decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC is activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode takes precedence An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three model specific registers (MSR), one output pin (PROCHOT#), and one input pin (FORCEPR#). All are available to monitor and control the state of the Intel thermal monitor feature. The Intel thermal monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# is not asserted when the processor is in the Stop Grant, and Sleep, low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters a low power state with PROCHOT# already asserted, PROCHOT# remains asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Thermal Monitor automatic mode is disabled, the processor is operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor automatically shuts down when the silicon has reached a temperature of approximately 125 C. At this point the THERMTRIP# signal goes active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.0.
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 65
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Thermal Specifications and Design Considerations
5.1.4
Digital Thermal Sensor
The Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz also contains an on die digital thermometer that can be read via a MSR (no I/O interface). The digital thermometer shares the thermal sensor of the Intel Thermal Monitor. Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz has a unique digital thermometer whose temperature is accessible via processor MSR. The digital sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor throttling via the Thermal Monitor. Unlike traditional thermal devices, the Digital Thermometer outputs a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the Digital Thermometer is always at or below T J,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermometer MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the thermal monitor (TM1/TM2) trigger points. When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism activates. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications.
5.1.5
Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor's TM1 or TM2 are triggered and the temperature remains high, an "Out Of Spec" status and sticky bit are latched in the status MSR register and generates thermal interrupt.
5.1.6
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 (TM1) or Intel Thermal Monitor 2 (TM2) is enabled (note that the TM1 or TM2 must be enabled for the processor to be operating within specification), the TCC is active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. If the processor die cools down below maximum operating temperature (Tjmax) either due to TCC activation or an external event, PROCHOT# automatically de-asserts and the processor resumes normal operation. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 66
January 2007 Order Number: 315876-002
Thermal Specifications and Design Considerations--Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz
5.1.7
FORCEPR# Signal Pin
The FORCEPR# (force power reduction) input can be used by the platform to cause the Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz to activate the TCC. If the Thermal Monitor is enabled, the TCC is activated upon the assertion of the FORCEPR# signal. The TCC remains active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous input. FORCEPR# can be used to thermally protect other system components. Using the VR as an example, when the FORCEPR# pin is asserted, the TCC circuit in the processor activates reducing the current consumption of the processor and the corresponding temperature of the VR. It should be noted that assertion of the FORCEPR# does not automatically assert PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high temperature situation is detected. A minimum pulse width of 500 s is recommend when the FORCEPR# is asserted by the system. Sustained activation of the FORCEPR# pin may cause noticeable platform performance degradation.
5.1.8
THERMTRIP# Signal Pin
Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor automatically shuts down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 11). At this point, the system bus signal THERMTRIP# goes active and stay active as described in Table 11. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.
January 2007 Order Number: 315876-002
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 67
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz--Thermal Specifications and Design Considerations
Intel(R) Celeron(R) Processor 1.66 GHz/1.83 GHz DS 68
January 2007 Order Number: 315876-002

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