View DS3514T_4823748.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 1; 10/08
I2C Gamma and VCOM Buffer with EEPROM
General Description
The DS3514 is a programmable gamma and VCOM voltage generator that supports both real-time updating as well as multibyte storage of gamma/VCOM data in onchip EEPROM memory. An independent 10-bit DAC, two 10-bit data registers, and four words of EEPROM memory are provided for each individually addressable gamma or V COM channel. High-performance buffer amplifiers are integrated on-chip, providing rail-to-rail, low-power (400A/gamma channel) operation. The VCOM channel features a high current drive (> 250mA peak) and a fast-settling buffer amplifier optimized to drive the VCOM node of a wide range of TFT-LCD panels. Programming occurs through an I2C-compatible serial interface. Interface performance and flexibility are enhanced by a pair of independently loaded data latches per channel, as well as support for I2C speeds up to 400kHz. The multitable EEPROM memory enables a rich variety of display system enhancements, including support for temperature or light-level dependent gamma tables, enabling of factory or field automated display adjustment, and support for backlight dimming algorithms to reduce system power. Upon power-up and depending on mode, DAC data is selected from EEPROM by the S0/S1 pins or from a fixed memory address. 10-Bit Gamma Buffers, 14 Channels 8-Bit VCOM Buffer, 1 Channel Four 10-Bit EEPROM Words per Channel Low-Power 400A/ch Gamma Buffers I2C-Compatible Serial Interface Flexible Control from I2C or Pins 9.0V to 15.0V Analog Supply 2.7V to 5.5V Digital Supply 48-Pin TQFN Package (7mm x 7mm)
Features
DS3514
Ordering Information
PART DS3514T+ DS3514T+T&R TEMP RANGE -45C to +95C -45C to +95C PIN-PACKAGE 48 TQFN-EP* 48 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Applications
TFT-LCD Gamma and VCOM Buffer Adaptive Gamma and VCOM Adjustment (Real Time by I2C, Select EEPROM Through I2C or S0/S1 Pins) Industrial Process Control
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
Gamma or VCOM Channel Functional Diagram
SDA, SCL A0 I2C INTERFACE LATCH A MUX LATCH B 8-/ 10-BIT* DAC
VOUT
IN EEPROM S1/ S0 LOGIC ADDRESS
OUT
LD * 10 BITS FOR GAMMA CHANNELS, 8 BITS FOR THE VCOM CHANNEL.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
I2C Gamma and VCOM Buffer with EEPROM DS3514
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to GND ................-0.5V to +16V Voltage Range on VRL, VRH, GHH, GHM, GLM, GLL Relative to GND.........-0.5V to (VDD + 0.5V), not to exceed 16V Voltage Range on VCC Relative to GND ..................-0.5V to +6V Voltage Range on SDA, SCL, A0, LD, S0, S1 Relative to GND .....-0.5V to (VCC + 0.5V), not to exceed 6V Junction Temperature ......................................................+125C Operating Temperature Range ...........................-45C to +95C Programming Temperature Range .........................0C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -45C to +95C.)
PARAMETER Digital Supply Voltage Analog Supply Voltage VRH, VRL Voltage GHH, GHM, GLM, GLL Voltage Input Logic 1 (SCL, SDA, A0, S0, S1, LD) Input Logic 0 (SCL, SDA, A0, S0, S1, LD) VCOM Load Capacitor VCAP Compensation Capacitor SYMBOL VCC VDD VVCOM VGM1-14 VIH VIL CD CCOMP (Notes 1, 2) (Note 1) Applies to VCOM output Applies to GM1-GM14 CONDITIONS MIN 2.7 9.0 2.0 GND + 0.2 0.7 x VCC -0.3 1 0.1 TYP MAX 5.5 15.0 VDD - 2.0 VDD - 0.2 VCC + 0.3 0.3 x VCC UNITS V V V V V V F F
INPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER Input Leakage (SDA, SCL, A0, S0, S1, LD) VDD Supply Current VCC Supply Current, Nonvolatile Read or Write VCC Standby Supply Current VDD Standby Supply Current I/O Capacitance (SDA, SCL, LD, S0, S1, A0) End-to-End Resistance (VRH to VRL) RTOTAL Tolerance SYMBOL IL IDD ICC ICCQ IDDQ CI/O RTOTAL TA = +25C -20 (Note 3) (Note 4) (Note 5) (Note 6) Guaranteed by design CONDITIONS MIN -1 5 0.25 10 450 5 16 +20 TYP MAX +1 10 0.6 30 850 10 UNITS A mA mA A A pF k %
2
_______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
INPUT ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER Input Resistance (GHH, GHM, GLM, GLL) Input Resistance Tolerance Power-On Recall Voltage Power-Up Time VPOR tD TA = +25C (Note 7) (Note 8) -20 1.6 25 SYMBOL CONDITIONS MIN TYP 75 +20 2.6 MAX UNITS k % V ms
DS3514
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, VRL = +2.0V, GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = +13.0V, GHH = +14.8V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER GM1-GM14 DAC Resolution VCOM DAC Resolution VCOM Integral Nonlinearity Error VCOM Differential Nonlinearity Error GM1-GM14 Integral Nonlinearity Error GM1-GM14 Differential Nonlinearity Error Output Voltage Range (VCOM) Output Voltage Range (GM1-G14) VCOM Output Accuracy GM1-GM14 Offset GM1-GM14 Output Accuracy Voltage Gain (GM1-GM14) Load Regulation (VCOM, GM1-GM14) Short-Circuit Current (VCOM) S0/S1 to LD Setup Time S0/S1 to LD Hold Time VCOM Settling Time from LD Low to High (S0/S1 Meet tSU) GM1-GM14 Settling Time from LD Low to High S0, S1 to GM1-GM14 Output 10% Settled t SU tHD t SET-V t SET-G t SEL To VDD or GND Figure 2 Figure 2 Settling to 0.1% of final VCOM level (Figure 1) (Note 11) 4tAU settled with ILOAD= 20mA (Figure 2) (Notes 11, 12, 13) 10% settling (Figure 3), LD = VCC (asynchronous) (Notes 11, 13) 250 37.5 37.5 2.0 5.0 600 TA = +25C GM outputs = VDD/2, TA = +25C GM outputs = VDD/2, TA = +25C -35 0.995 1.0 INL DNL INL DNL TA = +25C (Note 9) TA = +25C (Note 10) TA = +25C (Note 9) TA = +25C (Note 10) SYMBOL CONDITIONS MIN 10 8 -0.5 -0.5 -1.0 -0.35 2.0 0.2 -20 37 +35 +0.5 +0.5 +1.0 +0.35 VDD - 2.0 VDD - 0.2 +20 TYP MAX UNITS Bits Bits LSB LSB LSB LSB V V mV mV mV V/V mV/mA mA ns ns s s ns
_______________________________________________________________________________________
3
I2C Gamma and VCOM Buffer with EEPROM DS3514
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45C to +95C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 4.)
PARAMETER SCL Clock Frequency Bus-Free Time between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time Pulse-Width Suppression Time at SDA and SCL Inputs A0 Setup Time A0 Hold Time SDA and SCL Input Buffer Hysteresis Input Capacitance on A0, SDA, or SCL Low-Level Output Voltage (SDA) SCL Falling Edge to SDA Output Data Valid Output Data Hold CI VOL tAA tDH 4mA sink current SCL falling through 0.3 x VCC to SDA exit 0.3 x VCC to 0.7 x VCC window SCL falling through 0.3x VCC until SDA in 0.3 x VCC to 0.7 x VCC window 0 SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tHD:DAT t SU:DAT t SU:STA tR tF t SU:STO CB tW t IN t SU:A tHD:A (Note 15) (Note 16) (Note 17) Before START After STOP 0.6 0.6 0.05 x VCC 5 10 0.4 900 (Note 15) (Note 15) (Note 14) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 50 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms ns s s V pF V ns ns
4
_______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V.)
PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS TA = +85C (Guaranteed by design) TA = +25C (Guaranteed by design) MIN 50,000 200,000 MAX UNITS Writes
DS3514
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Note 10:
Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17:
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. If VCC is less than +2.7V or is left unconnected, the DS3514 pulls the I2C bus to VCC, preventing communication with other devices on the I2C bus. IDD supply current is specified with VDD = 15.0V and no load on VCOM or GM1-GM14 outputs. ICC is specified with the following conditions: SCL = 400kHz, SDA = VCC = 5.5V, and VCOM and GM1-GM14 floating. ICCQ is specified with the following conditions: SCL = SDA = VCC = 5.5V, and VCOM and GM1-GM14 floating. IDDQ is specified with the following conditions: SCL = SDA = VCC = 5.5V and VCOM and GM1-GM14 floating. This is the minimum VCC voltage that causes EEPROM to be recalled. This is the time from VCC > VPOR and VDD > VDD(MIN) until the device is powered up. Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. INL = [V(RW)i - (V(RW)0]/LSB(measured) - i, for i = 0...N (N = 255 for VCOM, 1023 for GM1-GM14). Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i]/LSB(measured) - 1, for i = 0...(N - 1) (N = 255 for VCOM, 1023 for GM1-GM14). Specified with the VCOM and gamma bias currents set to 100% (CR.5 = 1, CR.4 = 0). EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected. Rising transition from 5V to 10V; falling transition from 10V to 5V. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing. CB--total capacitance of one bus line in picofarads. EEPROM write time begins after a STOP condition occurs. Pulses narrower than max are suppressed.
VRH
VDD
DS3514 VCOM 80h 8-BIT DAC VCOM 2.2 CD = 1F 0.1F
0 TO 1.5V 50kHz
VRL
Figure 1. VCOM Settling Timing Diagram
_______________________________________________________________________________________
5
I2C Gamma and VCOM Buffer with EEPROM DS3514
S0/S1 VIH VIL tHD tSU tSET-G GM1-GM14 VIH LD VIL ILOAD 100pF
4tAU SETTLED
GM1-G14
Figure 2. GM1-GM14 Settling Timing Diagram
S0/S1 (LD = VCC)
VIH VIL GM1-GM14 tSEL OUTPUT 10% SETTLED 100pF
GM1-GM14
Figure 3. Input Pin to Output Change Timing Diagram
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 4. I2C Timing Diagram
6 _______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
Typical Operating Characteristics
(VCC = +5.0V, VDD = +15V, TA = +25C, unless otherwise noted.)
DS3514
DIGITAL SUPPLY STANDBY CURRENT vs. VCC
DS3514 toc01
DIGITAL SUPPLY STANDBY CURRENT vs. TEMPERATURE
SDA = SCL = VCC 25 ICCQ CURRENT (A) 20 VCC = 5.0V 15 10 5 VCC = 3.3V 0
DS3514 toc02
ANALOG SUPPLY STANDBY CURRENT vs. VDD
400 350 IDDQ CURRENT (A) 300 250 200 150 100
DS3514 toc03
30 SDA = SCL = VCC 25 ICCQ CURRENT (A) 20 15 10 5 0 2 3 4 VCC VOLTAGE (V) 5 6
30
450
50 0 55 75 95 9 11 13 15
-45
-25
-5
15
35
TEMPERATURE (C)
VDD VOLTAGE (V)
ANALOG SUPPLY STANDBY CURRENT vs. TEMPERATURE
DS3514 toc04
ANALOG SUPPLY CURRENT vs. VDD
DS3514 toc05
ANALOG SUPPLY CURRENT vs. TEMPERATURE
9 8 IDD CURRENT (mA) BIAS = 150%
DS3514 toc06
450 400 350 IDDQ CURRENT (A)
10 9 8 IDD CURRENT (mA) 7 6 5 4 3 2 1 0 BIAS = 80% BIAS = 60% BIAS = 100% BIAS = 150%
10
300 250 200 150 100 50 0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C)
7 6 5 4 3 2 1 0
BIAS = 100%
BIAS = 80% BIAS = 60%
9
11
13
15
-45
-25
-5
15
35
55
75
95
VDD VOLTAGE (V)
TEMPERATURE (C)
GAMMA SETTLING
DS3514 toc07
GAMMA OUTPUT vs. SETTING
VDD = 15.0V, GHH = 14.8V, GHM = 10.2V, GLM = 4.8V, GLL = 0.2V GM8 TO GM14 9
DS3514 toc08
GM DNL
0.20 0.15 0.10 GM DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20
DS3514 toc09
10 BIAS = 150% 9 GAMMA VOLTAGE (V) 8 7 BIAS = 60% 6 5 4 -1 0 1 2 TIME (s) 3 4 5 BIAS = 100% BIAS = 80%
15
0.25
12 GM OUTPUT (V)
6 GM1 TO GM7 3
0 0 128 256 384 512 640 768 896 1024 GAMMA SETTING (DEC)
-0.25 0 128 256 384 512 640 768 896 1024 GAMMA SETTING (DEC)
_______________________________________________________________________________________
7
I2C Gamma and VCOM Buffer with EEPROM DS3514
Typical Operating Characteristics (continued)
(VCC = +5.0V, VDD = +15V, TA = +25C, unless otherwise noted.)
GM INL
DS3514 toc10
VCOM DNL
DS3514 toc11
VCOM INL
0.40 0.30 VCOM INL (LSB) 0.20 0.10 0
DS3514 toc12
0.50
0.50 0.40 0.30 VCOM DNL (LSB) 0.20 0.10 0
0.50
0.25 GM INL (LSB)
0
-0.10 -0.20
-0.10 -0.20 -0.30 -0.40
-0.25
-0.30 -0.40
-0.50 0 128 256 384 512 640 768 896 1024 GAMMA SETTING (DEC)
-0.50 0 32 64 96 128 160 192 224 256 VCOM SETTING (DEC)
-0.50 0 32 64 96 128 160 192 224 256 VCOM SETTING (DEC)
VCOM PHASE MARGIN vs. LOAD CAPACITANCE
DS3514 toc13
VCOM UNITY GAIN BANDWIDTH vs. LOAD CAPACITANCE
DS3514 toc14
180 150 PHASE MARGIN (DEGREES) 120 90 60 30 0 100.0E-9
500
UNITY GAIN BANDWIDTH (kHz)
400
300
200
100
1.0E-6 LOAD CAPACITANCE (F)
10.0E-6
0 100.0E-9
1.0E-6 LOAD CAPACITANCE (F)
10.0E-6
8
_______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
Pin Description
PIN 1-5, 9, 10, 46, 48 6, 23, 43 7 8 11, 18, 19, 21, 22, 42 12 13 14 15 16 17, 47 20 24-30 31-37 38 39 40 41 44 45 EP NAME N.C. VDD VRH VRL GND S1 S0 LD SDA SCL VCC VCAP GM1-GM7 GM8-GM14 GLM GLL GHM GHH VCOM A0 GND TYPE -- Power Ref Input Ref Input Power Input Input Input Input/Output Input Power Input Output Output Ref Input Ref Input Ref Input Ref Input Output Input -- No Connection Analog Supply (9.0V to 15.5V) High-Voltage Reference for VCOM DAC Low-Voltage Reference for VCOM DAC Ground Select Inputs. When the Control register [1,0] = 00, S0 and S1 are used to select DAC input data from EEPROM. Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch). When LD is high, the input to Latch B data flows through to the output and updates the DACs asynchronously. I2C Serial Data Input/Output I2C Serial Clock Input Digital Supply (2.7V to 5.5V) Compensation Capacitor Input. Connect VCAP to GND through a 0.1F capacitor. Low-Voltage Gamma Analog Outputs High-Voltage Gamma Analog Outputs Reference for Low-Voltage Gamma DAC Reference for Low-Voltage Gamma DAC Reference for High-Voltage Gamma DAC Reference for High-Voltage Gamma DAC VCOM Analog Output. This output requires a 1F capacitor to GND. Address Input. This pin determines the DS3514's I2C slave address. Ground. Exposed Pad. Connect to GND. FUNCTION
DS3514
_______________________________________________________________________________________
9
I2C Gamma and VCOM Buffer with EEPROM DS3514
Block Diagram
GHH DS3514 BANKS GM14 BANK A GM14 BANK B GM14 BANK C GM14 BANK D S0/S1 PINS S0/S1 BITS I2C COMP MODE0 BIT MODE1 BIT 0 1 LATCH A GHH MUX 0 1 LD GHM 10 BITS LATCH B 10-BIT DAC GM14 GHH
BANKS GM8 BANK A GM8 BANK B GM8 BANK C GM8 BANK D S0/S1 PINS S0/S1 BITS I2C COMP 0 1
GHH MUX 0 1 LATCH A LD GHM 10 BITS LATCH B 10-BIT DAC GM8
SDA SCL A0
I2C INTERFACE
I2C
MODE0 BIT
MODE1 BIT GHM GHM
MODE0 BIT (CR.0) S0 S1 LD LOGIC AND CONTROL MODE1 BIT (CR.1) S0/S1 PINS S0/S1 BITS (SOFT S0/S1) LD I2C COMP
BANKS VCOM BANK A VCOM BANK B VCOM BANK C VCOM BANK D S0/S1 PINS S0/S1 BITS 0 1
VRH MUX 0 1 LATCH A LD VRL MODE0 BIT MODE1 BIT GLM GLM 8 BITS LATCH B 8-BIT DAC VCOM
VCAP
COMPENSATION
COMP
BANKS GM7 BANK A GM7 BANK B GM7 BANK C GM7 BANK D S0/S1 PINS S0/S1 BITS 0 1
GLM MUX 0 1 LATCH A LD GLL 10 BITS LATCH B 10-BIT DAC GM7
VDD VDD VCC VCC BANKS GM1 BANK A GM1 BANK B GM1 BANK C GM1 BANK D S0/S1 PINS S0/S1 BITS I2C COMP MODE0 BIT MODE1 BIT 0 1 LATCH A I2C COMP MODE0 BIT MODE1 BIT
GLM MUX 0 1 LD GLL 10 BITS LATCH B 10-BIT DAC GM1
GND
GLL
GLL
10
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM DS3514
Detailed Description
The DS3514 operates in one of three modes that determine how the V COM and gamma DACs are controlled/updated. The first two modes allow "banked" control of the 14 gamma channels and one VCOM channel. Depending on the mode, one of four banks (in EEPROM) can be selected using either the S0/S1 pins or using the SOFT S0/S1 bits in the Soft S0/S1 register. Once a bank is selected, the LD pin can then be used to simultaneously update each channel's DAC output. The third and final mode is not banked. It allows I2C control of each channel's Latch A register that is SRAM (volatile), allowing quick and unlimited updates. In this mode, the LD pin can also be used to simultaneously update each channel's DAC output. A detailed description of the three modes as well as additional features of the DS3514 follows. the state of S0/S1 to meet the t SEL specification. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by S0/S1. A high-to-low transition on LD latches the selected DAC data into Latch B.
SOFT S0/S1 Bit-Controlled Bank-Updating Mode
This mode also features banked operation with the only difference being how the desired bank is selected. In particular, the bank is selected using the SOFT S0 (bit 0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1 register (40h). The S0 and S1 pins are ignored in this mode. Table 2 illustrates the relationship between the bit settings and the selected bank. For example, if SOFT S0 and SOFT S1 are written to zero, the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of the LD pin. When LD is high, Latch B functions as a flowthrough latch, so the amplifier responds asynchronously to changes in the state of the SOFT S0/S1 bits. These are changed by an I2C write. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by the SOFT S0/S1 bits. A high-to-low transition on LD latches the selected DAC data into Latch B. Because the Soft S0/S1 register is SRAM, subsequent power ups result in the SOFT S0 and SOFT S1 bits being cleared to 0 and, hence, powering up to Bank A.
Mode Selection
The DS3514 mode of operation is determined by two bits located in Control register (CR, register 48h), which is nonvolatile (NV) (EEPROM). In particular, the mode is determined by the MODE0 bit (CR.0) and the MODE1 bit (CR.1). Table 1 illustrates how the two control bits are used to select the operating mode. When shipped from the factory, the DS3514 is programmed with both MODE bits set to zero.
S0/S1 Pin-Controlled Bank-Updating Mode
As shown in the Block Diagram, each channel contains four words of EEPROM that are used to implement the "banking" functionality. Each bank contains unique DAC settings for each channel. When the DS3514 is configured in this operating mode, the desired bank is selected using the S0 and S1 pins as shown in Table 2 where 0 is ground and 1 is VCC. For example, if S0 and S1 are both connected to ground, the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of LD pin. When LD is high, Latch B functions as a flow-through latch, so the amplifier responds asynchronously to changes in
I2C Individual Channel-Control Mode
In this mode the I2C master writes directly to individual channel Latch A registers to update a single DAC (i.e., not banked). The Latch A registers are SRAM and not EEPROM. This allows an unlimited number of write cycles as well as quicker write times since t W only applies to EEPROM writes. As shown in the Memory
Table 1. Operating Modes
MODE1 BIT (CR.1) 0 0 1 MODE0 BIT (CR.0) 0 1 X MODE S0/S1 Pin-Controlled Bank Updating (Factory Default) S0/S1 Bit-Controlled Bank Updating I2C Individual Channel Control
Table 2. Bank Selection Table
BIT OR PIN S1 0 0 1 1 S0 0 1 0 1 VCOM CHANNEL VCOM Bank A VCOM Bank B VCOM Bank C VCOM Bank D GAMMA CHANNELS GM1-GM14 Bank A GM1-GM14 Bank B GM1-GM14 Bank C GM1-GM14 Bank D
______________________________________________________________________________________
11
I2C Gamma and VCOM Buffer with EEPROM
Map, the Latch A registers for each channel are accessed through memory addresses 00-1Ch. Then, like the other modes, the LD pin determines when the DACs are updated. If the LD signal is high, Latch B is flow-through and the DAC is updated immediately. If LD is low, Latch B is loaded from Latch A after a low-tohigh transition on the LD pin. This latter method allows the timing of the DAC update to be controlled by an external signal pulse.
buffered output. The V COM channel's digital potentiometer is composed of 255 equal resistive elements. The relationship between output voltage and DAC setting is illustrated in Table 3a. Unlike the gamma channels, the V COM channel is capable of outputting a range of voltages including both references (VRH and VRL). Each of the gamma channel digital potentiometers, on the other hand, are composed of 1024 equal resistive elements. The extra resistive element prohibits one of the rails from being reached. In particular, gamma channel outputs GM1-GM7 can span from (and including) GLL to 1 LSB away from GLM. Likewise, gamma channel outputs GM8-GM14 span from (and including) GHM to 1 LSB away from GHH. The relationship between output voltage and DAC setting for the gamma channels are also illustrated in Table 3b.
DS3514
VCOM/Gamma Channel Outputs As illustrated in the Block Diagram, the gamma channel outputs are equivalent to a 10-bit digital potentiometer (DAC) with a buffered output. The VCOM channel is equivalent to an 8-bit digital potentiometer (DAC) with a
Table 3a. VCOM DAC Voltage/Data Relationship for Selected Codes
SETTING (HEX) 00h 01h 02h 03h 0Fh 3Fh 7Fh FDh FEh FFh VCOM OUTPUT VOLTAGE VRL VRL + (1/255) x (VRH - VRL) VRL + (2/255) x (VRH - VRL) VRL + (3/255) x (VRH - VRL) VRL + (15/255) x (VRH - VRL) VRL + (63/255) x (VRH - VRL) VRL + (127/255) x (VRH - VRL) VRL + (253/255) x (VRH - VRL) VRL + (254/255) x (VRH - VRL) VRH
Standby Mode
Standby mode (not to be confused with the three DS3514 operating modes) can be used to minimize current consumption. Standby mode is entered by setting the STANDBY bit, which is the MSB of register 41h. The VCOM and gamma outputs are placed in a highimpedance state. Current drawn from the VDD supply in this state is specified as IDDQ. The DS3514 continues to respond to I2C commands, and thus draws some current from VCC when I2C activity is occurring. When the I2C interface is inactive, current drawn from the VCC supply is specified as ICCQ.
Thermal Shutdown
As a safety feature, the DS3514 goes into a thermal shutdown state if the junction temperature ever reaches
Table 3b. Gamma DAC Voltage/Data Relationship for Selected Codes
SETTING (HEX) 000h 001h 002h 003h 00Fh 03Fh 07Fh 0FFh 3FDh 3FEh 3FFh GM1-GM7 OUTPUT VOLTAGE GLM + (0 + 1) x ((GLL - GLM)/1024) GLM + (1 + 1) x ((GLL - GLM)/1024) GLM + (2 + 1) x ((GLL - GLM)/1024) GLM + (3 + 1) x ((GLL - GLM)/1024) GLM + (15 + 1) x ((GLL - GLM)/1024) GLM + (63 + 1) x ((GLL - GLM)/1024) GLM + (127 + 1) x ((GLL - GLM)/1024) GLM + (255 + 1) x ((GLL - GLM)/1024) GLM + (1021 + 1) x ((GLL - GLM)/1024) GLM + (1022 + 1) x ((GLL - GLM)/1024) GLL GM8-GM14 OUTPUT VOLTAGE GHM + (0 + 1) x ((GHH - GHM)/1024) GHM + (1 + 1) x ((GHH - GHM)/1024) GHM + (2 + 1) x ((GHH - GHM)/1024) GHM + (3 + 1) x ((GHH - GHM)/1024) GHM + (15 + 1) x ((GHH - GHM)/1024) GHM + (63 + 1) x ((GHH - GHM)/1024) GHM + (127 + 1) x ((GHH - GHM)/1024) GHM + (255 + 1) x ((GHH - GHM)/1024) GHM + (1021 + 1) x ((GHH - GHM)/1024) GHM + (1022 + 1) x ((GHH - GHM)/1024) GHH
12
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
or exceeds +150C. In this state, the VCOM buffer is disabled (output goes high impedance) until the junction temperature falls below +150C.
DS3514
Slave Address Byte and Address Pin
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 5). The DS3514's slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same I2C bus. Connecting A0 to GND results in a 0 in the corresponding bit position in the slave address. Conversely, connecting A0 to VCC results in a 1 in the corresponding bit position. For example, the DS3514's slave address byte is C0h when A0 is grounded. I2C communication is described in detail in the I2C Serial Interface Description section.
MSB 1 1 0 0 0 0 A0
LSB R/W
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
Figure 5. DS3514 Slave Address Byte
Memory Organization
Memory Description
The list of registers/memory contained in the DS3514 is shown in the Memory Map section. Also shown for each of the registers is the memory type, accessibility,
as well as the power-up default values for volatile locations and factory-programmed defaults for the nonvolatile locations. Additional information regarding reading and writing the memory is located in the I2C Serial Interface Description section.
Memory Map
ADDRESS NAME (HEX) Latch A for VCOM Ch Latch A for GM1 Ch Latch A for GM2 Ch Latch A for GM3 Ch Latch A for GM4 Ch Latch A for GM5 Ch Latch A for GM6 Ch Latch A for GM7 Ch Latch A for GM8 Ch Latch A for GM9 Ch Latch A for GM10 Ch Latch A for GM11 Ch Latch A for GM12 Ch 0h 2h, 3h 4h, 5h 6h, 7h 8h, 9h Ah, Bh Ch, Dh Eh, Fh 10h, 11h 12h, 13h 14h, 15h 16h, 17h 18h, 19h (DEC) 0 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 24, 25 8-Bit I2C Data for VCOM DAC 10-Bit I2C Data for GM1 DAC 10-Bit I2C Data for GM2 DAC 10-Bit I2C Data for GM3 DAC 10-Bit I2C Data for GM4 DAC 10-Bit I2C Data for GM5 DAC 10-Bit I2C Data for GM6 DAC 10-Bit I2C Data for GM7 DAC 10-Bit I2C Data for GM8 DAC 10-Bit I2C Data for GM9 DAC 10-Bit I2C Data for GM10 DAC 10-Bit I2C Data for GM11 DAC 10-Bit I2C Data for GM12 DAC DESCRIPTION TYPE MEMORY OR COMMAND Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile Volatile I2C ACCESS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
______________________________________________________________________________________
13
I2C Gamma and VCOM Buffer with EEPROM DS3514
Memory Map (continued)
ADDRESS NAME (HEX) Latch A for GM13 Ch Latch A for GM14 Ch Reserved Soft S1/S0 Standby Reserved Control Reserved Status Bits Reserved VCOM1-VCOM4 GM1 GDAT1-GDAT4 GM2 GDAT1-GDAT4 GM3 GDAT1-GDAT4 GM4 GDAT1-GDAT4 GM5 GDAT1-GDAT4 GM6 GDAT1-GDAT4 GM7 GDAT1-GDAT4 GM8 GDAT1-GDAT4 GM9 GDAT1-GDAT4 GM10 GDAT1-GDAT4 GM11 GDAT1-GDAT4 GM12 GDAT1-GDAT4 GM13 GDAT1-GDAT4 GM14 GDAT1-GDAT4 Reserved 1Ah, 1Bh 1Ch, 1Dh 1Eh-3Fh 40h 41h 42h-47h 48h 49h 4Ah 4Bh-4Fh 50h, 52h, 54h, 56h 58h-5Fh 60h-67h 68h-6Fh 70h-77h 78h-7Fh 80h-87h 88h-8Fh 90h-97h 98h-9Fh A0h-A7h A8h-AFh B0h-B7h B8h-BFh C0h-C7h C8h-FFh (DEC) 26, 27 28, 29 30-63 64 65 66-71 72 73 74 75-79 10-Bit I2C Data for GM13 DAC 10-Bit I2C Data for GM14 DAC -- Software Bank Select Byte (Bits 1:0) Shutdown Byte -- Control Register (see Table 1) -- Status Bits -- DESCRIPTION TYPE MEMORY OR COMMAND Volatile Volatile -- Volatile Volatile -- NV -- Status -- NV NV NV NV NV NV NV NV NV NV NV NV NV NV NV -- I2C ACCESS R/W R/W -- R/W R/W -- R/W -- R -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W --
80, 82, 84, VCOM EEPROM Data (Four 8-Bit Words) 86 88-95 96-103 104-111 112-119 120-127 128-135 136-143 144-151 152-159 160-167 168-175 176-183 184-191 192-198 200-255 GM1 EEPROM Data (Four 10-Bit Words) GM2 EEPROM Data (Four 10-Bit Words) GM3 EEPROM Data (Four 10-Bit Words) GM4 EEPROM Data (Four 10-Bit Words) GM5 EEPROM Data (Four 10-Bit Words) GM6 EEPROM Data (Four 10-Bit Words) GM7 EEPROM Data (Four 10-Bit Words) GM8 EEPROM Data (Four 10-Bit Words) GM9 EEPROM Data (Four 10-Bit Words) GM10 EEPROM Data (Four 10-Bit Words) GM11 EEPROM Data (Four 10-Bit Words) GM12 EEPROM Data (Four 10-Bit Words) GM13 EEPROM Data (Four 10-Bit Words) GM14 EEPROM Data (Four 10-Bit Words) --
14
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
Detailed Register Descriptions
Soft S0/S1 Register 40h: SOFT S1/S0 Bits FACTORY DEFAULT MEMORY TYPE 40h x BIT 7 Bits 7:2 Reserved These bits are used when in SOFT S0/S1 Bit-Controlled Bank-Updating mode (MODE1 = 0, MODE0 = 1) SOFT S1, SOFT S0: 00 = Selects VCOM and GM1-GM14 Bank A 01 = Selects VCOM and GM1-GM14 Bank B 10 = Selects VCOM and GM1-GM14 Bank C 11 = Selects VCOM and GM1-GM14 Bank D x 00h Volatile x x x x SOFT S1 SOFT S0 BIT 0
DS3514
Bits 1:0
Standby Register 41h: Standby Mode Enable FACTORY DEFAULT MEMORY TYPE 41h STANDBY BIT 7 x 00h Volatile x x x x x x BIT 0
Bit 7 Bits 6:1
STANDBY: 0 = Standby mode disabled 1 = Standby mode enabled Reserved
______________________________________________________________________________________
15
I2C Gamma and VCOM Buffer with EEPROM DS3514
Control Register 48h: Control Register (CR) FACTORY DEFAULT MEMORY TYPE 48h x BIT 7 Bits 7:6 Reserved VCOM and Gamma Bias Current Control Bits (BIAS[1:0]): 00 = 60% 01 = 80% 10 = 100% (default) 11 = 150% Reserved DS3514 Mode (MODE[1:0]): 00 = S0/S1 pins are used to select the desired bank (A-D) (default). 01 = SOFT S0/S1 (bits) are used to select the desired bank (A-D). 1X = Latch A is used to control the DACs. x 20h NV BIAS1 BIAS0 x x MODE1 MODE0 BIT 0
Bits 5:4
Bits 3:2
Bits 1:0
Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins FACTORY DEFAULT MEMORY TYPE 4Ah LD BIT 7 x -- Read Only x x x x S1 S0 BIT 0
GDATx Register: EEPROM Data for the Gamma Channels
This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h-59h). This arrangement is applicable for all the EEPROM data for all gamma channels.
FACTORY DEFAULT MEMORY TYPE 58h 59h GDAT[9] GDAT[1] BIT 7 8000h NV GDAT[8] GDAT[0] GDAT[7] x GDAT[6] x GDAT[5] x GDAT[4] x GDAT[3] x GDAT[2] x BIT 0
16
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
I2C Serial Interface Description
I2C Definitions The following terminology is commonly used to describe I2C data transfers. (See Figure 4 and the I2C Electrical Characteristics for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgment is read using the bit-read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS3514's slave address is determined by the state of the A0 address pin as shown in Figure 5. An address pin connected to GND results in a 0 in the corresponding bit position in the slave address. Conversely, an address pin connected to V CC results in a 1 in the corresponding bit position. When the R/W bit is 0 (such as in C0h), the master is indicating it will write data to the slave. If R/W is set to a 1 (C1h in this case), the master is indicating that it wants to read from the slave. If an incorrect (nonmatching) slave address is written, the DS3514 assumes the master is communicating with another I 2 C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation to the DS3514, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
17
DS3514
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgment during all byte-write operations. When writing to the DS3514 (and if LD = 1), the DAC adjusts to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) is written following the STOP condition at the end of the write command. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3514 can write 1 to 8 bytes (one page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3514 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the DS3514, which allows communication to continue as soon as the DS3514 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM write cycles: The DS3514's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room temperature. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, because requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Recall that the master must NACK the last byte to inform the slave that no additional bytes will be read. See Figure 6 for I2C communication examples. Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a STOP condition.
DS3514
18
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM DS3514
TYPICAL I2C WRITE TRANSACTION MSB START 1 1 0 0 0 0 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND). C0h A) SINGLE-BYTE WRITE -WRITE LATCH A GM8 TO 00h B) SINGLE-BYTE READ -READ LATCH A GM2 08h OOh SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK C1h REPEATED START 80h SLAVE ACK 1000 0 0 0 0 SLAVE ACK STOP 1 1 0 0 0 0 0 1 SLAVE ACK STOP
START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 ACK C0h 02h
DATA I/O STATUS MASTER NACK STOP
START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 0 0 1 0 SLAVE ACK ACK C0h 41h SLAVE ACK 01000 001
C) SINGLE-BYTE WRITE -ENTER STANDBY MODE
START 1 1 0 0 0 0 0 0
C0h D) TWO-BYTE WRITE - WRITE 10h AND 11h TO 80h START 1 1 0 0 0 0 0 0 SLAVE ACK
10h 00010 000 SLAVE ACK
80h 1000 0 0 0 0 SLAVE ACK
80h 1000 0 0 0 0 SLAVE ACK STOP
C0h E) TWO-BYTE READ - READ 10h AND 11h START 1 1 0 0 0 0 0 0 SLAVE ACK
10h 00010 000 SLAVE ACK REPEATED START
C1h 1100 0 0 0 1 SLAVE ACK
DATA MASTER ACK
DATA MASTER NACK STOP
Figure 6. I2C Communication Examples
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3514, decouple all the power-supply pins (VCC and VDD) with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I 2 C Electrical Characteristics are within specification. A typical value for the pullup resistors is 4.7k.
______________________________________________________________________________________
19
I2C Gamma and VCOM Buffer with EEPROM DS3514
Typical Operating Circuit
15V 5V VDD VCC GHH GHM GLM GLL GM1 GM2 GM3 GM4 GM5 GM6 GM7 GM8 GM9 GM10 GM11 GM12 GM13 GM14 VRH 13V VRL 2V VCOM LCD 14.8V 8V 7V 0.2V 14 SOURCE DRIVER
I2C MASTER
SCL SDA S0 S1 LD A0 GND
DS3514
Pin Configuration
GM13 GM12 GM11 GM10 GM9 GM8 GM7 GM6 GM5 GM4 GM3 GM2
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE T4877M+6 DOCUMENT NO. 21-0144
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25 GM14 GLM GLL GHM GHH GND VDD VCOM A0 N.C. VCC N.C. 37 38 39 40 41 42 43 44 45 46 47 48 1 N.C. 2 N.C. 3 N.C. 4 N.C. 5 N.C. 6 VDD 7 VRH 8 VRL 9 N.C. 10 11 12 GND N.C. S1 DS3514 24 23 22 21 20 19 18 17 16 15 GM1 VDD GND GND VCAP GND GND VCC SCL SDA LD S0
48 TQFN-EP
+
*EP
14 13
THIN QFN (7mm x 7mm)
*EXPOSED PAD.
20
______________________________________________________________________________________
I2C Gamma and VCOM Buffer with EEPROM
Revision History
REVISION NUMBER 0 1 REVISION DATE 9/08 10/08 Initial release. Changed the maximum VCC supply current (lCC) specification from 0.5mA to 0.6mA. DESCRIPTION PAGES CHANGED -- 2
DS3514
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of DS3514T

	To Download DS3514T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .